{"jobs":[{"absolute_url":"https://job-boards.greenhouse.io/enchargeai36/jobs/4008053009","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4006530009,"location":{"name":"India"},"metadata":null,"id":4008053009,"updated_at":"2026-07-30T01:00:13-04:00","requisition_id":"INDO9","title":"AI Compiler Engineer","company_name":"EnCharge AI","first_published":"2025-07-10T17:09:06-04:00","language":"en","application_deadline":null,"content":"\u0026lt;p\u0026gt;EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;About the Role\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;EnCharge AI is seeking a highly skilled and experienced AI Compiler Engineer to spearhead the efforts in developing and optimizing graph compilers tailored to cutting-edge AI and ML workloads. You will collaborate with hardware architects, and AI researchers to enhance performance, optimize computation graphs, and enable efficient model deployment on EnCharge’s Inference Accelerators.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Architect, design, and implement optimizations for AI model execution on graph compilers to improve performance, reduce latency, and maximize hardware utilization.\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Work closely with ML researchers, hardware engineers, and software developers to design and deploy AI models, understanding and addressing hardware-specific challenges.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work on performance optimizations for neural network models, such as layer fusion, operator fusion, and graph-level transformations.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop compiler optimizations and passes that convert high-level AI models (e.g., from TensorFlow, PyTorch) into intermediate representations (IR).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Implement parsing, semantic analysis, and IR generation for deep learning frameworks.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Research and integrate the latest advancements in compiler design, ML model optimizations, and hardware acceleration into graph compilers.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Provide leadership, mentorship, and technical guidance to a team of engineers focused on graph compiler optimizations.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or related field (Ph.D. preferred).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;3+ years in compiler development, with a strong focus on AI or ML graph compilers.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency in AI graph compiler frameworks (e.g., MLIR, Torch-FX)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Solid background in hardware architectures (e.g., GPUs, TPUs, ASICs) and optimization techniques such as fusion, quantization, and tiling.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with neural networks operators and code generation.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of intermediate representations, code parsing, and semantic analysis in compiler design.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency in C++, Python, or other programming languages commonly used in compiler development.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Open-source contributions to AI software frameworks and libraries is a plus\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Demonstrated experience leading and mentoring engineering teams with successful project delivery.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;EnchargeAI is an equal employment opportunity employer in the United States.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;","departments":[{"id":4005972009,"name":"Software","child_ids":[],"parent_id":null}],"offices":[{"id":4030255009,"name":"India","location":null,"child_ids":[4063997009,4063998009],"parent_id":null}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":"http://app9.greenhouse.io/ai_opt_out_request/job_post/4008053009/ai_opt_out"},{"absolute_url":"https://job-boards.greenhouse.io/enchargeai36/jobs/4280792009","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4164876009,"location":{"name":"Remote-US, Canada, Germany and Norway"},"metadata":null,"id":4280792009,"updated_at":"2026-09-21T18:05:13-04:00","requisition_id":"10171","title":"AI Compiler Engineer","company_name":"EnCharge AI","first_published":"2026-06-09T19:46:28-04:00","language":"en","application_deadline":null,"content":"\u0026lt;p\u0026gt;EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;About the Role\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;EnCharge AI is seeking a highly skilled and experienced AI Compiler Engineer to spearhead the efforts in developing and optimizing graph compilers tailored to cutting-edge AI and ML workloads. You will collaborate with hardware architects, and AI researchers to enhance performance, optimize computation graphs, and enable efficient model deployment on EnCharge’s Inference Accelerators.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Architect, design, and implement optimizations for AI model execution on graph compilers to improve performance, reduce latency, and maximize hardware utilization.\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Work closely with ML researchers, hardware engineers, and software developers to design and deploy AI models, understanding and addressing hardware-specific challenges.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work on performance optimizations for neural network models, such as layer fusion, operator fusion, and graph-level transformations.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop compiler optimizations and passes that convert high-level AI models (e.g., from TensorFlow, PyTorch) into intermediate representations (IR).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Implement parsing, semantic analysis, and IR generation for deep learning frameworks.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Research and integrate the latest advancements in compiler design, ML model optimizations, and hardware acceleration into graph compilers.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Provide leadership, mentorship, and technical guidance to a team of engineers focused on graph compiler optimizations.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or related field (Ph.D. preferred).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;3+ years in compiler development, with a strong focus on AI or ML graph compilers.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency in AI graph compiler frameworks (e.g., MLIR, Torch-FX)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Solid background in hardware architectures (e.g., GPUs, TPUs, ASICs) and optimization techniques such as fusion, quantization, and tiling.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with neural networks operators and code generation.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of intermediate representations, code parsing, and semantic analysis in compiler design.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency in C++, Python, or other programming languages commonly used in compiler development.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Open-source contributions to AI software frameworks and libraries is a plus\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Demonstrated experience leading and mentoring engineering teams with successful project delivery.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;EnCharge AI is an equal employment opportunity employer in the United States.\u0026lt;br\u0026gt;\u0026lt;br\u0026gt;The salary range for this position is $190,000 to $255,000 USD per year.\u0026amp;nbsp;(Per Year: $195,000 to $265,000 CAD | €110,000 to €160,000 EUR | 1,206,458 to 1,754,848 NOK)\u0026lt;br\u0026gt;Actual compensation offered will be determined based on job-related knowledge, skills, and experience.\u0026lt;/p\u0026gt;","departments":[{"id":4005972009,"name":"Software","child_ids":[],"parent_id":null}],"offices":[{"id":4006051009,"name":"Canada","location":null,"child_ids":[],"parent_id":null},{"id":4006052009,"name":"Germany","location":null,"child_ids":[],"parent_id":null},{"id":4006053009,"name":"Norway","location":null,"child_ids":[],"parent_id":null},{"id":4006050009,"name":"Remote - US","location":null,"child_ids":[],"parent_id":null}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":"http://app9.greenhouse.io/ai_opt_out_request/job_post/4280792009/ai_opt_out"},{"absolute_url":"https://job-boards.greenhouse.io/enchargeai36/jobs/4008063009","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4006538009,"location":{"name":"U.S., Canada, Germany, Norway"},"metadata":null,"id":4008063009,"updated_at":"2026-07-30T01:00:13-04:00","requisition_id":"10114","title":"AI Runtime Engineer","company_name":"EnCharge AI","first_published":"2025-07-10T17:09:17-04:00","language":"en","application_deadline":null,"content":"\u0026lt;p\u0026gt;EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;About the Role\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;EnCharge AI is seeking an AI Runtime Engineer to develop and optimize the execution stack for our next-generation AI accelerator. In this role, you will work on low-latency, high-performance runtime software that enables efficient execution of deep learning models on specialized hardware. You will collaborate with hardware, compiler, and AI framework teams to deliver optimized AI inference and training performance across cloud and edge environments.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Develop and optimize the AI runtime software stack for executing deep learning workloads on AI accelerators.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Implement task scheduling, memory management, and kernel execution strategies for efficient computation.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Optimize data movement between host and device using PCIe, DMA, shared memory.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Design and implement high-performance APIs for AI Inference frameworks such as OpenVino, ONNX Runtime, vLLM\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work on graph execution optimizations, including kernel fusion, pipelining, tensor tiling, and caching.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Integrate runtime components with AI compilers (LLVM, MLIR, XLA, TVM) for optimized execution.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ensure scalability and reliability of the AI runtime for cloud-based and edge AI deployments.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or a related field.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;3+ years of experience in developing low-level runtime software for AI accelerators, GPUs, or HPC systems.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong proficiency in C/C++ and low-level systems programming.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep understanding of task scheduling, concurrency, and memory hierarchy.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with hardware-aware optimizations and dataflow architectures.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with deep learning execution frameworks (ONNX Runtime, TensorRT, TVM, OpenVINO).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with low-latency, high-throughput workload execution for AI models.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong debugging and profiling skills for optimizing AI execution performance.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Exposure to AI model deployment pipelines (Triton, TensorFlow Serving).\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;EnchargeAI is an equal employment opportunity employer in the United States.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;","departments":[{"id":4005972009,"name":"Software","child_ids":[],"parent_id":null}],"offices":[{"id":4006051009,"name":"Canada","location":null,"child_ids":[],"parent_id":null},{"id":4006052009,"name":"Germany","location":null,"child_ids":[],"parent_id":null},{"id":4006053009,"name":"Norway","location":null,"child_ids":[],"parent_id":null},{"id":4006050009,"name":"Remote - US","location":null,"child_ids":[],"parent_id":null}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":"http://app9.greenhouse.io/ai_opt_out_request/job_post/4008063009/ai_opt_out"},{"absolute_url":"https://job-boards.greenhouse.io/enchargeai36/jobs/4409175009","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4236810009,"location":{"name":"India"},"metadata":null,"id":4409175009,"updated_at":"2026-09-16T19:48:41-04:00","requisition_id":"IND16","title":"AI Software Engineer, Agent Harness","company_name":"EnCharge AI","first_published":"2026-09-16T19:48:40-04:00","language":"en","application_deadline":null,"content":"\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;AI Software Engineer, Agent Harness\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Location: Bengaluru, Karnataka\u0026amp;nbsp;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; (or throughout India remote-friendly with travel)\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;About EnCharge AI\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;EnCharge AI is building the next generation AI platform. Our novel in-memory-computing architecture delivers a 10x step-function improvement in compute energy efficiency and performance for AI inference workloads. As the demands of artificial intelligence move beyond today\u0026#39;s models, we believe fundamental underlying infrastructure must evolve. We are an experienced team of AI researchers, silicon \u0026amp;amp; systems engineers, and architects backed by leading investors, poised to become the essential platform for the next wave of AI innovation.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;The Opportunity\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;We serve open-weight models and our own bespoke checkpoints on EnCharge hardware. The models change often, and the harness around them needs to keep up. You own this layer that runs agents against files, tools, documents with permissions, memory, unattended execution, and real outputs. It will be assembled from a combination of open-source and bespoke code.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Own the harness architecture end to end — agent loop, safe execution, context management, knowledge base, memory, permissions, orchestration, outputs, interfaces, observability — one component per layer, with clear interfaces so layers can be swapped.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Build the pieces with no open-source equivalent e.g. session semantics, enforced permissions, memory in a human-editable file, orchestrator, and outputs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Keep pace with the models: adapters, prompt formats, tool-call schemas, stop conditions, benchmarking and evaluation.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Make tool use reliable across models of uneven tool-calling quality — validation, repair, retries, fallbacks.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop agents, tools, and MCP servers for internal and customer use cases, and review them for security before they ship.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Build the evaluation harness: task suites, regression runs on every model or harness change, cost and latency per task alongside quality.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Define the interfaces: session API, CLI, GUI, and an endpoint existing tools can point at.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;10+ years of software engineering experience in backend systems or ML infrastructure\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong Python and at least one systems language (e.g., Go, Rust, C++)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Have shipped and operated an agent loop in production — tool use, multi-step workflows, unattended runs\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on with RAG, context management, and memory for LLM applications\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with sandboxing, isolation, and permission models for automated systems\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Have run open-weight models yourself and understand how quantization and serving choices change model behavior\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Comfort in fast-moving, ambiguous environments where you define the roadmap; strong product instincts\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Nice to Have\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Contributions to open-source agent harnesses or coding agents\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with agent benchmarks (e.g., SWE-bench, Terminal-Bench) and building internal task suites\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;MoE serving familiarity e.g. expert placement, tensor parallelism, quantization etc.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Observability for LLM systems\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Document parsing and indexing pipelines\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Desktop or GUI application experience\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;","departments":[{"id":4005972009,"name":"Software","child_ids":[],"parent_id":null}],"offices":[{"id":4030255009,"name":"India","location":null,"child_ids":[4063997009,4063998009],"parent_id":null}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":"http://app9.greenhouse.io/ai_opt_out_request/job_post/4409175009/ai_opt_out"},{"absolute_url":"https://job-boards.greenhouse.io/enchargeai36/jobs/4008062009","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4006536009,"location":{"name":"U.S., Canada, Germany, Norway"},"metadata":null,"id":4008062009,"updated_at":"2026-07-30T01:00:13-04:00","requisition_id":"10115","title":"Device Driver Engineer","company_name":"EnCharge AI","first_published":"2025-07-10T17:09:18-04:00","language":"en","application_deadline":null,"content":"\u0026lt;p\u0026gt;EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;About the Role\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;EnCharge AI is seeking a highly skilled Device Driver Engineer to design and implement high-performance driver stack for our cutting-edge AI accelerator hardware. In this role, you will work closely with hardware, firmware, and AI software teams to develop low-latency, high-bandwidth communication between the host system and AI accelerator.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Develop, optimize, and maintain Linux/Windows PCIe device drivers for AI accelerators.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Implement low-level hardware interactions, DMA, memory management, and interrupt handling.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work on driver optimizations to reduce latency and improve throughput for AI workloads.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Debug and troubleshoot PCIe protocol, kernel panics, crashes, and performance bottlenecks.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with hardware, firmware, and AI software teams to define driver interfaces.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ensure compliance with PCIe standards (Gen4/Gen5), SR-IOV, BAR memory mapping, and IOMMU.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support virtualization (VFIO, SR-IOV, DPUs) and containerized environments (Kubernetes, Docker, etc.).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop tools for profiling, debugging, and monitoring driver performance.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Contribute to open-source kernel modules if applicable.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or a related field.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;3+ years of experience in device driver development for Linux and/or Windows.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong experience with PCIe-based hardware, including BAR regions, DMA, interrupts, and MMIO.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency in C/C++ and kernel-mode programming (Linux Kernel, Windows WDDM/WDF/MCDM).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with AI-specific accelerators (e.g., GPUs, NPUs, TPUs) is a plus.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of low-level debugging tools (gdb, perf, ftrace, dmesg, PCIe analyzers).\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Understanding of multi-threading, synchronization, and memory management in kernel space.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with high-performance AI/ML workloads is a plus.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience in hypervisor interactions, VFIO, and passthrough solutions.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of secure boot, firmware updates, and trusted execution environments (TEE).\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;EnchargeAI is an equal employment opportunity employer in the United States.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;","departments":[{"id":4005972009,"name":"Software","child_ids":[],"parent_id":null}],"offices":[{"id":4006051009,"name":"Canada","location":null,"child_ids":[],"parent_id":null},{"id":4006052009,"name":"Germany","location":null,"child_ids":[],"parent_id":null},{"id":4006053009,"name":"Norway","location":null,"child_ids":[],"parent_id":null},{"id":4006050009,"name":"Remote - US","location":null,"child_ids":[],"parent_id":null}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":"http://app9.greenhouse.io/ai_opt_out_request/job_post/4008062009/ai_opt_out"},{"absolute_url":"https://job-boards.greenhouse.io/enchargeai36/jobs/4008069009","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4006542009,"location":{"name":"U.S., Canada, Germany, Norway"},"metadata":null,"id":4008069009,"updated_at":"2026-07-30T01:00:14-04:00","requisition_id":"10111","title":"Embedded SW Engineer","company_name":"EnCharge AI","first_published":"2025-07-10T17:09:18-04:00","language":"en","application_deadline":null,"content":"\u0026lt;p\u0026gt;EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;About the Role\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;EnCharge AI is looking for an Embedded SW Engineer to develop the firmware for our Edge AI processors. The candidate must possess an excellent understanding of computer architecture and operating system concepts including, but not limited to, memory management, virtualization and PCIe address space. The role includes designing and developing the core Firmware for various parts of the SOC. The candidate must possess strong communication skills to interface with Runtime, Architecture and H/W teams.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Develop the critical pieces of EAI Firmware used to deploy inference jobs on EAI processors\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Validate different IP blocks on the SOC\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Evaluate and integrate third-party device drivers to interface with EnCharge’s SW stack\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work closely with the Runtime, Hardware and Architecture teams define the driver architecture\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelors in EE/CS\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Advanced programming skills in C/C++ for operating system kernel \u0026amp;amp; systems development\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Understanding of RISC-V architecture is a plus\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Exposure to PCIe BAR and IOMMU architecture\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Exposure to virtualization and hypervisor technologies\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep understanding of operating systems concepts, data structures, x86-64 and accelerator architectures\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with low-level debug tools as well as emulators and simulators\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience running, analyzing, and tuning system performance benchmarks\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent verbal and written communication skills\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;EnchargeAI is an equal employment opportunity employer in the United States.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;","departments":[{"id":4005972009,"name":"Software","child_ids":[],"parent_id":null}],"offices":[{"id":4006051009,"name":"Canada","location":null,"child_ids":[],"parent_id":null},{"id":4006052009,"name":"Germany","location":null,"child_ids":[],"parent_id":null},{"id":4006053009,"name":"Norway","location":null,"child_ids":[],"parent_id":null},{"id":4006050009,"name":"Remote - US","location":null,"child_ids":[],"parent_id":null}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":"http://app9.greenhouse.io/ai_opt_out_request/job_post/4008069009/ai_opt_out"},{"absolute_url":"https://job-boards.greenhouse.io/enchargeai36/jobs/4369637009","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4213585009,"location":{"name":"Canada, Remote - US"},"metadata":null,"id":4369637009,"updated_at":"2026-08-13T16:50:59-04:00","requisition_id":"10017A","title":"Lead DFT Engineer","company_name":"EnCharge AI","first_published":"2026-08-13T16:43:59-04:00","language":"en","application_deadline":null,"content":"\u0026lt;p\u0026gt;EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Lead DFT Engineer\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Job Description:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Developing silicon for edge-to-cloud computing isn\u0026#39;t just about speed; it’s about balancing high-performance data processing with extreme power efficiency and reliability in remote environments.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As the Design for Test (DFT) Lead, you will be the architect of our testing strategy, ensuring our data center chips are flawlessly manufacturable and resilient enough for edge deployment.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Architectural Leadership: Define and implement the end-to-end DFT architecture for complex SoCs, including Hierarchical DFT, Scan compression, \u0026lt;em\u0026gt;\u0026lt;strong\u0026gt;Boundary Scan\u0026lt;/strong\u0026gt;\u0026lt;/em\u0026gt;\u0026amp;nbsp;and MBIST.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Edge-Specific Reliability: Develop strategies for In-System Test (IST) and power-on self-test (POST) to ensure chip health in remote edge data centers.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Implementation \u0026amp;amp; Flow: Oversee scan insertion, ATPG (Stuck-at, Transition, Path Delay), and\u0026amp;nbsp;\u0026lt;em\u0026gt;\u0026lt;strong\u0026gt;Memory\u0026lt;/strong\u0026gt;\u0026lt;/em\u0026gt;/Logic BIST.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Cross-Functional Synergy: Collaborate with Design, Physical Design, and Yield teams to ensure high test coverage while minimizing area overhead and power impact\u0026amp;nbsp;\u0026lt;em\u0026gt;\u0026lt;strong\u0026gt;as well as timing analysis\u0026lt;/strong\u0026gt;\u0026lt;/em\u0026gt;.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Post-Silicon Validation: Lead the bring-up and debug phase on ATE (Automated Test Equipment) to root-cause silicon failures and optimize test time.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Technical Requirements:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Experience: 12+ years in DFT, with at least 2 years in a leadership or principal role. Bachelor’s degree in a related field.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Tools: Mastery of industry-standard tools (e.g., Synopsys TestMAX, Siemens/Mentor Tessent, Cadence Modus).\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Memory \u0026amp;amp; Logic Test: Deep expertise in MBIST (Memory Built-In Self-Test) with repair capabilities,\u0026amp;nbsp;\u0026lt;em\u0026gt;\u0026lt;strong\u0026gt;SCAN\u0026lt;/strong\u0026gt;\u0026lt;/em\u0026gt;,\u0026amp;nbsp;\u0026lt;em\u0026gt;\u0026lt;strong\u0026gt;IJTAG (IEEE 1687)\u0026lt;/strong\u0026gt;\u0026lt;/em\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;em\u0026gt;\u0026amp;nbsp;\u0026lt;/em\u0026gt;\u0026lt;/strong\u0026gt;and boundary scan (IEEE 1149.1/6).\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Advanced Nodes: Proven track record with FinFET nodes (7nm, 5nm, or below).\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Low Power: Experience managing DFT in multi-voltage/power-gated designs—crucial for edge efficiency.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;EnCharge AI is an equal employment opportunity employer in the United States.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;The salary range for this position is $200,000 to $250,000 USD/CAN per year.\u0026amp;nbsp;Actual compensation offered will be determined based on job-related knowledge, skills, and experience.\u0026lt;/p\u0026gt;","departments":[{"id":4005974009,"name":"Hardware","child_ids":[],"parent_id":null}],"offices":[{"id":4006051009,"name":"Canada","location":null,"child_ids":[],"parent_id":null},{"id":4006050009,"name":"Remote - US","location":null,"child_ids":[],"parent_id":null}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":"http://app9.greenhouse.io/ai_opt_out_request/job_post/4369637009/ai_opt_out"},{"absolute_url":"https://job-boards.greenhouse.io/enchargeai36/jobs/4136976009","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4090260009,"location":{"name":"Bangalore"},"metadata":null,"id":4136976009,"updated_at":"2026-07-30T01:00:14-04:00","requisition_id":"10161","title":"Lead DFT Engineer (Edge Computing)","company_name":"EnCharge AI","first_published":"2026-02-18T18:26:24-05:00","language":"en","application_deadline":null,"content":"\u0026lt;p\u0026gt;EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;ms-outlook-mobile-reference-message skipProofing\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Job Description\u0026lt;/strong\u0026gt;: Lead DFT Engineer (Edge Computing)\u0026lt;br\u0026gt;Developing silicon for Edge Computing isn\u0026#39;t just about speed; it’s about balancing high-performance data processing with extreme power efficiency and reliability in remote environments.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;ms-outlook-mobile-reference-message skipProofing\u0026quot;\u0026gt;As the Design for Test (DFT) Lead, you will be the architect of our testing strategy, ensuring our data center chips are flawlessly manufacturable and resilient enough for edge deployment.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;ms-outlook-mobile-reference-message skipProofing\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;br\u0026gt;\u0026lt;/strong\u0026gt;Architectural Leadership: Define and implement the end-to-end DFT architecture for complex SoCs, including Hierarchical DFT, Scan compression,\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;em\u0026gt;Boundary Scan\u0026lt;/em\u0026gt;\u0026lt;/strong\u0026gt;\u0026amp;nbsp;and MBIST.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;ms-outlook-mobile-reference-message skipProofing\u0026quot;\u0026gt;Edge-Specific Reliability: Develop strategies for In-System Test (IST) and power-on self-test (POST) to ensure chip health in remote edge data centers.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;ms-outlook-mobile-reference-message skipProofing\u0026quot;\u0026gt;Implementation \u0026amp;amp; Flow: Oversee scan insertion, ATPG (Stuck-at, Transition, Path Delay), and\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;em\u0026gt;Memory\u0026lt;/em\u0026gt;\u0026lt;/strong\u0026gt;/Logic BIST.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;ms-outlook-mobile-reference-message skipProofing\u0026quot;\u0026gt;Cross-Functional Synergy: Collaborate with Design, Physical Design, and Yield teams to ensure high test coverage while minimizing area overhead and power impact\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;em\u0026gt;as well as timing analysis\u0026lt;/em\u0026gt;\u0026lt;/strong\u0026gt;.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;ms-outlook-mobile-reference-message skipProofing\u0026quot;\u0026gt;Post-Silicon Validation: Lead the bring-up and debug phase on ATE (Automated Test Equipment) to root-cause silicon failures and optimize test time.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;ms-outlook-mobile-reference-message skipProofing\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Technical Requirements\u0026lt;/strong\u0026gt;\u0026lt;br\u0026gt;Experience: 12+ years in DFT, with at least 2 years in a leadership or principal role.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;ms-outlook-mobile-reference-message skipProofing\u0026quot;\u0026gt;Tools: Mastery of industry-standard tools (e.g., Synopsys TestMAX, Siemens/Mentor Tessent, or Cadence Modus).\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;ms-outlook-mobile-reference-message skipProofing\u0026quot;\u0026gt;Memory \u0026amp;amp; Logic Test: Deep expertise in MBIST (Memory Built-In Self-Test) with repair capabilities,\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;em\u0026gt;SCAN\u0026lt;/em\u0026gt;\u0026lt;/strong\u0026gt;,\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;em\u0026gt;IJTAG (IEEE 1687)\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/em\u0026gt;\u0026lt;/strong\u0026gt;and boundary scan (IEEE 1149.1/6).\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;ms-outlook-mobile-reference-message skipProofing\u0026quot;\u0026gt;Advanced Nodes: Proven track record with FinFET nodes (7nm, 5nm, or below).\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;ms-outlook-mobile-reference-message skipProofing\u0026quot;\u0026gt;Low Power: Experience managing DFT in multi-voltage/power-gated designs—crucial for edge efficiency.\u0026lt;/p\u0026gt;","departments":[{"id":4005974009,"name":"Hardware","child_ids":[],"parent_id":null}],"offices":[{"id":4030255009,"name":"India","location":null,"child_ids":[4063997009,4063998009],"parent_id":null}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":"http://app9.greenhouse.io/ai_opt_out_request/job_post/4136976009/ai_opt_out"},{"absolute_url":"https://job-boards.greenhouse.io/enchargeai36/jobs/4210887009","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4123716009,"location":{"name":"Bangalore"},"metadata":null,"id":4210887009,"updated_at":"2026-07-30T01:00:15-04:00","requisition_id":"IND07","title":"Physical Design Engineer","company_name":"EnCharge AI","first_published":"2026-04-07T19:18:13-04:00","language":"en","application_deadline":null,"content":"\u0026lt;p\u0026gt;EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.\u0026lt;/p\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Physical Design Engineer (2-4 Years Experience)\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;We are looking for a high-caliber\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;Physical Design Engineer\u0026lt;/strong\u0026gt;\u0026amp;nbsp;to join our fast-paced startup team. This role is designed for \u0026quot;top 1%\u0026quot; talent—engineers from\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;tier-1 universities (IIT/NIT/BITS or equivalent)\u0026lt;/strong\u0026gt;\u0026amp;nbsp;who possess a relentless \u0026quot;go-getter\u0026quot; attitude and the critical thinking skills required to solve complex, next-generation silicon challenges.\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;If you are eager to move beyond standard digital flows into the future of\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;AI-driven automation\u0026lt;/strong\u0026gt;, this is your playground.\u0026lt;/div\u0026gt;\n\u0026lt;hr\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;ul data-path-to-node=\u0026quot;5\u0026quot;\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;End-to-End Ownership:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Drive RTL-to-GDSII implementation, including floorplanning, placement, CTS, routing, and physical verification (LVS/DRC/ERC).\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Performance Optimization:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Execute high-performance design closure focusing on\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;PPA (Power, Performance, Area)\u0026lt;/strong\u0026gt;\u0026amp;nbsp;targets in advanced process nodes ( 3nm or below)\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Static Timing Analysis (STA):\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Perform comprehensive timing closure, including signal integrity, crosstalk analysis, and\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;CPPR (Common Path Pessimism Removal)\u0026lt;/strong\u0026gt;\u0026amp;nbsp;optimization.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Power Integrity:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Conduct IR-drop analysis (Static/Dynamic) and EM (Electromigration) checks to ensure robust power delivery.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Innovation:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Develop and integrate\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;AI/ML-based automation scripts\u0026lt;/strong\u0026gt;\u0026amp;nbsp;to optimize the physical design flow and reduce turnaround time.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Qualifications \u0026amp;amp; Requirements\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;ul data-path-to-node=\u0026quot;7\u0026quot;\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Education:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;B.Tech/M.Tech\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;in Electrical/Electronics Engineering from a\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;Top Tier University\u0026lt;/strong\u0026gt;.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Experience:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;2–4 years of hands-on experience in Physical Design within the semiconductor industry.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Tool Expertise:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Expert-level proficiency in industry-standard tools (Preferred\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;Innovus\u0026lt;/strong\u0026gt;).\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Technical Depth:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Strong understanding of multi-corner multi-mode (MCMM) closure, low-power design techniques (UPF/CPF), and physical verification.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Mindset:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;A proven \u0026quot;go-getter\u0026quot; who is diligent, detail-oriented, and capable of taking complete ownership of blocks under tight deadlines.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;The \u0026quot;Plus\u0026quot;:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Proficiency in Python/Tcl and experience using\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;AI/ML models for EDA tool automation\u0026lt;/strong\u0026gt;\u0026amp;nbsp;or predictive PPA analysis.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;Location: Bangalore\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;","departments":[{"id":4005974009,"name":"Hardware","child_ids":[],"parent_id":null}],"offices":[{"id":4030255009,"name":"India","location":null,"child_ids":[4063997009,4063998009],"parent_id":null}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":"http://app9.greenhouse.io/ai_opt_out_request/job_post/4210887009/ai_opt_out"},{"absolute_url":"https://job-boards.greenhouse.io/enchargeai36/jobs/4139138009","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4091428009,"location":{"name":"Bangalore"},"metadata":null,"id":4139138009,"updated_at":"2026-07-30T01:00:14-04:00","requisition_id":"10166","title":"Principal Physical Design Engineer (RTL-to-GDSII)","company_name":"EnCharge AI","first_published":"2026-02-19T12:36:36-05:00","language":"en","application_deadline":null,"content":"\u0026lt;p\u0026gt;EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.\u0026lt;/p\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;strong\u0026gt;Job Title: Principal Physical Design Engineer (RTL-to-GDSII)\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;strong\u0026gt;Experience:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;14+ Years\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;strong\u0026gt;Technology Focus:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Sub-5nm (3nm/2nm)\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;strong\u0026gt;Location:\u0026lt;/strong\u0026gt;\u0026amp;nbsp; Bangalore Hybrid\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;strong\u0026gt;The Vision\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;We are seeking a\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;Principal Physical Design Engineer\u0026lt;/strong\u0026gt;\u0026amp;nbsp;who thrives on complexity and rejects the \u0026quot;black box\u0026quot; approach to EDA tools. This role is for a\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;First Principles thinker\u0026lt;/strong\u0026gt;\u0026amp;nbsp;who questions the status quo. If a standard flow isn\u0026#39;t yielding the desired PPA (Power, Performance, Area), you dive into the PDK, the tool algorithms, and the methodology to find a better way. You are responsible for transforming raw RTL into world-class silicon by eliminating systemic bottlenecks and building a scalable, predictable path to GDSII.\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;br\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Full-Flow Ownership:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Lead the implementation of massive, high-speed blocks/SoCs from Synthesis through Sign-off using the\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;Cadence Digital Suite\u0026lt;/strong\u0026gt;.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;PPA Optimization:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Push the theoretical limits of the PDK and tools. You will analyze and optimize the interplay between library cells, metal stacks, and tool engines to squeeze out every millivolt and picosecond.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Methodology \u0026amp;amp; Scalability:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Build and refine a \u0026quot;Push-Button\u0026quot; style execution methodology that is robust, repeatable, and minimizes manual \u0026quot;human-in-the-loop\u0026quot; iterations.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional \u0026quot;Left-Shift\u0026quot;:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Collaborate with RTL, Architecture, and DFT teams to influence design decisions early. You will drive a holistic approach where physical constraints inform the architecture, not just react to it.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Bottleneck Elimination:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Identify \u0026quot;drag\u0026quot; in the execution pipeline—whether it’s runtime, convergence issues, or tool limitations—and architect automated solutions to bypass them.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;div\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;strong\u0026gt;Technical Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;table id=\u0026quot;x_table_0\u0026quot; border=\u0026quot;0\u0026quot; cellspacing=\u0026quot;0\u0026quot; cellpadding=\u0026quot;0\u0026quot;\u0026gt;\n\u0026lt;tbody\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td\u0026gt;\n\u0026lt;div\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td\u0026gt;\n\u0026lt;div\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;strong\u0026gt;Experience\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td\u0026gt;\n\u0026lt;div\u0026gt;14+ years in Physical Design with a proven track record of multiple\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;sub-5nm\u0026lt;/strong\u0026gt;\u0026amp;nbsp;tape-outs.\u0026lt;/div\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;strong\u0026gt;Tool Suite\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td\u0026gt;\n\u0026lt;div\u0026gt;Mastery of\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;Cadence Innovus\u0026lt;/strong\u0026gt;, Tempus, Joules, Pegasus, and Voltus.\u0026lt;/div\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;strong\u0026gt;Advanced Nodes\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td\u0026gt;\n\u0026lt;div\u0026gt;Deep understanding of sub-5nm physics: EUV constraints, multi-patterning, FinFET\u0026amp;nbsp; \u0026amp;nbsp;and IR/EM challenges.\u0026lt;/div\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;strong\u0026gt;Sign-off\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;Expert-level knowledge in Static Timing Analysis (STA), Physical Verification (PV), and Power Integrity (PI) and ECO methodology.\u0026lt;/div\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;strong\u0026gt;Scripting\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td\u0026gt;\n\u0026lt;div\u0026gt;Proficiency in\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;Tcl and Python\u0026lt;/strong\u0026gt;\u0026amp;nbsp;to develop custom flow wrappers and data-mining tools for PPA analysis.\u0026lt;/div\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;/tbody\u0026gt;\n\u0026lt;/table\u0026gt;\n\u0026lt;div\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;strong\u0026gt;Soft Skills \u0026amp;amp; Leadership\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Holistic Thinking:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;You look at the \u0026quot;Big Picture.\u0026quot; You solve timing by fixing the floorplan or the RTL/ARCH\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Influence \u0026amp;amp; Rapport:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;You can build strong technical bridges with Front-End, Foundry, and EDA vendors to align on a unified execution strategy.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Critical Thinking:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;You operate on first principles. You don\u0026#39;t just follow a vendor\u0026#39;s \u0026quot;Best Practices\u0026quot; if they don\u0026#39;t make sense for our specific architecture.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Mentorship:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;You act as a force multiplier, elevating the technical competence of the entire PD team.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;div\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;strong\u0026gt;Why Join This Team?\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;In this role, you aren\u0026#39;t just a \u0026quot;user\u0026quot; of tools; you are an engineer who shapes how silicon is built. You will have the autonomy to overhaul legacy flows and the resources to execute on cutting-edge nodes that define the industry\u0026#39;s future.\u0026lt;/div\u0026gt;","departments":[{"id":4005974009,"name":"Hardware","child_ids":[],"parent_id":null}],"offices":[{"id":4030255009,"name":"India","location":null,"child_ids":[4063997009,4063998009],"parent_id":null}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":"http://app9.greenhouse.io/ai_opt_out_request/job_post/4139138009/ai_opt_out"},{"absolute_url":"https://job-boards.greenhouse.io/enchargeai36/jobs/4322288009","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4188626009,"location":{"name":"Bangalore (Hybrid), India (Remote)"},"metadata":null,"id":4322288009,"updated_at":"2026-07-30T01:00:15-04:00","requisition_id":"IND12","title":"Principal SOC Physical Verification \u0026 Integration Specialist","company_name":"EnCharge AI","first_published":"2026-07-16T18:21:57-04:00","language":"en","application_deadline":null,"content":"\u0026lt;p\u0026gt;EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.\u0026lt;/p\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\n\u0026lt;hr\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;The Role\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;We are seeking a thorough \u0026lt;strong\u0026gt;SOC Physical Verification \u0026amp;amp; Integration Specialist\u0026lt;/strong\u0026gt; to drive the physical assembly and signoff of our next-generation SOCs. In this role, you will own the physical integration strategy from the floorplan stage through to tapeout, ensuring seamless assembly of massive multi-hierarchical blocks. You will act as the critical bridge between block-level implementation, top-level integration, and final foundry signoff, ensuring that complex physical bottlenecks are resolved without compromising power, performance, or area (PPA).\u0026lt;/p\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Top-Level Physical Integration:\u0026lt;/strong\u0026gt; Drive the full-chip physical assembly of very large-scale SOCs (e.g., multi-billion transistor designs). Manage top-level floorplanning, bump planning, global power grid (PG) integration, and top-level clock/routing integration.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Hierarchical Verification Methodology:\u0026lt;/strong\u0026gt; Architect and deploy highly efficient, hierarchical physical verification (PV) flows. Define the boundary conditions, abstraction models, and interface rules required to assemble heavily partitioned, massive-scale designs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Signoff Execution \u0026amp;amp; Debugging:\u0026lt;/strong\u0026gt; Own full-chip DRC, LVS, ERC, Antenna, ESD, and Latch-up signoff using industry-standard tools (e.g., Siemens Calibre) at advanced process nodes (5nm, 3nm, or below).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional Collaboration:\u0026lt;/strong\u0026gt; Partner tightly with the Physical Design (PD) and Static Timing Analysis (STA) teams. Proactively resolve integration conflicts—such as top-level routing congestion or interface timing violations—ensuring that physical fixes do not disrupt timing closure.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Design Rule Co-Optimization:\u0026lt;/strong\u0026gt; Work directly with foundry partners to interpret complex design rules and waive or resolve edge-case violations specific to reticle-limit designs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Automation \u0026amp;amp; Flow Development:\u0026lt;/strong\u0026gt; Develop robust scripts and utilities to automate physical integration tasks, database merging, and PV result parsing to accelerate the tapeout cycle.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;hr\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Required Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;ul data-path-to-node=\u0026quot;9\u0026quot;\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Experience: \u0026lt;/strong\u0026gt;14 + years of hands-on experience in SOC physical design and physical verification, with a proven track record of taping out very large, complex SOCs (e.g., Datacenter, AI accelerators, or High-Performance Compute chips).\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Technical Domain Expertise\u0026lt;/strong\u0026gt;: * Deep understanding of the entire RTL-to-GDSII flow, with expert-level knowledge of physical integration challenges in flat vs. hierarchical methodologies.\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong foundational understanding of Physical Design and Static Timing Analysis (STA) to effectively communicate with implementation teams and assess the timing impact of PV fixes.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Tool Proficiency: \u0026lt;/strong\u0026gt;* Mastery of top-level integration tools (Cadence Innovus).\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Expertise in physical verification suites (e.g., Siemens Calibre nmDRC/nLVS/PERC, Synopsys IC Validator).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with chip/package co-design and bump planning tools.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Programming/Scripting:\u0026lt;/strong\u0026gt; High proficiency in Tcl, Python, and/or Perl for EDA flow automation and database manipulation.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul data-path-to-node=\u0026quot;9\u0026quot;\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Education:\u0026lt;/strong\u0026gt; Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;hr\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience with multi-die integration, 2.5D/3D packaging, or chiplet-based architectures.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Previous experience leading tapeout operations for start-up or fast-paced advanced technology environments.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Advanced knowledge of custom layout integration and mixed-signal IP drop-in\u0026lt;strong\u0026gt;\u0026lt;br\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;","departments":[{"id":4005974009,"name":"Hardware","child_ids":[],"parent_id":null}],"offices":[{"id":4030255009,"name":"India","location":null,"child_ids":[4063997009,4063998009],"parent_id":null}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":"http://app9.greenhouse.io/ai_opt_out_request/job_post/4322288009/ai_opt_out"},{"absolute_url":"https://job-boards.greenhouse.io/enchargeai36/jobs/4375746009","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4217021009,"location":{"name":"US Remote"},"metadata":null,"id":4375746009,"updated_at":"2026-09-04T16:18:20-04:00","requisition_id":"10301","title":"Principal Solutions Engineer","company_name":"EnCharge AI","first_published":"2026-08-19T12:41:55-04:00","language":"en","application_deadline":null,"content":"\u0026lt;p\u0026gt;EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;About the Role\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;EnCharge AI is looking for a highly experienced, hands-on \u0026lt;strong\u0026gt;Principal Solutions Engineer\u0026lt;/strong\u0026gt; to lead customer and partner solution development, architecture, and deployment for our next-generation AI acceleration platform. This is a senior technical leadership role that combines customer-facing engagement, solution architecture, AI software optimization, and technical mentorship.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This role will partner with strategic customers throughout their development lifecycle—from initial technical discovery, architectural evaluation, and proof-of-concepts through production deployment and scaling. Bridging the gap between AI hardware, software, systems, and customers, helping them successfully build, optimize, and scale cutting-edge AI workloads and agentic workflows on EnCharge technology. Serving as the voice of the customer, directly influencing product roadmaps, software features, and developer experience.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Serve as the primary technical interface and trusted advisor for strategic customers and partners evaluating and deploying AI workloads on EnCharge platforms.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead end-to-end customer engagements from technical discovery through proof-of-concept (PoC), design-in, performance benchmarking, system-level tuning, and production deployment.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support technical pre-sales efforts by clearly articulating solution value propositions, architectural differentiators, and competitive performance benchmarks.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Architect and develop reference applications, demonstrations, solution accelerators, and customer evaluation platforms for diverse verticals (e.g., edge AI, robotics, autonomous systems, enterprise datacenter).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Help customers integrate complex AI models, perception pipelines, multi-modal systems, AI agents, and software stacks into robust end-to-end solutions.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proactively identify and onboard strategic software and hardware partners, mapping value chains to co-develop AI solutions that expand market reach and accelerate time-to-market.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with ODMs on complete system designs and collaborate with ISVs to deliver documentation and reference designs that empower the ecosystem.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Troubleshoot complex hardware/software integration challenges, optimizing application performance, latency, throughput, and power efficiency to drive winning proof points.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Partner closely with Product Management and Engineering to communicate requirements, identify product gaps, and directly influence the product roadmap.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop comprehensive technical documentation, application notes, tutorials, training materials, and enablement collateral.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;8+ years of experience in Solutions Engineering, Field Applications Engineering, Technical Marketing Engineering, or related customer-facing technical roles within the semiconductor or AI industry.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven track record of bringing complex hardware and software products to market and driving adoption through end-to-end solution integration.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong software development experience using Python and C++.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience with AI/ML frameworks such as PyTorch, TensorFlow, ONNX Runtime, or similar, as well as AI inference optimization and model deployment.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of AI workloads, optimization, heterogeneous SoC architectures, software stacks, and system integration.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience working with embedded Linux systems, heterogeneous compute platforms, or AI accelerators.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Outstanding communication and interpersonal skills, with the ability to explain complex technical concepts clearly to diverse technical and executive audiences.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Self-motivated, execution-oriented mindset with a strong customer-first approach to solving complex technical challenges.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Master’s or Ph.D. in Electrical Engineering, Computer Science, or a related field preferred.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of AI agents, agentic workflows, multi-modal AI systems, or LLM-based edge applications.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Background in computer vision, autonomous navigation, perception systems, or embedded industrial automation.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience delivering technical training or speaking at customer workshops and industry conferences.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p class=\u0026quot;p2\u0026quot;\u0026gt;EnCharge AI is an equal employment opportunity employer in the United States.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p2\u0026quot;\u0026gt;The salary range for this position is $200,000 to $250,000 USD per year. Actual compensation offered will be determined based on job-related knowledge, skills, and experience.\u0026lt;/p\u0026gt;","departments":[{"id":4005973009,"name":"Platform","child_ids":[4059094009],"parent_id":null}],"offices":[{"id":4006050009,"name":"Remote - US","location":null,"child_ids":[],"parent_id":null}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":"http://app9.greenhouse.io/ai_opt_out_request/job_post/4375746009/ai_opt_out"},{"absolute_url":"https://job-boards.greenhouse.io/enchargeai36/jobs/4252539009","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4147675009,"location":{"name":"India"},"metadata":null,"id":4252539009,"updated_at":"2026-08-28T17:29:52-04:00","requisition_id":"IND03","title":"Research Engineer, AI Models","company_name":"EnCharge AI","first_published":"2026-06-26T11:15:47-04:00","language":"en","application_deadline":null,"content":"\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Research Engineer,\u0026amp;nbsp;Applied AI\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Location:\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; Bangalore (or throughout India remote-friendly with travel)\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;About\u0026amp;nbsp;EnCharge\u0026amp;nbsp;AI:\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;EnCharge\u0026amp;nbsp;AI is building the next generation AI platform. Our novel in-memory-computing architecture delivers a 10x step-function improvement in\u0026amp;nbsp;compute\u0026amp;nbsp;energy efficiency and performance for AI inference workloads. As the demands of artificial intelligence move beyond today\u0026#39;s models, we believe fundamental underlying infrastructure must evolve. We are an experienced team of AI researchers, silicon \u0026amp;amp; systems engineers, and architects backed by leading investors, poised to become the essential platform for the next wave of AI innovation.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;The Opportunity:\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Modern AI workloads—from large language models to diffusion-based generators to multimodal systems—represent some of the most compute-intensive frontiers in AI, and some of the most promising applications for our\u0026amp;nbsp;hardware’s\u0026amp;nbsp;energy efficiency advantages.\u0026amp;nbsp;We’re\u0026amp;nbsp;building a vertically integrated AI stack that will\u0026amp;nbsp;showcase\u0026amp;nbsp;the transformative potential of our silicon while delivering real value to customers today.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;We are seeking a Research Engineer to push the boundaries of AI model\u0026amp;nbsp;capability,\u0026amp;nbsp;quality,\u0026amp;nbsp;and efficiency.\u0026amp;nbsp;You’ll\u0026amp;nbsp;build fine-tuning\u0026amp;nbsp;and post training\u0026amp;nbsp;pipelines, develop rigorous benchmarking frameworks, and work at the intersection of ML research and hardware-aware optimization—ensuring our models\u0026amp;nbsp;run\u0026amp;nbsp;beautifully on our silicon.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;This is a role for someone who thrives at the boundary between research and engineering.\u0026amp;nbsp;You’ll\u0026amp;nbsp;read papers, implement techniques, and ship production-quality code—all in service of making AI inference faster, cheaper, and better.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Key Responsibilities:\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; 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Systematically characterize tradeoffs between model quality, latency, throughput, and power consumption to find\u0026amp;nbsp;optimal\u0026amp;nbsp;operating points across different use cases.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;10\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:2,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Hardware Co-Design:\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026amp;nbsp;Partner closely with hardware, compiler, and quantization teams to ensure algorithmic improvements translate to real gains on our silicon.\u0026amp;nbsp;Identify\u0026amp;nbsp;optimizations aligned with our\u0026amp;nbsp;architecture\u0026#39;s\u0026amp;nbsp;strengths—maximizing throughput while minimizing power. Shape the feedback loop between model development and hardware.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;10\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:2,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Evaluation:\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026amp;nbsp;Build profiling tools and comprehensive benchmarking frameworks to understand compute bottlenecks, measure model quality across standard and domain-specific evals, and track efficiency metrics.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;10\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:2,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Applied Research:\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026amp;nbsp;Build robust fine-tuning workflows for modern AI models, enabling rapid experimentation with\u0026amp;nbsp;LoRA, adapters, and full fine-tuning. Stay current with the rapidly evolving landscape—evaluate new architectures, implement promising techniques, and contribute insights that inform technical and go-to-market strategy.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Qualifications:\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;12\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;5+ years of experience in ML research, applied ML, or ML systems\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;12\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Strong fundamentals in Python and\u0026amp;nbsp;PyTorch\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;12\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Hands-on experience with transformers, diffusion models,\u0026amp;nbsp;state space\u0026amp;nbsp;models\u0026amp;nbsp;etc.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;12\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience fine-tuning large models and building training/evaluation pipelines\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;12\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Deep understanding of transformers, attention mechanisms, \u0026amp;amp; optimization techniques\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;12\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Comfort reading and implementing techniques from research papers\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Nice to Have:\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience with efficient inference techniques (KV cache optimization, attention variants,\u0026amp;nbsp;MoE\u0026amp;nbsp;routing, flow matching)\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Background in hardware-aware ML optimization or quantization\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Familiarity with profiling tools (PyTorch\u0026amp;nbsp;Profiler, Nsight, custom instrumentation)\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Publications in generative modeling, efficient inference, or ML systems\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Contributions to open-source ML projects\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;","departments":[{"id":4059094009,"name":"Applied Research","child_ids":[],"parent_id":4005973009}],"offices":[{"id":4030255009,"name":"India","location":null,"child_ids":[4063997009,4063998009],"parent_id":null}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":"http://app9.greenhouse.io/ai_opt_out_request/job_post/4252539009/ai_opt_out"},{"absolute_url":"https://job-boards.greenhouse.io/enchargeai36/jobs/4300106009","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4175895009,"location":{"name":"Germany"},"metadata":null,"id":4300106009,"updated_at":"2026-07-30T01:00:15-04:00","requisition_id":"10283","title":"Research Engineer, AI Models","company_name":"EnCharge AI","first_published":"2026-06-29T15:56:50-04:00","language":"en","application_deadline":null,"content":"\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Research Engineer,\u0026amp;nbsp;Applied AI\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Location:\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; Germany\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;About\u0026amp;nbsp;EnCharge\u0026amp;nbsp;AI:\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;EnCharge\u0026amp;nbsp;AI is building the next generation AI platform. Our novel in-memory-computing architecture delivers a 10x step-function improvement in\u0026amp;nbsp;compute\u0026amp;nbsp;energy efficiency and performance for AI inference workloads. As the demands of artificial intelligence move beyond today\u0026#39;s models, we believe fundamental underlying infrastructure must evolve. We are an experienced team of AI researchers, silicon \u0026amp;amp; systems engineers, and architects backed by leading investors, poised to become the essential platform for the next wave of AI innovation.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;The Opportunity:\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Modern AI workloads—from large language models to diffusion-based generators to multimodal systems—represent some of the most compute-intensive frontiers in AI, and some of the most promising applications for our\u0026amp;nbsp;hardware’s\u0026amp;nbsp;energy efficiency advantages.\u0026amp;nbsp;We’re\u0026amp;nbsp;building a vertically integrated AI stack that will\u0026amp;nbsp;showcase\u0026amp;nbsp;the transformative potential of our silicon while delivering real value to customers today.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;We are seeking a Research Engineer to push the boundaries of AI model\u0026amp;nbsp;capability,\u0026amp;nbsp;quality,\u0026amp;nbsp;and efficiency.\u0026amp;nbsp;You’ll\u0026amp;nbsp;build fine-tuning\u0026amp;nbsp;and post training\u0026amp;nbsp;pipelines, develop rigorous benchmarking frameworks, and work at the intersection of ML research and hardware-aware optimization—ensuring our models\u0026amp;nbsp;run\u0026amp;nbsp;beautifully on our silicon.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;This is a role for someone who thrives at the boundary between research and engineering.\u0026amp;nbsp;You’ll\u0026amp;nbsp;read papers, implement techniques, and ship production-quality code—all in service of making AI inference faster, cheaper, and better.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Key Responsibilities:\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;10\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:2,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Algorithmic Acceleration:\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026amp;nbsp;Research and implement\u0026amp;nbsp;state-of-the-art\u0026amp;nbsp;techniques to accelerate AI inference—quantization, sparsity, distillation, speculative decoding, caching strategies, and architectural modifications. Systematically characterize tradeoffs between model quality, latency, throughput, and power consumption to find\u0026amp;nbsp;optimal\u0026amp;nbsp;operating points across different use cases.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;10\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:2,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Hardware Co-Design:\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026amp;nbsp;Partner closely with hardware, compiler, and quantization teams to ensure algorithmic improvements translate to real gains on our silicon.\u0026amp;nbsp;Identify\u0026amp;nbsp;optimizations aligned with our\u0026amp;nbsp;architecture\u0026#39;s\u0026amp;nbsp;strengths—maximizing throughput while minimizing power. Shape the feedback loop between model development and hardware.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;10\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:2,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Evaluation:\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026amp;nbsp;Build profiling tools and comprehensive benchmarking frameworks to understand compute bottlenecks, measure model quality across standard and domain-specific evals, and track efficiency metrics.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;10\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:2,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Applied Research:\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026amp;nbsp;Build robust fine-tuning workflows for modern AI models, enabling rapid experimentation with\u0026amp;nbsp;LoRA, adapters, and full fine-tuning. Stay current with the rapidly evolving landscape—evaluate new architectures, implement promising techniques, and contribute insights that inform technical and go-to-market strategy.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Qualifications:\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;12\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;5+ years of experience in ML research, applied ML, or ML systems\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;12\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Strong fundamentals in Python and\u0026amp;nbsp;PyTorch\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;12\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Hands-on experience with transformers, diffusion models,\u0026amp;nbsp;state space\u0026amp;nbsp;models\u0026amp;nbsp;etc.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;12\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience fine-tuning large models and building training/evaluation pipelines\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;12\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Deep understanding of transformers, attention mechanisms, \u0026amp;amp; optimization techniques\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;12\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Comfort reading and implementing techniques from research papers\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Nice to Have:\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience with efficient inference techniques (KV cache optimization, attention variants,\u0026amp;nbsp;MoE\u0026amp;nbsp;routing, flow matching)\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Background in hardware-aware ML optimization or quantization\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Familiarity with profiling tools (PyTorch\u0026amp;nbsp;Profiler, Nsight, custom instrumentation)\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Publications in generative modeling, efficient inference, or ML systems\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Contributions to open-source ML projects\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;The salary range for this position is €116,000 to €154,000 EUR per year.\u0026amp;nbsp;Actual compensation offered will be determined based on job-related knowledge, skills, and experience.\u0026lt;/p\u0026gt;","departments":[{"id":4059094009,"name":"Applied Research","child_ids":[],"parent_id":4005973009}],"offices":[{"id":4006052009,"name":"Germany","location":null,"child_ids":[],"parent_id":null}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":"http://app9.greenhouse.io/ai_opt_out_request/job_post/4300106009/ai_opt_out"},{"absolute_url":"https://job-boards.greenhouse.io/enchargeai36/jobs/4212464009","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4124608009,"location":{"name":"India"},"metadata":null,"id":4212464009,"updated_at":"2026-07-30T01:00:15-04:00","requisition_id":"IND08","title":"Senior Emulation Engineer","company_name":"EnCharge AI","first_published":"2026-04-08T16:49:43-04:00","language":"en","application_deadline":null,"content":"\u0026lt;p\u0026gt;EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Senior Emulation Engineer\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Location: \u0026lt;/strong\u0026gt;India - Remote\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Job Description:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;At EnCharge AI, we are building the next generation of AI compute silicon — purpose-built\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;for high-performance, low-power, and scalable AI inference. As an Emulation Engineer, you\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;will play a critical role in validating complex AI accelerator architectures on emulation\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;platforms before tape-out. This position is ideal for someone passionate about bridging the\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;gap between hardware and software in fast-paced, deep tech environments.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Responsibilities:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;s1\u0026quot;\u0026gt;•\u0026lt;/span\u0026gt; Set up and maintain Siemens Veloce emulation and prototyping platforms\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;s1\u0026quot;\u0026gt;•\u0026lt;/span\u0026gt; Adapt SoC designs for Emulation and Prototyping\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;s1\u0026quot;\u0026gt;•\u0026lt;/span\u0026gt; Develop and debug emulation testbenches and system-level environments\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;s1\u0026quot;\u0026gt;•\u0026lt;/span\u0026gt; Support pre-silicon validation, power/performance analysis, and early software\u0026amp;nbsp;bring-up. Participate in silicon bring-up and validation.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;s1\u0026quot;\u0026gt;•\u0026lt;/span\u0026gt; Collaborate with design and verification teams to isolate design issues and\u0026amp;nbsp;accelerate debug.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;s1\u0026quot;\u0026gt;•\u0026lt;/span\u0026gt; Optimize performance of the emulation workloads and reduce turnaround time.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;s1\u0026quot;\u0026gt;•\u0026lt;/span\u0026gt; Work with firmware/software teams to enable use of emulators for OS and driver\u0026amp;nbsp;testing.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Required Background:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;s1\u0026quot;\u0026gt;•\u0026lt;/span\u0026gt; BS/MS/Ph.D. in EE, CS, or related field with 7+ years of SoC design experience.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;s1\u0026quot;\u0026gt;•\u0026lt;/span\u0026gt; Experience with emulation platforms (Veloce, Palladium, or ZeBu) and FPGA-based\u0026amp;nbsp;prototyping systems (proFPGA, HAPS, or Protium)\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;s1\u0026quot;\u0026gt;•\u0026lt;/span\u0026gt; Experience with emulating high speed I/O interfaces such as PCIe and UCIe and\u0026amp;nbsp;memory technologies such as LPDDR and HBM\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;s1\u0026quot;\u0026gt;•\u0026lt;/span\u0026gt; Solid understanding of digital design, RTL (Verilog/SystemVerilog), and SoC\u0026amp;nbsp;architecture.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;s1\u0026quot;\u0026gt;•\u0026lt;/span\u0026gt; Proficiency in hardware debug tools, waveform viewers, and logic analyzers\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;s1\u0026quot;\u0026gt;•\u0026lt;/span\u0026gt; Scripting skills (e.g., Python, Tcl, Perl) for automation and infrastructure\u0026amp;nbsp;development\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;s1\u0026quot;\u0026gt;•\u0026lt;/span\u0026gt; Familiarity with UVM, simulation, and testbench environments. SystemVerilog and\u0026amp;nbsp;UVM-based verification experience a plus\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;s1\u0026quot;\u0026gt;•\u0026lt;/span\u0026gt; Hand-on software development experience with C/C++ is a plus\u0026lt;/p\u0026gt;","departments":[{"id":4005973009,"name":"Platform","child_ids":[4059094009],"parent_id":null}],"offices":[{"id":4030255009,"name":"India","location":null,"child_ids":[4063997009,4063998009],"parent_id":null}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":"http://app9.greenhouse.io/ai_opt_out_request/job_post/4212464009/ai_opt_out"},{"absolute_url":"https://job-boards.greenhouse.io/enchargeai36/jobs/4254543009","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4148799009,"location":{"name":"US-Remote, Canada"},"metadata":null,"id":4254543009,"updated_at":"2026-07-30T01:00:15-04:00","requisition_id":"10067","title":"Senior NPU Architect","company_name":"EnCharge AI","first_published":"2026-05-20T18:57:37-04:00","language":"en","application_deadline":null,"content":"\u0026lt;p\u0026gt;EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;About the Role\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;EnCharge AI is seeking a Senior NPU Architect to join our Architecture Team. In this role, you will collaborate with a team of NPU and system architects, hardware engineers, and software teams to define and optimize key features in our AI accelerator with the cutting-edge in-memory computing technology. You will contribute to designing a holistic AI HW/SW solution that has the best performance and efficiency on the market for the latest AI/ML workloads, such as LLMs, diffusion models, CNNs, and more.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Define and develop the spec, architecture, and micro-architecture of key architecture modules (such as the in-memory compute unit, on-chip network, and memory orchestration units) based on the requirements of the workloads and software deployment flow\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Contribute to the modeling of aforementioned key architecture modules in our C++ simulation framework to ensure a functional implementation of the features\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with the design verification team to deliver a strategy and infrastructure\u0026amp;nbsp;for the testing of the architecture features within said modules\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work with the software team and other architects to analyze the performance and efficiency of the architecture modules for key workloads, identify performance bottlenecks, and guide architectural decisions\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Stay up to date with the latest trends and research in AI workloads, architectures, and applications to help define a path for the future generations of architectures\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;BS or MS in EE, CS, or a related field with 5-8 years of relevant experience. \u0026lt;br\u0026gt;Preferred: Ph.D. in a related field with 2-4 years of relevant experience.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Understanding in computer architecture, digital design, and micro-architecture concepts\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with AI/ML algorithms, frameworks, and workloads\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Programming experience in C/C++ and Python\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with HDLs such as Verilog or System Verilog\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;The salary range for this position is $180,000 to $240,000 USD ($175,000 to $245,000 CAD) per year. Actual compensation offered will be determined based on job-related knowledge, skills, and experience.\u0026lt;/p\u0026gt;","departments":[{"id":4005973009,"name":"Platform","child_ids":[4059094009],"parent_id":null}],"offices":[{"id":4006051009,"name":"Canada","location":null,"child_ids":[],"parent_id":null},{"id":4006050009,"name":"Remote - US","location":null,"child_ids":[],"parent_id":null}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":"http://app9.greenhouse.io/ai_opt_out_request/job_post/4254543009/ai_opt_out"},{"absolute_url":"https://job-boards.greenhouse.io/enchargeai36/jobs/4357591009","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4208001009,"location":{"name":" Bangalore INDIA Hybrid / Remote"},"metadata":null,"id":4357591009,"updated_at":"2026-08-06T12:59:52-04:00","requisition_id":"IND15","title":"Senior PD Engineer: Synthesis \u0026 STA","company_name":"EnCharge AI","first_published":"2026-08-06T12:59:52-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Job Title: Senior PD engineer : Synthesis \u0026amp;amp; STA\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Location:\u0026lt;/strong\u0026gt;\u0026amp;nbsp; Bangalore INDIA Hybrid / Remote\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;We are seeking a highly skilled\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;VLSI Synthesis \u0026amp;amp; STA Specialist\u0026lt;/strong\u0026gt;\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;to take end-to-end ownership of logic synthesis and quality signoff for key blocks and sub-chips.\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;In this role, you will act as a critical bridge between the front-end design and back-end physical implementation teams.\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;You will not only drive synthesis execution to meet aggressive target frequencies but also act as an advisor to the RTL team, providing structural feedback to optimize the netlist.\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;This role offers a distinct growth trajectory, with the expectation to expand into adjacent physical design territories, including Place and Route (PNR) and comprehensive timing convergence.\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Synthesis Ownership:\u0026lt;/strong\u0026gt;\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;Drive and own the complete logic synthesis process for all designated blocks and sub-chips, ensuring optimal area, power, and performance metrics.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Quality Signoff:\u0026lt;/strong\u0026gt;\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;Define, execute, and monitor rigorous sanity checks to achieve a high-quality, pristine Synthesis Signoff.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;RTL Collaboration:\u0026lt;/strong\u0026gt;\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;Work closely with RTL design engineers to ensure the delivery of a clean, fully linted netlist prior to handoff.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Frequency \u0026amp;amp; LOL Optimization:\u0026lt;/strong\u0026gt;\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;Deep dive into timing paths to ensure Levels of Logic (LOL) are strictly controlled and aligned with high-frequency target requirements.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Micro-architecture Guidance:\u0026lt;/strong\u0026gt;\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;Go beyond reporting LOL violations; provide actionable RTL coding guidelines, structural recommendations, and micro-architecture inputs to help designers transform their code into a superior, synthesis-friendly netlist.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Role Expansion:\u0026lt;/strong\u0026gt;\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;Progressively take on responsibilities in physical implementation adjacencies, actively participating in PNR execution, Static Timing Analysis (STA), and full-chip timing convergence.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Required Skills \u0026amp;amp; Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Experience: 5 to 8 years\u0026lt;/strong\u0026gt;\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;of proven experience in ASIC/SoC Logic Synthesis and Static Timing Analysis.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;EDA Tools Expertise:\u0026lt;/strong\u0026gt;\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;Hands-on experience with industry-standard synthesis tools, with a strong preference for\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;Cadence Genus\u0026lt;/strong\u0026gt;. Proficiency with STA signoff tools (e.g., Tempus, PrimeTime) is also required.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Timing \u0026amp;amp; STA:\u0026lt;/strong\u0026gt;\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;Strong foundational knowledge of STA, timing constraints (SDC), delay calculation, and multi-mode multi-corner (MMMC) analysis.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;RTL \u0026amp;amp; Logic Fundamentals:\u0026lt;/strong\u0026gt;\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;Deep understanding of Verilog/SystemVerilog, digital logic design, and RTL linting/CDC tools.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Netlist Optimization:\u0026lt;/strong\u0026gt;\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;Proven ability to analyze datapath architectures, identify logic bottlenecks, and recommend specific RTL changes to reduce logic depth.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Scripting/Automation:\u0026lt;/strong\u0026gt;\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;Proficiency in Tcl, Python, or Perl for developing and maintaining synthesis flow automation and customized reporting scripts.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional Communication:\u0026lt;/strong\u0026gt;\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;Excellent analytical and communication skills to effectively negotiate solutions between RTL and Physical Design teams.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Prior exposure to Place and Route (PNR) flows (e.g., Innovus, ICC2) and a solid understanding of how synthesis decisions impact physical placement and routing congestion.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with Formal Verification / Logic Equivalence Checking (LEC/Formality).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Knowledge of advanced technology nodes (e.g., 5nm, 3nm) and their specific synthesis/timing challenges.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;","departments":[{"id":4005974009,"name":"Hardware","child_ids":[],"parent_id":null}],"offices":[{"id":4030255009,"name":"India","location":null,"child_ids":[4063997009,4063998009],"parent_id":null}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":"http://app9.greenhouse.io/ai_opt_out_request/job_post/4357591009/ai_opt_out"},{"absolute_url":"https://job-boards.greenhouse.io/enchargeai36/jobs/4139769009","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4091787009,"location":{"name":"Bangalore"},"metadata":null,"id":4139769009,"updated_at":"2026-07-30T01:00:14-04:00","requisition_id":"IND01","title":"Senior Physical Design Engineer","company_name":"EnCharge AI","first_published":"2026-02-19T16:25:46-05:00","language":"en","application_deadline":null,"content":"\u0026lt;p\u0026gt;EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.\u0026lt;/p\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Job Title: Senior Physical Design Engineer\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Experience:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;4–7 Years\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Focus:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Block-Level RTL-to-GDSII \u0026amp;amp; PPA Optimization\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Location:\u0026lt;/strong\u0026gt;\u0026amp;nbsp; Bangalore Hybrid\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;The Role\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;We are looking for a high-energy, technically curious\u0026amp;nbsp;\u0026lt;strong\u0026gt;Physical Design Engineer\u0026lt;/strong\u0026gt;\u0026amp;nbsp;to join our advanced silicon team. This isn\u0026#39;t a role for someone who wants to just \u0026quot;push buttons\u0026quot; on a vendor flow.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;We need a driver—someone with 4–6 years of experience who has lived through the trenches of quality tape-outs and is hungry to take full ownership of complex partitions.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;You will be expected to work with a high degree of independence, using your analytical skills to bridge the gap between a standard recipe and a\u0026amp;nbsp;\u0026lt;strong\u0026gt;world-class PPA result\u0026lt;/strong\u0026gt;.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;You should be comfortable following expert lead direction while maintaining the \u0026quot;question the status-quo\u0026quot;\u0026amp;nbsp; mindset when you see a more efficient path.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Partition Ownership:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Lead the physical implementation of complex blocks from Synthesis and Floor-planning through to CTS, Routing, and Sign-off.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;PPA Recipe Development:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Don\u0026#39;t just run the flow—optimize it. You will perform deep-dive analysis on timing paths, power profiles, and congestion to derive custom optimization strategies.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Automation-First Mindset:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Use\u0026amp;nbsp;\u0026lt;strong\u0026gt;Tcl and Python\u0026lt;/strong\u0026gt;\u0026amp;nbsp;to automate repetitive tasks, build custom analysis scripts, and enhance the efficiency of the physical design environment.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Independent Convergence:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Take a partition from \u0026quot;dirty\u0026quot; RTL to a clean GDSII, resolving complex DRC/LVS, IR drop, and timing violations with minimal supervision.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional Collaboration:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Work closely with RTL and DFT teams to \u0026quot;left-shift\u0026quot; physical constraints, ensuring the design is optimized for routing and timing from the start.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Technical Requirements\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;table\u0026gt;\n\u0026lt;tbody\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td width=\u0026quot;99\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Category\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td width=\u0026quot;696\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Requirement\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td width=\u0026quot;99\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td width=\u0026quot;696\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;4–7 years in Physical Design with at least 2–3 successful tape-outs.\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td width=\u0026quot;101\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Tool Mastery\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td width=\u0026quot;694\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;Solid hands-on experience with industry-standard EDA tools (\u0026lt;strong\u0026gt;Cadence Innovus/Tempus\u0026lt;/strong\u0026gt;).\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td width=\u0026quot;99\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Automation\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td width=\u0026quot;696\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;Proficient in\u0026amp;nbsp;\u0026lt;strong\u0026gt;Tcl\u0026lt;/strong\u0026gt;\u0026amp;nbsp;(for tool control) and\u0026amp;nbsp;\u0026lt;strong\u0026gt;Python\u0026lt;/strong\u0026gt;\u0026amp;nbsp;(for data parsing and flow automation).\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td width=\u0026quot;99\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;PPA Skills\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td width=\u0026quot;703\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;Proven ability to analyse and improve Power, Performance, and Area through floor-planning and placement tuning.\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td width=\u0026quot;99\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Analysis\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td width=\u0026quot;696\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;Strong debugging skills in STA (Static Timing Analysis), EM/IR, and Physical Verification (DRC/LVS/ERC).\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;/tbody\u0026gt;\n\u0026lt;/table\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;The Ideal Candidate Profile\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;High \u0026quot;Workability\u0026quot; Quotient:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;You are coachable and can execute on complex instructions, but you possess the critical thinking to flag \u0026quot;status quo\u0026quot; processes that are inefficient.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;The \u0026quot;Detective\u0026quot; Mindset:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;When a tool fails or timing won\u0026#39;t close, you don\u0026#39;t just restart the run; you dig into the logs and data to find the root cause.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Driven \u0026amp;amp; Independent:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;You have a \u0026quot;get it done\u0026quot; attitude and pride yourself on your ability to unblock yourself through research and experimentation.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Curiosity:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Understand the psychology of the tool and drive it as an expert driver.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/div\u0026gt;","departments":[{"id":4005974009,"name":"Hardware","child_ids":[],"parent_id":null}],"offices":[{"id":4030255009,"name":"India","location":null,"child_ids":[4063997009,4063998009],"parent_id":null}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":"http://app9.greenhouse.io/ai_opt_out_request/job_post/4139769009/ai_opt_out"},{"absolute_url":"https://job-boards.greenhouse.io/enchargeai36/jobs/4343802009","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4200936009,"location":{"name":"Bangalore"},"metadata":null,"id":4343802009,"updated_at":"2026-08-03T14:18:08-04:00","requisition_id":"IND14","title":"Senior Staff / Principal SOC Floorplan Lead","company_name":"EnCharge AI","first_published":"2026-08-03T14:17:48-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;The Role\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;We are seeking a highly skilled and hands-on\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;SoC Floorplan Lead\u0026lt;/strong\u0026gt;\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;to own the physical foundation of our next-generation AI and Data Center SoCs. In this critical role, you will be the bridge between architecture, logic design, and physical design. You will work hand-in-hand with Chip Architects and RTL Leads to influence micro-architecture and ensure the physical implementation achieves best-in-class Power, Performance, and Area (PPA).\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;If you love solving complex spatial puzzles on advanced technology nodes, integrating sensitive analog components, and driving execution in a high-energy start-up environment, this is the role for you.\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;ul data-path-to-node=\u0026quot;10\u0026quot;\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Top-Level Floorplanning:\u0026lt;/strong\u0026gt;\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;Own the SoC-level floorplan from concept to tape-out for high-performance, large-scale AI/Data Center chips on advanced process nodes (e.g., 5nm, 3nm or below).\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Architecture \u0026amp;amp; RTL Collaboration:\u0026lt;/strong\u0026gt;\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;Partner closely with Architecture and RTL teams to provide early physical feasibility feedback. Drive block partitioning, shape optimization, and data-flow planning to achieve the absolute best PPA.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Bump \u0026amp;amp; Package Co-Design:\u0026lt;/strong\u0026gt;\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;Lead bump planning and IO ring definition. Work with packaging teams on flip-chip/advanced packaging constraints, ensuring optimal signal escape and power delivery.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Custom \u0026amp;amp; Analog Routing:\u0026lt;/strong\u0026gt;\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;Manage the placement and custom routing strategies for critical Analog/Mixed-Signal (AMS) IPs, high-speed SerDes (PCIe, Ethernet, Memory interfaces), PLLs, and sensitive clock distributions.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Power Delivery Network (PDN):\u0026lt;/strong\u0026gt;\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;Design and analyze the top-level power grid, ensuring robust power delivery for high-current AI workloads while minimizing IR drop.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Pin Assignment \u0026amp;amp; Feedthroughs:\u0026lt;/strong\u0026gt;\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;Manage macro placement, block-level pin assignments, and top-level feedthrough planning to optimize global timing and routing congestion.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Methodology Development:\u0026lt;/strong\u0026gt;\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;Build and maintain scalable Floorplanning workflows and scripts (Tcl, Python) tailored for a lean, fast-moving start-up team.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Required Skills \u0026amp;amp; Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;ul data-path-to-node=\u0026quot;12\u0026quot;\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Experience:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;strong\u0026gt;12 + years of hands-on experience in Physical Design SoC Floor planning preferably in Datacenter domain\u0026lt;/strong\u0026gt;, with at least 3 years acting as a lead or primary owner of SoC-level Floorplanning.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Domain Expertise:\u0026lt;/strong\u0026gt;\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;Proven track record of taping out large, complex chips—specifically for\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;Data Center, Networking, or AI/Machine Learning\u0026lt;/strong\u0026gt;applications.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Start-Up Mentality:\u0026lt;/strong\u0026gt;\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;Highly driven, self-motivated, and comfortable with ambiguity. You take extreme ownership of your domain, pivot quickly when needed, and roll up your sleeves to get things done.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Technical Depth:\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;ul data-path-to-node=\u0026quot;12,3,1\u0026quot;\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;Deep understanding of how RTL structures and architectural decisions impact physical design PPA.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;Extensive experience with bump planning, flip-chip package requirements, and die-to-package co-optimization.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;Strong knowledge of analog/mixed-signal IP integration, shielding, and custom routing constraints.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;Expertise with industry-standard physical design tools ( Cadence Innovus).\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Education:\u0026lt;/strong\u0026gt;\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;BS, MS, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;ul data-path-to-node=\u0026quot;14\u0026quot;\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;Experience with multi-die / chiplet integration (2.5D, 3D packaging, interposers, UCIe).\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;Strong scripting and automation skills (Tcl, Python, Perl, Makefile).\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;Knowledge of advanced clocking architectures (H-trees, meshes) for highly synchronous AI fabrics.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;What We Offer\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;ul data-path-to-node=\u0026quot;16\u0026quot;\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Impact:\u0026lt;/strong\u0026gt;\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;The opportunity to build ground-up architecture and see your ideas taped out in cutting-edge silicon.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Equity:\u0026lt;/strong\u0026gt;\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;Competitive start-up equity packages—when the company wins, you win.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Culture:\u0026lt;/strong\u0026gt;\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;A flat, collaborative, and bureaucracy-free environment surrounded by top-tier industry veterans.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;","departments":[{"id":4005974009,"name":"Hardware","child_ids":[],"parent_id":null}],"offices":[{"id":4030255009,"name":"India","location":null,"child_ids":[4063997009,4063998009],"parent_id":null}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":"http://app9.greenhouse.io/ai_opt_out_request/job_post/4343802009/ai_opt_out"},{"absolute_url":"https://job-boards.greenhouse.io/enchargeai36/jobs/4164343009","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4098167009,"location":{"name":"Bangalore (Hybrid) or India (Remote)"},"metadata":null,"id":4164343009,"updated_at":"2026-07-30T01:00:14-04:00","requisition_id":"IND04","title":"Staff DFT Engineer","company_name":"EnCharge AI","first_published":"2026-03-03T13:36:19-05:00","language":"en","application_deadline":null,"content":"\u0026lt;p\u0026gt;EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.\u0026lt;/p\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;The Opportunity\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;We are looking for a high-energy,\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;Staff-level DFT Engineer\u0026lt;/strong\u0026gt;\u0026amp;nbsp;to join our silicon team. In the fast-paced world of Edge AI, efficiency is everything.\u0026amp;nbsp;\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;As a \u0026quot;go-getter\u0026quot; in a startup environment, you’ll have the autonomy to shape the end-to-end DFT insertion process for our next-generation AI accelerators.\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Location: Hybrid via Bangalore or Remote across India \u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities:\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;ul data-path-to-node=\u0026quot;10\u0026quot;\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;End-to-End DFT Strategy:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Define and implement the complete DFT architecture as independent as possible, including Scan, MBIST, BSCAN, and Boundary Scan.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Constraint Management:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Take charge of DFT constraint development and management, ensuring seamless integration with synthesis and STA (Static Timing Analysis) teams.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;ATPG \u0026amp;amp; Simulation:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Generate high-coverage test patterns (Stuck-at, At-speed, Transition, Path Delay) and lead the verification of these patterns through timing-annotated simulations.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;AI-Specific Optimization:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Implement advanced DFT techniques tailored for Edge AI architectures, such as high-bandwidth memory testing and low-power test modes.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Hierarchical DFT:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Design and execute hierarchical DFT flows to manage complexity in large-scale AI SOCs.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Silicon Bring-up:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Partner with the ATE (Automated Test Equipment) teams to debug patterns on silicon and drive yield improvement initiatives.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;hr\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;What You Bring\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;ul data-path-to-node=\u0026quot;13\u0026quot;\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;The Experience:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;9–10 years of hands-on experience in DFT, preferably with at least one full tape-out cycle in a lead or staff capacity.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;The Toolkit:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Expert-level proficiency with industry-standard tools (e.g., Siemens Tessent, Synopsys DFTMAX/TetraMAX, or Cadence Genus/Modus).\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Technical Depth:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Deep understanding of DFT-centric STA, power-aware DFT, and high-speed IO testing.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Startup Mindset:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;You are comfortable wearing multiple hats. You don\u0026#39;t wait for a manual; you build the manual.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Edge AI Interest:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;A genuine interest in how AI hardware differs from general-purpose CPUs/GPUs.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;hr\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Why Join Us?\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;ul data-path-to-node=\u0026quot;16\u0026quot;\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;High Impact:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;In a startup, your decisions aren\u0026#39;t buried in layers of bureaucracy; they are visible in the final silicon.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Growth:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;You’ll be working alongside veterans from top-tier chipmakers, solving problems that haven\u0026#39;t been solved yet.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Ownership:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;We value \u0026quot;intrapreneurs\u0026quot;—engineers who treat the product like it’s their own.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;hr\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Technical Skills at a Glance\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;table data-path-to-node=\u0026quot;19\u0026quot;\u0026gt;\n\u0026lt;tbody\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;strong\u0026gt;Category\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;strong\u0026gt;Requirement\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;strong\u0026gt;Logic Test\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td\u0026gt;\n\u0026lt;div\u0026gt;Scan Compression, ATPG (Stuck-at, Transition), EDT\u0026lt;/div\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;strong\u0026gt;Memory Test\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td\u0026gt;\n\u0026lt;div\u0026gt;MBIST (Programmable/Hardened), Repair Algorithms\u0026lt;/div\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;strong\u0026gt;System Level\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td\u0026gt;\n\u0026lt;div\u0026gt;JTAG, IEEE 1149.1/6, IEEE 1500 (Wrappers)\u0026lt;/div\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;strong\u0026gt;Timing\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td\u0026gt;\n\u0026lt;div\u0026gt;DFT Constraints, SDC management, Post-layout STA\u0026lt;/div\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;strong\u0026gt;Scripting\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td\u0026gt;\n\u0026lt;div\u0026gt;Expert in Tcl, Python, or Perl for flow automation\u0026lt;/div\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;/tbody\u0026gt;\n\u0026lt;/table\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;","departments":[{"id":4005974009,"name":"Hardware","child_ids":[],"parent_id":null}],"offices":[{"id":4030255009,"name":"India","location":null,"child_ids":[4063997009,4063998009],"parent_id":null}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":"http://app9.greenhouse.io/ai_opt_out_request/job_post/4164343009/ai_opt_out"},{"absolute_url":"https://job-boards.greenhouse.io/enchargeai36/jobs/4329845009","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4193581009,"location":{"name":"Bangalore"},"metadata":null,"id":4329845009,"updated_at":"2026-07-30T01:00:15-04:00","requisition_id":"IND13","title":"Staff Engineer: STA Methodology \u0026 Sign-off Lead","company_name":"EnCharge AI","first_published":"2026-07-23T14:03:30-04:00","language":"en","application_deadline":null,"content":"\u0026lt;p\u0026gt;EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.\u0026lt;/p\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\n\u0026lt;div class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Staff Engineer: STA Methodology \u0026amp;amp; Sign-off Lead\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;We are seeking a high-caliber Staff or Senior Staff Engineer to architect and lead our SOC Static Timing Analysis (STA) Methodology along with execution responsibilities to eliminate the bottle-necks in STA and build bridges.\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;This is a critical\u0026amp;nbsp; role for a\u0026amp;nbsp; forward-thinking engineer who excels at defining the frameworks and flows required to navigate the complexities of modern, large-scale SOC designs. Engineer will have scope to bridge Architecture, CAD, RTL, and Physical Design to establish a predictable, high-performance, and scalable path to tape-out.\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;The Role\u0026lt;/strong\u0026gt;\u0026amp;nbsp;As the lead for STA Methodology, you will own the sign-off architecture and the timing convergence strategy. Rather than just executing runs, you will build the \u0026quot;engine\u0026quot; that enables execution—defining flows, qualifying tools, establishing margin strategies (AOCV/LVF/POCV), and driving cross-functional alignment to meet aggressive Power, Performance, and Area (PPA) targets.\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Sign-off Methodology \u0026amp;amp; Architecture:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Define and own full-chip SOC timing sign-off criteria, including Multi-Mode Multi-Corner (MMMC) definitions, derate strategies, and operating condition mapping for functional, shift, and capture modes.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Flow Development \u0026amp;amp; Left-Shift Automation:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Architect, deploy, and maintain advanced STA and ECO flows. Develop methodologies to proactively identify structural timing issues and predict physical design bottlenecks early in the RTL/Synthesis phases.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Tool Benchmarking \u0026amp;amp; Deployment:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Evaluate, qualify, and deploy new EDA tool features and capabilities (with a strong emphasis on Cadence Tempus) to improve Quality of Results (QoR), optimize memory/runtime efficiency, and streamline hierarchical timing models.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Custom Automation Infrastructure:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Architect scalable, robust automation utilities (Tcl, Python, Perl) to standardize constraint (SDC) management, automate cross-domain timing audits, and accelerate the ECO loop across distributed design teams.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional Enablement:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Partner with Physical Design to define optimal clock tree synthesis (CTS) methodologies and floorplanning guidelines. Guide DFT and RTL teams on methodology to resolve structural bottlenecks (e.g., NoC timing, complex CDC paths).\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;div class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Requirements \u0026amp;amp; Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Experience:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;8 to 11 years of hands-on experience in VLSI design, with a primary focus on STA Methodology, flow development, and sign-off criteria at advanced process nodes (7nm, 5nm, or below).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Technical Mastery:\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Deep expertise in building flows around industry-standard sign-off tools, with a strong preference for Cadence Tempus.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Mastery of Multi-Mode Multi-Corner (MMMC) flow architecture, Hierarchical (ILM/ETM) vs. Flat timing strategies, and constraint (SDC) validation methodologies.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of advanced node timing phenomena, including waveform propagation, crosstalk, and statistical margining (LVF/POCV).\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Critical Thinking:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Proven ability to architect broad flow solutions and debug systemic tool or methodology bottlenecks, rather than just fixing isolated timing violations.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Soft Skills:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Strong leadership presence with the ability to define technical standards, influence cross-functional teams, and drive methodology adoption in a fast-paced, high-growth environment.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Education:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;B.Tech/M.Tech\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;in Electrical/Electronics Engineering or a related field.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/div\u0026gt;","departments":[{"id":4005974009,"name":"Hardware","child_ids":[],"parent_id":null}],"offices":[{"id":4030255009,"name":"India","location":null,"child_ids":[4063997009,4063998009],"parent_id":null}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":"http://app9.greenhouse.io/ai_opt_out_request/job_post/4329845009/ai_opt_out"},{"absolute_url":"https://job-boards.greenhouse.io/enchargeai36/jobs/4397954009","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4230417009,"location":{"name":"US-Remote, Canada"},"metadata":null,"id":4397954009,"updated_at":"2026-09-08T12:32:48-04:00","requisition_id":"10062","title":"Staff Physical Design Engineer ","company_name":"EnCharge AI","first_published":"2026-09-08T12:31:41-04:00","language":"en","application_deadline":null,"content":"\u0026lt;p\u0026gt;EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;About the Role\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;EnCharge AI is looking for a highly motivated and experienced \u0026lt;strong\u0026gt;Staff Physical Design Engineer\u0026lt;/strong\u0026gt; to drive the physical implementation of our next-generation semiconductor chips. In this role, you will play a critical part in translating complex microarchitectures into high-performance, power-efficient silicon. Working closely with cross-functional teams, you will own block-level and top-level implementation using industry-standard EDA tools, tackle complex timing closure and power challenges, and guide designs all the way from netlist to successful foundry tapeout.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Drive block-level and top-level physical design, including floor-planning, placement, clock tree synthesis (CTS), and routing.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Achieve aggressive timing, power, and area (PPA) targets through advanced timing closure techniques.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Perform power grid verification and manage electromigration and IR drop (EM/IR) analysis and resolution.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop and maintain automation scripts (Tcl/Python) to streamline design flows and methodologies.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with physical verification and foundry teams to ensure design rule compliance and successful tapeout execution.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Qualifications and Requirements\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor\u0026#39;s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;10–15 years of dedicated experience in physical design.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of EDA implementation flows with extensive experience using Cadence design tools.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep understanding of static timing analysis (STA) concepts and advanced timing closure methodologies.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Demonstrated success in top-level and block-level physical design, with hierarchical floorplanning expertise a strong plus.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency in low-power design techniques, debugging, and EM/IR check resolution/power grid verification.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong scripting skills in Tcl or Python for design flow automation.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Solid understanding of advanced process nodes and physical verification requirements associated with routing.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with physical design methodology, flow setup, and advanced flow evaluations.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Prior experience with PDK management or foundry tapeout processes is highly desirable.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;EnCharge AI is an equal employment opportunity employer in the United States.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;The salary range for this position is $170,000 to $240,000 USD ($170,000 to $230,000 CAD) per year. Actual compensation offered will be determined based on job-related knowledge, skills, and experience.\u0026lt;/p\u0026gt;","departments":[{"id":4005974009,"name":"Hardware","child_ids":[],"parent_id":null}],"offices":[{"id":4006051009,"name":"Canada","location":null,"child_ids":[],"parent_id":null},{"id":4006050009,"name":"Remote - US","location":null,"child_ids":[],"parent_id":null}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":"http://app9.greenhouse.io/ai_opt_out_request/job_post/4397954009/ai_opt_out"},{"absolute_url":"https://job-boards.greenhouse.io/enchargeai36/jobs/4312902009","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4183862009,"location":{"name":"Bangalore (Hybrid), India (Remote)"},"metadata":null,"id":4312902009,"updated_at":"2026-07-30T01:00:15-04:00","requisition_id":"IND10","title":"Staff / Senior Staff CAD \u0026 Methodology Engineer (Digital Implementation \u0026 Signoff)","company_name":"EnCharge AI","first_published":"2026-07-10T00:42:54-04:00","language":"en","application_deadline":null,"content":"\u0026lt;p\u0026gt;EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.\u0026lt;/p\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;We are an ambitious AI hardware startup building next-generation accelerators with massive compute density. To achieve aggressive Power, Performance, and Area (PPA) targets on accelerated tapeout schedules, we require a robust, highly automated, and heavily optimized physical implementation and signoff flow.\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\n\u0026lt;hr\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;The Role\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;As a\u0026lt;strong\u0026gt; Staff / Senior Staff CAD \u0026amp;amp; Methodology Engineer,\u0026lt;/strong\u0026gt; you will be the resident expert in Innovus and Tempus, responsible for developing, debugging, and continually accelerating our RTL-to-GDSII and timing signoff flows. You will work closely with Physical Design and STA leads to eliminate bottlenecks, automate manual tasks, and push the limits of EDA capabilities at advanced process nodes.\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Flow Architecture \u0026amp;amp; Automation: Architect, develop, and maintain a highly automated, robust, and scalable physical design and signoff flow from synthesis through GDSII, optimized for AI accelerator architectures.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Innovus Methodology: Drive advanced physical design methodologies in Cadence Innovus. Optimize recipes for floorplanning, placement, Clock Tree Synthesis (CTS), routing, and power grid implementation to squeeze out maximum PPA.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Tempus Signoff Integration: Own the STA and timing signoff methodology using Cadence Tempus. Implement and optimize Distributed Multi-Scenario Analysis (DMSA), advanced OCV methodologies, and automated Tempus ECO flows to ensure rapid timing closure.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Turnaround Time (TAT) Reduction: Identify inefficiencies in the daily execution of block and top-level implementation. Develop Python and Tcl-based automation, database parsers, and custom utilities to drastically reduce tool runtime and engineering debug time.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Tool \u0026amp;amp; Vendor Interface: Act as the primary technical liaison with Cadence. Drive tool evaluations, beta testing of new features, and resolution of critical tool bugs or limitations to ensure continuous flow stability.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Mentorship \u0026amp;amp; Support: Serve as the final escalation point for the PD and Timing teams regarding flow-related issues. Document methodologies clearly and mentor junior engineers on tool usage and flow mechanics.\u0026lt;strong\u0026gt;\u0026lt;br\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;hr\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Requirements \u0026amp;amp; Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;ul data-path-to-node=\u0026quot;9\u0026quot;\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;Experience: 9 to 14 years of industry experience in ASIC/SOC physical design, with a primary focus on CAD, TFM (Tools, Flows, and Methodology), or flow automation.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;Cadence Mastery:\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Deep, production-proven expertise with Cadence Innovus (Implementation) and Cadence Tempus (Signoff STA).\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of internal tool mechanics, database access commands (dbGet), and advanced tool configuration.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;Scripting \u0026amp;amp; Software Skills: Expert-level proficiency in Tcl and Python. Strong background in Makefile generation, shell scripting, and version control (Git/Perforce).\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;Domain Knowledge: Thorough understanding of deep sub-micron physical design concepts (advanced node DRCs, cross-talk, electromigration, IR drop) and the theoretical foundations of Static Timing Analysis.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;Startup Mindset: Ability to thrive in a fast-paced, dynamic environment where flow requirements evolve rapidly as the architecture matures.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, Computer Engineering, or a related discipline.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;","departments":[{"id":4005974009,"name":"Hardware","child_ids":[],"parent_id":null}],"offices":[{"id":4030255009,"name":"India","location":null,"child_ids":[4063997009,4063998009],"parent_id":null}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":"http://app9.greenhouse.io/ai_opt_out_request/job_post/4312902009/ai_opt_out"},{"absolute_url":"https://job-boards.greenhouse.io/enchargeai36/jobs/4140565009","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4092270009,"location":{"name":"Bangalore or Remote in India"},"metadata":null,"id":4140565009,"updated_at":"2026-07-30T01:00:14-04:00","requisition_id":"IND02","title":"Staff/Senior Staff Physical Design Engineer (Technical Lead)","company_name":"EnCharge AI","first_published":"2026-02-20T14:23:36-05:00","language":"en","application_deadline":null,"content":"\u0026lt;p\u0026gt;EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.\u0026lt;/p\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Job Title:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;strong\u0026gt;Staff/\u0026lt;/strong\u0026gt;\u0026lt;strong\u0026gt;Senior Staff Physical Design Engineer (Technical Lead)\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Experience:\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;Staff 8-10 years\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;Senior Staff 11-13 years\u0026lt;/div\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Location:\u0026lt;/strong\u0026gt;\u0026amp;nbsp; Bangalore Hybrid/Remote or Remote in India\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;The Role\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;We are seeking a high-impact\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;strong\u0026gt;Staff/\u0026lt;/strong\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;Senior Staff Physical Design Engineer\u0026lt;/strong\u0026gt;\u0026amp;nbsp;to serve as a Technical Lead for our next-generation silicon products.\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;This is a \u0026quot;player-coach\u0026quot; role designed for a\u0026lt;strong\u0026gt;\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;versatile expert\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;who is equally comfortable architecting a\u0026amp;nbsp; convergence strategy as they are mentoring a small team of engineers.\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;You will own the physical delivery of a major sub-chip or complex block, pushing the absolute limits of\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;PPA (Power, Performance, Area)\u0026lt;/strong\u0026gt;.\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;As a Staff/Senior Staff lead, you are expected to be the \u0026quot;anchor\u0026quot; of the project—assertive in your decision-making, highly analytical in your debugging,\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026amp;nbsp;and adept at managing stakeholders to ensure we hit our tape-out milestones without compromise.\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;strong\u0026gt;Technical Leadership:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Lead a small team of PD engineers, providing technical direction, workload management, and architectural oversight for a sub-chip or partition.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;    \u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;em\u0026gt;\u0026amp;nbsp;\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/em\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;em\u0026gt;SOC clocking , FEV/VCLP specialized skills are preferred.\u0026lt;/em\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Complex Block/Sub-chip Ownership:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Take personal hands-on ownership of the most critical, high-congestion, or timing-critical blocks in the design.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Timing \u0026amp;amp; PPA Strategy:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Act as the primary architect for PD convergence. Derive and implement custom \u0026quot;PPA recipes\u0026quot; that go beyond standard vendor flows to meet aggressive targets.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Advanced Automation:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Drive efficiency across the team by developing sophisticated\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;Tcl and Python\u0026lt;/strong\u0026gt;\u0026amp;nbsp;scripts for flow automation, data mining, and sign-off verification.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Stakeholder Management:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Build strong rapport with RTL, DFT, and Synthesis teams. Effectively communicate risks and push for \u0026quot;left-shift\u0026quot; optimizations to safeguard the project schedule.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Sign-off Accountability:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Ensure the sub-chip meets all gold-standard sign-off criteria, including STA, EM/IR (Voltus/Apache), and Physical Verification (Pegasus/Calibre).\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Technical Requirements\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;table border=\u0026quot;0\u0026quot; cellspacing=\u0026quot;0\u0026quot; cellpadding=\u0026quot;0\u0026quot;\u0026gt;\n\u0026lt;tbody\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Category\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Requirement\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Experience\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;Staff 8-10 years\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;Senior Staff 11-13 years\u0026lt;/div\u0026gt;\nPD experience with a proven track record of multiple successful\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;lead-level\u0026lt;/strong\u0026gt;\u0026amp;nbsp;tape-outs.\u0026lt;/div\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Tool Mastery\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;Expert-level proficiency in\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;Cadence Innovus/Tempus\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Timing Convergence\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;Deep expertise in Static Timing Analysis (STA), including complex clocking, multi-corner sign-off, and crosstalk closure.\u0026lt;/div\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;PPA Optimization\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;Demonstrated ability to squeeze performance out of advanced nodes (7nm, 5nm, or below) via custom floorplanning, CTS strategies and other convergence approaches.\u0026lt;/div\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Automation\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;Advanced scripting in\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;Tcl and Python\u0026lt;/strong\u0026gt;\u0026amp;nbsp;to build scalable, repeatable design methodologies.\u0026lt;/div\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;/tbody\u0026gt;\n\u0026lt;/table\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Leadership \u0026amp;amp; Soft Skills\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;High Workability \u0026amp;amp; Assertiveness:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;You are a proactive communicator who can hold ground on technical requirements while remaining collaborative and solution-oriented.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Analytical Problem Solver:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;You don\u0026#39;t just identify violations; you analyze the \u0026quot;why\u0026quot; and derive a systemic fix that prevents the issue from recurring.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Driven \u0026amp;amp; Versatile:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;You possess the \u0026quot;Senior Staff\u0026quot; mindset—ready to jump into any part of the flow (from floorplan to GDSII) to unblock the team and meet the schedule.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;strong\u0026gt;Mentorship:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Passionate about raising the technical bar for the engineers reporting to you.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;","departments":[{"id":4005974009,"name":"Hardware","child_ids":[],"parent_id":null}],"offices":[{"id":4030255009,"name":"India","location":null,"child_ids":[4063997009,4063998009],"parent_id":null}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":"http://app9.greenhouse.io/ai_opt_out_request/job_post/4140565009/ai_opt_out"},{"absolute_url":"https://job-boards.greenhouse.io/enchargeai36/jobs/4179886009","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4103876009,"location":{"name":"Bangalore"},"metadata":null,"id":4179886009,"updated_at":"2026-07-30T01:00:15-04:00","requisition_id":"IND05","title":"Staff/Senior Staff Physical Design Floorplan \u0026 PDN Lead","company_name":"EnCharge AI","first_published":"2026-03-10T19:21:22-04:00","language":"en","application_deadline":null,"content":"\u0026lt;p\u0026gt;EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Staff/Senior Staff Physical Design Floorplan \u0026amp;amp; PDN Lead\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Experience:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;10–14 Years\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Location:\u0026lt;/strong\u0026gt;\u0026amp;nbsp; Bangalore/2 days to work\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Department:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;RTL-to-GDSII / Physical Implementation\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;We are seeking a high-caliber\u0026amp;nbsp;\u0026lt;strong\u0026gt;Staff or Senior Staff Physical Design Engineer\u0026lt;/strong\u0026gt;\u0026amp;nbsp;with a specialized mastery of\u0026amp;nbsp;\u0026lt;strong\u0026gt;Floorplanning and Power Delivery Network (PDN)\u0026lt;/strong\u0026gt;\u0026amp;nbsp;design. You won’t just be pushing buttons; you will be the architectural bridge between RTL/Systems and the final GDSII. This role requires a visionary who understands how a single floorplan decision ripples through the entire PPA (Power, Performance, Area) spectrum.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As a technical lead, you will own the chip-top floorplan for complex, large-scale SoCs or Sub-chips, driving strategies that balance aggressive performance targets with robust power integrity.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Architectural Floorplanning:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Lead chip-level floorplanning, including macro placement, pin assignment, and partition definition for multi-million gate designs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Strategic PDN Design:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Architect and implement complex Power Delivery Networks. You will define the metal stack usage and grid density to support high-performance cores while minimizing routing congestion.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;EMIR Mastery:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Perform exhaustive IR-drop (Static/Dynamic) and Electromigration (EM) analysis. You must be able to diagnose root causes and propose architectural or physical fixes that don\u0026#39;t compromise timing.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional PPA Trade-offs:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Collaborate directly with RTL and Architecture teams. You will use \u0026quot;Design Thinking\u0026quot; to influence the micro-architecture, suggesting changes to bus widths, pipeline stages, or memory configurations to optimize physical outcomes.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Methodology Development:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Establish best practices and automated flows for floorplanning and PDN synthesis to be used by the wider implementation team.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Technical Requirements\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Core Experience:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;10+ years in Physical Design with a proven track record of multiple successful tape-outs at advanced nodes (\u0026lt;strong\u0026gt;7nm, 5nm, or 3nm\u0026lt;/strong\u0026gt;).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;PDN Expertise:\u0026lt;/strong\u0026gt;Ability to model complex power-up sequences and multi-voltage domains.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Floorplanning Savvy:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Deep proficiency in hierarchical physical design and top-level integration using industry-standard tools (Innovus or IC Compiler II).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Analysis Skills:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Strong understanding of thermal-aware PDN and the physical implications of high-current density paths.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Scripting:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Advanced proficiency in\u0026amp;nbsp;\u0026lt;strong\u0026gt;Tcl, Python, or Perl\u0026lt;/strong\u0026gt;\u0026amp;nbsp;to automate complex floorplanning tasks and data analysis.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Behavioral Attributes\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Critical Thinker:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;You don\u0026#39;t just follow a recipe. You question constraints and look for \u0026quot;hidden\u0026quot; PPA gains.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Design Thinking:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Ability to empathize with the challenges of upstream (RTL) and downstream (Sign-off) teams to create a holistic solution.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Influence:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;You can articulate technical trade-offs to stakeholders,\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Education\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;B.Tech/M.Tech\u0026amp;nbsp;in Electrical/Electronic Engineering or equivalent.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;","departments":[{"id":4005974009,"name":"Hardware","child_ids":[],"parent_id":null}],"offices":[{"id":4030255009,"name":"India","location":null,"child_ids":[4063997009,4063998009],"parent_id":null}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":"http://app9.greenhouse.io/ai_opt_out_request/job_post/4179886009/ai_opt_out"},{"absolute_url":"https://job-boards.greenhouse.io/enchargeai36/jobs/4376670009","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4217613009,"location":{"name":"US Remote"},"metadata":null,"id":4376670009,"updated_at":"2026-08-19T20:49:19-04:00","requisition_id":"10073","title":"Technical Program Manager - Embedded Software","company_name":"EnCharge AI","first_published":"2026-08-19T20:40:11-04:00","language":"en","application_deadline":null,"content":"\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;EnCharge AI is building a new generation of AI compute systems designed to deliver dramatically\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;higher energy efficiency for AI inference. Our technology combines innovative compute\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;architectures with a full-stack software platform spanning silicon, firmware, drivers, compilers,\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;runtimes, and AI model enablement.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;We are looking for a \u0026lt;strong\u0026gt;Technical Program Manager - Embedded Software\u0026lt;/strong\u0026gt; to drive execution\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;across our embedded software organization and ensure tight alignment between firmware, drivers,\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;hardware, architecture, compiler, runtime, and system teams.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p2\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;About the Role\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;As Embedded SW TPM, you will be the connective tissue between silicon, platforms and systems\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;teams, driving the embedded and low-level software programs that enable EN100 (and future\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;accelerators) to run real AI workloads reliably and efficiently. You\u0026#39;ll own the program plan from\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;architecture through bring-up, pre-/post- silicon validation, and customer/OEM deployment to\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;surface risks before they become blockers and keeping a hardware-coupled software org moving\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;in lockstep with silicon milestones.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p2\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;What You\u0026#39;ll Do\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;s1\u0026quot;\u0026gt;•\u0026lt;/span\u0026gt; Own end-to-end program management for embedded software workstreams: device\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;drivers, firmware, boot-loaders and board support packages for EnCharge accelerators.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;s1\u0026quot;\u0026gt;•\u0026lt;/span\u0026gt; Build and maintain integrated program schedules that align embedded software milestones\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;with chip tape-out, silicon bring-up, board bring-up, and customer/OEM delivery dates.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;s1\u0026quot;\u0026gt;•\u0026lt;/span\u0026gt; Partner closely with embedded software, ASIC/hardware, platform and validation teams to\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;define scope, sequence dependencies, and track execution against plan.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;s1\u0026quot;\u0026gt;•\u0026lt;/span\u0026gt; Identify, track, and drive resolution of cross-team risks and blockers (e.g., silicon errata\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;affecting driver behavior, toolchain dependencies, host OS/driver compatibility).\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;s1\u0026quot;\u0026gt;•\u0026lt;/span\u0026gt; Drive silicon bring-up and platform enablement, including early firmware, boot flows,\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;device initialization, memory management, command submission, interrupts, power\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;management, and hardware/software integration.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;s1\u0026quot;\u0026gt;•\u0026lt;/span\u0026gt; Run the program\u0026#39;s operating cadence: planning, standups, milestone reviews,\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;retrospectives tuned to what a hardware-coupled software team actually needs, not generic\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;ceremony.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;s1\u0026quot;\u0026gt;•\u0026lt;/span\u0026gt; Drive execution across geographically distributed engineering teams and external partners\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;as needed.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;s1\u0026quot;\u0026gt;•\u0026lt;/span\u0026gt; Help build the program management function like process, tooling, and reporting.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p2\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;What We\u0026#39;re Looking For\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;s1\u0026quot;\u0026gt;•\u0026lt;/span\u0026gt; 8+ years of technical program or project management experience, with a meaningful\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;portion spent on embedded software, drivers, firmware, or low-level systems software.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;s1\u0026quot;\u0026gt;•\u0026lt;/span\u0026gt; Direct experience coordinating software programs tightly coupled to hardware (silicon\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;bring-up, board bring-up, or similar), ideally in AI/ML accelerators, semiconductors,\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;robotics, or a related hardware-software domain.\u0026lt;span class=\u0026quot;s1\u0026quot;\u0026gt;•\u0026lt;/span\u0026gt; Background in Linux kernel driver development processes, JTAG/lab-based debug\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;workflows, or hardware validation methodologies.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;s1\u0026quot;\u0026gt;•\u0026lt;/span\u0026gt; Experience with FPGA simulation and emulator environments like Zebu, Veloce,\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;Palladium.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;s1\u0026quot;\u0026gt;•\u0026lt;/span\u0026gt; Strong understanding of areas such as:\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot; style=\u0026quot;padding-left: 40px;\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;s4\u0026quot;\u0026gt;o\u0026lt;/span\u0026gt; Embedded firmware\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot; style=\u0026quot;padding-left: 40px;\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;s4\u0026quot;\u0026gt;o\u0026lt;/span\u0026gt; Device drivers\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot; style=\u0026quot;padding-left: 40px;\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;s4\u0026quot;\u0026gt;o\u0026lt;/span\u0026gt; SoC/accelerator architecture\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot; style=\u0026quot;padding-left: 40px;\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;s4\u0026quot;\u0026gt;o\u0026lt;/span\u0026gt; Memory and DMA\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot; style=\u0026quot;padding-left: 40px;\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;s4\u0026quot;\u0026gt;o\u0026lt;/span\u0026gt; Interrupts and command queues\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot; style=\u0026quot;padding-left: 40px;\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;s4\u0026quot;\u0026gt;o\u0026lt;/span\u0026gt; Boot and initialization\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot; style=\u0026quot;padding-left: 40px;\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;s4\u0026quot;\u0026gt;o\u0026lt;/span\u0026gt; Hardware/software interfaces\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot; style=\u0026quot;padding-left: 40px;\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;s4\u0026quot;\u0026gt;o\u0026lt;/span\u0026gt; Performance and system-level debugging\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;s1\u0026quot;\u0026gt;•\u0026lt;/span\u0026gt; Track record of managing complex, multi-team schedules with hard external dependencies\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;(tape-out dates, partner deliverables, customer commitments) and keeping them honest.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;s1\u0026quot;\u0026gt;•\u0026lt;/span\u0026gt; Strong risk management instincts — you find the thing that\u0026#39;s going to break the schedule\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;two months before it does.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;s1\u0026quot;\u0026gt;•\u0026lt;/span\u0026gt; Excellent written and verbal communication; able to flex between engineering detail and\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;executive summary.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p3\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;s1\u0026quot;\u0026gt;•\u0026lt;/span\u0026gt; Experience with AI accelerators, GPUs, NPUs, DSPs, or other heterogeneous compute\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;architectures.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;s1\u0026quot;\u0026gt;•\u0026lt;/span\u0026gt; Experience with silicon bring-up and early hardware/software co-development.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;s1\u0026quot;\u0026gt;•\u0026lt;/span\u0026gt; Experience with firmware for custom accelerators or SoCs.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;s1\u0026quot;\u0026gt;•\u0026lt;/span\u0026gt; Experience working across firmware, driver, compiler, and runtime teams.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;s1\u0026quot;\u0026gt;•\u0026lt;/span\u0026gt; Experience with simulation/emulation environments used for pre-silicon software\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;development.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;s1\u0026quot;\u0026gt;•\u0026lt;/span\u0026gt; Experience with Linux kernel, embedded Linux, RTOS, or low-level systems software.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;s1\u0026quot;\u0026gt;•\u0026lt;/span\u0026gt; Experience managing external engineering partners or vendors.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;EnCharge AI is an equal employment opportunity employer in the United States.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p1\u0026quot;\u0026gt;The salary range for this position is $200,000 to $250,000 USD per year. Actual compensation offered will be determined based on job-related knowledge, skills, and experience.\u0026lt;/p\u0026gt;","departments":[{"id":4005972009,"name":"Software","child_ids":[],"parent_id":null}],"offices":[{"id":4006050009,"name":"Remote - US","location":null,"child_ids":[],"parent_id":null}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":"http://app9.greenhouse.io/ai_opt_out_request/job_post/4376670009/ai_opt_out"}],"meta":{"total":26}}