{"jobs":[{"absolute_url":"https://job-boards.greenhouse.io/efficientcomputer/jobs/4284052009","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4167179009,"location":{"name":"San Jose, CA"},"metadata":null,"id":4284052009,"updated_at":"2026-06-11T15:16:44-04:00","requisition_id":"51","title":"Applications Engineer","company_name":"Efficient Computer","first_published":"2026-06-11T14:53:12-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;Efficient is developing the world’s most energy-efficient general-purpose computer processor. Efficient’s patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years. Our platform’s unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;Efficient Computer is seeking a\u0026amp;nbsp;\u0026lt;strong\u0026gt;Applications Engineer\u0026lt;/strong\u0026gt; to bridge the gap between our groundbreaking hardware and real-world customer applications. In this role, you will design and implement embedded computing solutions tailored to customer use cases, enabling them to fully leverage the power of Efficient’s architecture.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;If you thrive on solving technical challenges, enjoy working hands-on with both hardware and software, and love collaborating directly with customers to bring solutions to life, this is the role for you. You will play a critical part in ensuring our customers succeed across a wide range of embedded platforms and applications.\u0026lt;/p\u0026gt;\n\u0026lt;h3\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/h3\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Customer Engagement \u0026amp;amp; Application Engineering\u0026lt;/strong\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Partner directly with customers to understand their applications, requirements, and system challenges\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Design and implement board-level and embedded solutions that align with customer needs\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Serve as a trusted technical resource in customer interactions, helping them integrate Efficient hardware into their products\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Technical Development \u0026amp;amp; Integration\u0026lt;/strong\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Develop and optimize software and firmware on a variety of embedded computing platforms\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work across the full embedded stack—board design, firmware, and software—to deliver robust, efficient solutions\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with internal architecture, hardware, and software teams to refine customer-facing solutions\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Solution Delivery \u0026amp;amp; Enablement\u0026lt;/strong\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Own the development of reference designs, demos, and technical collateral to showcase Efficient’s technology in real-world scenarios\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support customers throughout the development lifecycle—from initial design to final deployment\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Provide feedback from the field to guide future product improvements and feature development\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h3\u0026gt;\u0026lt;strong\u0026gt;Required Qualifications \u0026amp;amp; Experience\u0026lt;/strong\u0026gt;\u0026lt;/h3\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s or Master’s degree in \u0026lt;strong\u0026gt;Electrical Engineering, Computer Engineering, Computer Science, or a related technical field\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;3+ years of experience in \u0026lt;strong\u0026gt;embedded systems development\u0026lt;/strong\u0026gt;, with strong background in software and firmware development\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience with multiple embedded platforms\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of board design and embedded system integration\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven track record in \u0026lt;strong\u0026gt;application engineering\u0026lt;/strong\u0026gt; or customer-facing technical roles\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent communication skills with the ability to explain complex technical concepts to a variety of audiences\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Willingness to \u0026lt;strong\u0026gt;travel to customer sites, Efficient offices, and industry events\u0026lt;/strong\u0026gt; as needed (up to 30%+ of your time)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Certain assignments for customers may require candidates to hold U.S. citizenship.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h3\u0026gt;\u0026lt;strong\u0026gt;Desired Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/h3\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Prior experience in \u0026lt;strong\u0026gt;solutions engineering, field application engineering, or customer-facing embedded development\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience building \u0026lt;strong\u0026gt;reference designs or developer kits\u0026lt;/strong\u0026gt; for embedded platforms\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with performance, power, and efficiency trade-offs in embedded computing systems\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Demonstrated ability to work independently in fast-moving, ambiguous environments\u0026lt;br\u0026gt;\u0026lt;br\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;We offer a competitive salary for this role, generally ranging from $160,000 to $210,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Why Join Efficient?\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Efficient offers a\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;competitive compensation and benefits package\u0026lt;/strong\u0026gt;, including\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;401K match, company-paid benefits, equity program, paid parental leave, and flexibility\u0026lt;/strong\u0026gt;. We are committed to personal and professional development and strive to grow together as people and as a company.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4056469009,"name":"Applications Engineering","child_ids":[],"parent_id":4001383009}],"offices":[{"id":4000912009,"name":"San Jose, CA","location":null,"child_ids":[],"parent_id":null}]},{"absolute_url":"https://job-boards.greenhouse.io/efficientcomputer/jobs/4005140009","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4003955009,"location":{"name":"Pittsburgh, PA, San Jose, CA"},"metadata":null,"id":4005140009,"updated_at":"2026-06-01T13:31:00-04:00","requisition_id":"15","title":"Computer Architect ","company_name":"Efficient Computer","first_published":"2025-06-12T12:53:41-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;Efficient is developing the world’s most energy-efficient general-purpose computer processor. Efficient’s patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years. Our platform’s unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;If you are a \u0026lt;em\u0026gt;Computer Architect \u0026lt;/em\u0026gt;who wants to impact the transformation of the next evolution of computing, we would like to talk to you. Efficient is hiring an \u0026lt;em\u0026gt;Computer Architect \u0026lt;/em\u0026gt;with experience in design-space exploration across the hardware-software interface. We seek individuals who are comfortable designing and executing experiments and interpreting and visualizing data.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This is a unique opportunity to get in at the ground level and have influence on our products as we move from initial stages of product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond!\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Work with Compiler and Digital Design teams to define the hardware-software interface for Efficient’s Fabric architecture.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work with Applications and Embedded teams to analyze the performance and efficiency of key applications on the Fabric and competing architectures.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Build simulation infrastructure to quickly and accurately model the performance of the Fabric.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Build visualization dashboard infrastructure to continuously monitor the performance and efficiency of the Fabric architecture.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Design \u0026amp;amp; execute experiments to perform a design-space exploration of the Fabric architecture and optimize it for key applications.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collect and analyze data from design-space explorations.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Write internal reports, white papers, and research publications on the Fabric architecture.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Master’s degree in Computer Science or Electrical Engineering and 3+ years of industry experience, or a doctoral degree in Computer Science or Electrical Engineering.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Extensive experience (3+ years) in designing and implementing architectural/microarchitectural simulators.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent coding skills in C++, Bash, and Python.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with data analysis and visualization tools like numpy, matplotlib, and Mathematica.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent technical communication skills in presentation and writing.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Track record of research publications in computer architecture.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;We offer a competitive salary for this role, generally ranging from $160,000 to $220,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Why Join Efficient?\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Efficient offers a\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;competitive compensation and benefits package\u0026lt;/strong\u0026gt;, including\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;401K match, company-paid benefits, equity program, paid parental leave, and flexibility\u0026lt;/strong\u0026gt;. We are committed to personal and professional development and strive to grow together as people and as a company.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4001390009,"name":"Architecture","child_ids":[],"parent_id":4001383009}],"offices":[{"id":4000913009,"name":"Pittsburgh, PA","location":null,"child_ids":[],"parent_id":null},{"id":4000912009,"name":"San Jose, CA","location":null,"child_ids":[],"parent_id":null}]},{"absolute_url":"https://job-boards.greenhouse.io/efficientcomputer/jobs/4135769009","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4089506009,"location":{"name":"San Jose, CA OR Pittsburgh, PA OR Austin,TX"},"metadata":null,"id":4135769009,"updated_at":"2026-04-08T16:03:29-04:00","requisition_id":"32","title":"Design Verification and Emulation Manager","company_name":"Efficient Computer","first_published":"2026-02-18T17:28:23-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;Efficient is developing the world’s most energy-efficient general-purpose computer processor. Efficient’s patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years. Our platform’s unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;Efficient is looking for a seasoned \u0026lt;strong\u0026gt;Design Verification \u0026amp;amp; Emulation Manager\u0026lt;/strong\u0026gt; to staff, lead and scale our verification and emulation organization which is part of our newly formed HW engineering organization. This is a high-impact leadership role responsible for ensuring silicon correctness and system-level readiness across multiple industry defining product lines. You will own the verification strategy from block-level to full-chip, drive emulation-based validation for early software enablement, and build a world-class team of verification and emulation engineers.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This role combines deep technical expertise with strong people leadership and program execution skills, and is ideal for someone who thrives at the intersection of architecture, verification methodology, hardware-software integration, and team building. This is a unique opportunity to have an influence on our products and processes as we move from the initial stages of product development to market release and scaled volume production.\u0026amp;nbsp; Join our team and help us shape the future of computing at the edge and beyond!\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Define end-to-end verification strategy\u0026lt;/strong\u0026gt; from block-level through full-chip simulation to emulation and prototyping\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Own UVM-based methodology\u0026lt;/strong\u0026gt;, including constrained-random, coverage-driven closure, assertions, and formal verification adoption\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Drive emulation platform strategy\u0026lt;/strong\u0026gt; — platform selection, capacity planning, compilation flows, and multi-project scheduling\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Enable system-level validation on emulation\u0026lt;/strong\u0026gt; — processor boot, OS bring-up, firmware execution, and IO exercising\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Deliver pre-silicon platforms for early software development\u0026lt;/strong\u0026gt; in partnership with firmware and software teams\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Establish hybrid simulation-emulation methodologies\u0026lt;/strong\u0026gt; using transactor-based interfaces to maximize both environments\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Own functional coverage models and sign-off criteria\u0026lt;/strong\u0026gt;, driving closure across simulation and emulation combined\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Lead debug and root cause analysis\u0026lt;/strong\u0026gt; across simulation and emulation, driving cross-functional bug resolution\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Manage verification dashboards, bug tracking, and regression health\u0026lt;/strong\u0026gt; to provide clear visibility to program leadership\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Build, mentor, and scale\u0026lt;/strong\u0026gt; a high-performing team of verification and emulation engineers\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Drive verification schedules and risk mitigation\u0026lt;/strong\u0026gt; aligned with chip program milestones and tapeout readiness\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Represent verification and emulation in tapeout readiness reviews\u0026lt;/strong\u0026gt; and program-level decision forums\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Collaborate cross-functionally\u0026lt;/strong\u0026gt; with Compiler Team, RTL design, architecture, DFT, physical design, and post-silicon teams\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Manage emulation lab infrastructure\u0026lt;/strong\u0026gt;, including hardware resources, licensing, and vendor relationships\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Evaluate and adopt new EDA tools and methodologies\u0026lt;/strong\u0026gt;, including AI/ML-assisted verification techniques.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Define right DV\u0026amp;nbsp; mix for in-house\u0026amp;nbsp; vs outsourcing to 3rd party vendors\u0026lt;/strong\u0026gt;. Coordinate 3rd party vendor resources towards achieving project goals.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Qualifications \u0026amp;amp; Experience\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Education:\u0026lt;/strong\u0026gt; Bachelor\u0026#39;s or Master\u0026#39;s degree in Electrical Engineering, Computer Engineering, or a related field. PhD is a plus.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Experience:\u0026lt;/strong\u0026gt; 12+ years of progressive experience in ASIC/SoC design verification, with at least 3–5 years in a management or senior technical leadership role overseeing both verification and emulation functions.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Verification Methodology:\u0026lt;/strong\u0026gt; Deep expertise in UVM, constrained-random verification, functional coverage, assertions (SVA), and simulation-based debug. Strong understanding of formal verification techniques.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Emulation Platforms:\u0026lt;/strong\u0026gt; Hands-on experience with at least one major emulation platform (Palladium, ZeBu, or Veloce) and familiarity with FPGA prototyping flows.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Languages \u0026amp;amp; Tools:\u0026lt;/strong\u0026gt; Strong proficiency in SystemVerilog, Verilog, and C/C++ for testbench and reference model development. Experience with Python, Tcl, and scripting for flow automation.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;SoC Architecture:\u0026lt;/strong\u0026gt; Solid understanding of modern SoC architectures — processors (ARM, RISC-V), cache coherency, interconnects (AMBA AXI/ACE/CHI), memory subsystems, and common peripherals.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Leadership:\u0026lt;/strong\u0026gt; Demonstrated ability to build, mentor, and manage verification teams of 10+ engineers. Experience hiring, developing talent, and scaling teams.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Execution:\u0026lt;/strong\u0026gt; Strong track record of driving verification closure and tapeout sign-off on complex designs (multi-million gate, multi-clock domain, multi-power domain).\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualification\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience with portable stimulus standard (PSS / Accellera) for verification reuse across simulation and emulation.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Background in power-aware verification (UPF/CPF-based) and low-power design verification challenges.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with AI/ML-assisted verification techniques (e.g., intelligent coverage convergence, ML-driven regression optimization).\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;We offer a competitive salary for this role, generally ranging from $210,000 to $250,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Why Join Efficient?\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Efficient offers a\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;competitive compensation and benefits package\u0026lt;/strong\u0026gt;, including\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;401K match, company-paid benefits, equity program, paid parental leave, and flexibility\u0026lt;/strong\u0026gt;. We are committed to personal and professional development and strive to grow together as people and as a company.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4001385009,"name":"Verification \u0026 Emulation","child_ids":[],"parent_id":4001383009}],"offices":[{"id":4030274009,"name":"Austin, TX","location":"Austin, TX","child_ids":[],"parent_id":null},{"id":4000913009,"name":"Pittsburgh, PA","location":null,"child_ids":[],"parent_id":null},{"id":4000912009,"name":"San Jose, CA","location":null,"child_ids":[],"parent_id":null}]},{"absolute_url":"https://job-boards.greenhouse.io/efficientcomputer/jobs/4286610009","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4168696009,"location":{"name":"San Jose, CA OR Pittsburgh, PA"},"metadata":null,"id":4286610009,"updated_at":"2026-06-15T16:44:19-04:00","requisition_id":"52","title":"Embedded Hardware Engineer","company_name":"Efficient Computer","first_published":"2026-06-15T16:44:19-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;Efficient is developing the world’s most energy-efficient general-purpose computer processor. Efficient’s patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years. Our platform’s unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;Efficient’s\u0026amp;nbsp;\u0026lt;em\u0026gt;\u0026lt;strong\u0026gt;Embedded Hardware Engineer\u0026lt;/strong\u0026gt; \u0026lt;/em\u0026gt;will design and implement complete systems that feature the world’s most energy-efficient programmable processor.\u0026amp;nbsp; Your primary role will be to develop PCB designs and accompanying system software to test and showcase our revolutionary processors.\u0026amp;nbsp; Specifically, you will be tasked with creating bring-up test hardware and customer evaluation development kits (EDKs), and assist with customer hardware reviews.\u0026amp;nbsp; You will develop the requisite software to operate our bring-up test hardware and EDKs, as well as develop our customer-facing SDK.\u0026amp;nbsp; Additionally, you will be involved in pre-silicon activities such as validating our processors using RTL simulators and FPGA emulators, and developing secure boot ROMs.\u0026amp;nbsp; This position is a unique opportunity to develop cutting-edge hardware and software as part of a highly interdisciplinary team, helping to demonstrate the value of Efficient’s breakthrough technology.\u0026amp;nbsp; If you are an engineer who wants to be part of an intensely skilled team and wants to have an immediate impact building the next generation of energy-efficient embedded applications, this is for you!\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Develop bring-up test hardware and customer EDKs\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Engage with PCBA vendors, and manage relationships\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Perform board bring-up\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Perform pre-silicon validation activities for our processors\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop boot ROM and firmware for our processors\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Perform first-silicon bring-up and checkout activities\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Engage with Digital Design and Compiler teams to debug silicon issues\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Build out a low level SDK for our processors and maintain a set of standard libraries\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support customers with their board development efforts, reviewing designs and providing recommended solutions\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deploy applications to our processors, in software simulation, RTL emulation, and silicon implementation\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Qualifications \u0026amp;amp; Experience Requirements\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;8+ years experience with PCB board design\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;8+ years of experience developing software for embedded systems\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience debugging new silicon and hardware prototypes in the lab\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;5+ years of experience with C and/or C++\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep knowledge of at least one embedded platform, such as MSP430, STM32, Ambiq Apollo, PIC32, or similar\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience using industry standard development and debugging tools for embedded systems\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong attention to detail, and an ability to work on multiple projects simultaneously\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Good problem solving skills, communication skills, and work ethic\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Comfortable working at a start-up engineering pace\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Desired Qualifications \u0026amp;amp; Experience Requirements\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience with Altium Develop\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Solid grasp of computer architectures\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;p\u0026gt;We offer a competitive salary for this role, generally ranging from $160,000 to $210,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.\u0026lt;/p\u0026gt;\n\u0026lt;/div\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Why Join Efficient?\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Efficient offers a\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;competitive compensation and benefits package\u0026lt;/strong\u0026gt;, including\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;401K match, company-paid benefits, equity program, paid parental leave, and flexibility\u0026lt;/strong\u0026gt;. We are committed to personal and professional development and strive to grow together as people and as a company.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4001388009,"name":"Embedded","child_ids":[],"parent_id":4001383009}],"offices":[{"id":4000913009,"name":"Pittsburgh, PA","location":null,"child_ids":[],"parent_id":null},{"id":4000912009,"name":"San Jose, CA","location":null,"child_ids":[],"parent_id":null}]},{"absolute_url":"https://job-boards.greenhouse.io/efficientcomputer/jobs/4251212009","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4146907009,"location":{"name":"San Jose, CA OR Pittsburgh, PA OR Austin,TX"},"metadata":null,"id":4251212009,"updated_at":"2026-06-15T16:46:42-04:00","requisition_id":"47","title":"Hardware Infrastructure Engineer","company_name":"Efficient Computer","first_published":"2026-05-18T14:28:09-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;Efficient is developing the world’s most energy-efficient general-purpose computer processor. Efficient’s patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years. Our platform’s unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;We are seeking an experienced engineer to develop, maintain, and scale ATLAS, our critical hardware regression testing and performance profiling infrastructure, while also serving as a key CI/CD owner across three development teams.\u0026amp;nbsp; ATLAS supports automated benchmarking and validation of both our company\u0026#39;s products and competitor hardware, providing essential data that drives engineering and product decisions.\u0026amp;nbsp; In addition, the CI/CD pipelines you own will be the backbone of day-to-day development velocity across multiple teams.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;The ideal candidate is a versatile full-stack infrastructure engineer who is equally comfortable writing Go services, debugging embedded test programs, managing Kubernetes clusters, and partnering with developers to deliver fast, reliable CI/CD experiences.\u0026lt;/p\u0026gt;\n\u0026lt;h2\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/h2\u0026gt;\n\u0026lt;h3\u0026gt;\u0026lt;strong\u0026gt;Regression Testing \u0026amp;amp; Performance Profiling Infrastructure\u0026lt;/strong\u0026gt;\u0026lt;/h3\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Server \u0026amp;amp; Client Development:\u0026lt;/strong\u0026gt; Design, implement, and maintain Go-based server and client applications, including WebSocket connections, HTTP API endpoints, feature additions, and bug fixes for our test orchestration platform\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Hardware Deployment, Maintenance \u0026amp;amp; Troubleshooting:\u0026lt;/strong\u0026gt; Install new hardware, manage deployed hardware, and perform debug and failure analysis of hardware issues.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Test Program Development:\u0026lt;/strong\u0026gt; Write, port, and maintain C/C++ test programs that run on a diverse set of hardware targets to measure performance, power, and functional behavior\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Tooling \u0026amp;amp; Automation:\u0026lt;/strong\u0026gt; Build Python tooling and scripts to automate workflows, parse results, generate reports, and improve developer productivity\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Kubernetes Infrastructure:\u0026lt;/strong\u0026gt; Maintain and evolve multi-cluster Kubernetes deployments, including job queueing, load balancing, scheduling, and resource management for hardware-attached worker nodes\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Containerization:\u0026lt;/strong\u0026gt; Build, version, and publish Docker images; author Dockerfiles for embedded toolchain environments and test runners\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Database Operations:\u0026lt;/strong\u0026gt; Manage and optimize PostgreSQL (operations data store) and Redis (caching layer), including schema design, query optimization, migrations, and reliability improvements\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Reliability \u0026amp;amp; Observability:\u0026lt;/strong\u0026gt; Monitor system health, triage failures, perform root-cause analysis, and continually improve the resilience and performance of the infrastructure\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h3\u0026gt;\u0026lt;strong\u0026gt;CI/CD Ownership\u0026lt;/strong\u0026gt;\u0026lt;/h3\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Pipeline Design \u0026amp;amp; Maintenance:\u0026lt;/strong\u0026gt; Own and maintain GitHub Actions CI/CD pipelines across three development teams, ensuring consistent, reliable, and performant builds, tests, deployments, and health checks\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Shared CI/CD Platform:\u0026lt;/strong\u0026gt; Develop reusable workflows, composite actions, and shared libraries to standardize CI/CD patterns across teams while accommodating team-specific needs\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Developer Experience:\u0026lt;/strong\u0026gt; Act as the primary point of contact for CI/CD-related issues across teams; triage failures, unblock developers, and reduce mean-time-to-green for pull requests\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Build \u0026amp;amp; Test Optimization:\u0026lt;/strong\u0026gt; Continuously improve pipeline speed, caching strategies, runner utilization, and test parallelization to reduce CI/CD cycle times and infrastructure costs\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Cloud-Based CI/CD Infrastructure:\u0026lt;/strong\u0026gt; Operate and optimize cloud-based CI/CD resources, including hosted and ephemeral runners, distributed build/test caching, and artifact/object storage backends\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Self-Hosted Runners:\u0026lt;/strong\u0026gt; Manage self-hosted GitHub Actions runners, including those with hardware attachments, ensuring capacity, security, and reliability across teams\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Package \u0026amp;amp; Artifact Management:\u0026lt;/strong\u0026gt; Operate and maintain PyPI services (e.g., private package indexes, mirrors, and proxies) and other artifact repositories used by development and CI/CD workflows\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Release Engineering:\u0026lt;/strong\u0026gt; Support release workflows, artifact management, versioning, and deployment automation for services and embedded firmware across teams\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Standards \u0026amp;amp; Best Practices:\u0026lt;/strong\u0026gt; Define and evangelize CI/CD best practices, branch protection policies, testing standards, and security/secret-management practices across the organization\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Cross-Team Coordination:\u0026lt;/strong\u0026gt; Partner with leads from each development team to align CI/CD roadmaps, plan migrations, prioritize improvements, and communicate changes that affect developer workflows\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Documentation \u0026amp;amp; Enablement:\u0026lt;/strong\u0026gt; Produce clear technical documentation, onboarding guides, and runbooks; provide training and office hours to help teams adopt and contribute to shared CI/CD infrastructure\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h2\u0026gt;\u0026lt;strong\u0026gt;Required Qualifications \u0026amp;amp; Experience\u0026lt;/strong\u0026gt;\u0026lt;/h2\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor\u0026#39;s degree in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field — or equivalent practical experience\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;5+ years of professional experience in a related infrastructure, DevOps, test engineering, or full-stack systems role\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on embedded hardware and software development experience, including working with embedded toolchains and bring-up of new hardware platforms\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Demonstrated experience owning CI/CD systems that serve multiple development teams or a large engineering organization\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Go:\u0026lt;/strong\u0026gt; Strong proficiency, including experience building production services with HTTP APIs and WebSockets\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;C/C++:\u0026lt;/strong\u0026gt; Demonstrated ability to write, debug, and maintain systems-level or test code.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Python:\u0026lt;/strong\u0026gt; Solid experience using Python for tooling, automation, and scripting\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Kubernetes:\u0026lt;/strong\u0026gt; Hands-on experience operating and maintaining multi-cluster environments, including queueing and load balancing patterns\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Docker:\u0026lt;/strong\u0026gt; Proficient at writing Dockerfiles, building/pushing images, and managing complex toolchain containers\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Databases:\u0026lt;/strong\u0026gt; Practical experience with PostgreSQL (operations workloads) and Redis (caching)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;CI/CD:\u0026lt;/strong\u0026gt; Deep experience designing and maintaining GitHub Actions pipelines, including reusable workflows, composite actions, matrix builds, caching, and self-hosted runners\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Cloud-Based CI/CD:\u0026lt;/strong\u0026gt; Hands-on experience with cloud-based CI/CD infrastructure, including managed/ephemeral runners, distributed caching strategies, and artifact/object storage\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Package Services:\u0026lt;/strong\u0026gt; Experience operating or integrating with PyPI services (private indexes, mirrors, or proxies) and managing Python package distribution in CI/CD environments\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Cross-Team Collaboration:\u0026lt;/strong\u0026gt; Proven ability to support and influence multiple engineering teams, balancing competing priorities and driving shared standards\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Communication:\u0026lt;/strong\u0026gt; Excellent written, verbal, and technical communication skills, with the ability to clearly document systems, lead discussions across teams, and produce developer-facing materials\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h2\u0026gt;\u0026lt;strong\u0026gt;Desired Qualifications \u0026amp;amp; Experience\u0026lt;/strong\u0026gt;\u0026lt;/h2\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Master\u0026#39;s degree in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with JTAG/SWD debugging tools and workflows\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with energy and power measurement tools (e.g., power monitors, current probes, instrumented test fixtures)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience designing hardware-in-the-loop (HIL) test systems or large-scale automated benchmarking infrastructure\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Background in performance profiling, benchmark design, or comparative hardware analysis.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience operating developer productivity / build engineering functions at scale, including metrics-driven improvements (e.g., DORA metrics, CI/CD cycle time, flaky test reduction)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with release engineering practices for both cloud services and embedded firmware.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with secrets management and CI/CD security best practices\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience administering artifact/package ecosystems\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;We offer a competitive salary for this role, generally ranging from $160,000 to $210,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Why Join Efficient?\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Efficient offers a\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;competitive compensation and benefits package\u0026lt;/strong\u0026gt;, including\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;401K match, company-paid benefits, equity program, paid parental leave, and flexibility\u0026lt;/strong\u0026gt;. We are committed to personal and professional development and strive to grow together as people and as a company.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4001388009,"name":"Embedded","child_ids":[],"parent_id":4001383009}],"offices":[{"id":4030274009,"name":"Austin, TX","location":"Austin, TX","child_ids":[],"parent_id":null},{"id":4000913009,"name":"Pittsburgh, PA","location":null,"child_ids":[],"parent_id":null},{"id":4000912009,"name":"San Jose, CA","location":null,"child_ids":[],"parent_id":null}]},{"absolute_url":"https://job-boards.greenhouse.io/efficientcomputer/jobs/4137172009","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4090373009,"location":{"name":"San Jose, CA OR Pittsburgh, PA OR Austin, TX"},"metadata":null,"id":4137172009,"updated_at":"2026-02-20T11:37:21-05:00","requisition_id":"33","title":"Lead Digital Verification Engineer","company_name":"Efficient Computer","first_published":"2026-02-18T19:36:56-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;Efficient is developing the world’s most energy-efficient general-purpose computer processor. Efficient’s patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years. Our platform’s unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;We are looking for an experienced \u0026lt;strong\u0026gt;Design Verification Lead\u0026lt;/strong\u0026gt; to drive the functional verification of complex SoC/IP designs from specification through tapeout in a newly formed hardware engineering organization. You will own the verification strategy, define methodology standards, build and guide a team of verification engineers, and serve as the final authority on verification quality and sign-off readiness. This role demands a strong blend of technical depth in modern verification methodologies (UVM, embedded C and compiler generated trace driven testing) and the leadership ability to execute across a multi-block chip program on schedul.e The DV Lead will help shape our internal processes for building robust and verified designs, including the company’s second product line, which will scale computing performance and capability, while improving energy efficiency.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This is a unique opportunity to have an influence on our products and processes as we move from the initial stages of product development to market release and scaled volume production.\u0026amp;nbsp; Join our team and help us shape the future of computing at the edge and beyond!\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Define the end-to-end verification strategy\u0026lt;/strong\u0026gt; across block, subsystem, and full-chip levels aligned with tapeout milestones\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Author and review verification plans\u0026lt;/strong\u0026gt; mapping specifications to features, stimulus strategies(traditional stimulus generation, compiler driven), coverage goals, and sign-off criteria\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Architect scalable UVM-based testbench environments\u0026lt;/strong\u0026gt; including agents, scoreboards, reference models, and coverage monitors\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Drive constrained-random stimulus development\u0026lt;/strong\u0026gt; targeting protocol interactions, concurrency, error injection, and corner cases\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Define and close functional coverage models\u0026lt;/strong\u0026gt; through systematic hole analysis, targeted tests, seed optimization, and regression tuning\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Deploy SystemVerilog Assertions\u0026lt;/strong\u0026gt; for protocol compliance, interface checks, and design invariants across all simulation runs\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Lead full-chip verification\u0026lt;/strong\u0026gt; including boot sequences, interrupt handling, DMA flows, power-on reset, and multi-block interactions\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Ensure CDC, RDC, and multi-power-domain verification\u0026lt;/strong\u0026gt; in coordination with specialist tools and teams\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Debug complex simulation failures\u0026lt;/strong\u0026gt; spanning multi-block interactions, protocol violations, race conditions, and timing-dependent corner cases\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Own the bug lifecycle\u0026lt;/strong\u0026gt; — triage, prioritization, tracking, fix verification, and cross-functional resolution with RTL designers and architects\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Manage the regression framework\u0026lt;/strong\u0026gt; — defining suites, maintaining stability, optimizing throughput, and integrating with CI/CD pipelines\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Coordinate simulation-to-emulation handoff\u0026lt;/strong\u0026gt; ensuring verification collateral transitions effectively to emulation environments\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Collaborate cross-functionally\u0026lt;/strong\u0026gt; with Compiler Team, RTL design, DFT, physical design, and post-silicon validation teams\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Lead, mentor, and grow\u0026lt;/strong\u0026gt; the verification engineering team while maintaining a high quality bar through rigorous reviews\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Represent verification readiness\u0026lt;/strong\u0026gt; in tapeout sign-off reviews and program-level decisions\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Support running gate-level simulations as part of design signoff.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Assist in building a verification dashboard to quickly understand where a design is in the verification process and to identify regressions.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Qualifications \u0026amp;amp; Experience\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Education:\u0026lt;/strong\u0026gt; Bachelor\u0026#39;s or Master\u0026#39;s/PhD degree in Electrical Engineering, Computer Engineering, or a related field.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Experience:\u0026lt;/strong\u0026gt; 10+ years of progressive experience in ASIC/SoC design verification, with at least 3 years in a lead role owning verification strategy, sign-off, and team execution.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;UVM Mastery:\u0026lt;/strong\u0026gt; Deep expertise in UVM-based testbench architecture and constrained-random verification methodology — not just usage, but architectural decision-making and optimization.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;SystemVerilog:\u0026lt;/strong\u0026gt; Advanced proficiency in SystemVerilog for verification including classes, constraints, functional coverage, assertions (SVA), interfaces, and packages.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Coverage Closure:\u0026lt;/strong\u0026gt; Demonstrated track record of driving functional and code coverage to tapeout sign-off on complex, multi-million-gate SoC/ASIC designs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Debug Skills:\u0026lt;/strong\u0026gt; Proven ability to debug deeply complex simulation failures spanning multiple design blocks, protocols, and abstraction levels.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;SoC Architecture:\u0026lt;/strong\u0026gt; Strong understanding of modern SoC building blocks — processors (ARM, RISC-V), interconnects (AMBA AXI/ACE/CHI), memory controllers, DMA engines, interrupt controllers, and standard peripherals.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Scripting \u0026amp;amp; Automation:\u0026lt;/strong\u0026gt; Proficiency in Python, Perl, or Tcl for test automation, log analysis, coverage post-processing, and regression flow development.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Communication:\u0026lt;/strong\u0026gt; Clear and effective communication of verification status, risk, and trade-offs to technical peers and program leadership.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;We offer a competitive salary for this role, generally ranging from $200,000 to $230,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Why Join Efficient?\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Efficient offers a\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;competitive compensation and benefits package\u0026lt;/strong\u0026gt;, including\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;401K match, company-paid benefits, equity program, paid parental leave, and flexibility\u0026lt;/strong\u0026gt;. We are committed to personal and professional development and strive to grow together as people and as a company.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4001385009,"name":"Verification \u0026 Emulation","child_ids":[],"parent_id":4001383009}],"offices":[{"id":4030274009,"name":"Austin, TX","location":"Austin, TX","child_ids":[],"parent_id":null},{"id":4000913009,"name":"Pittsburgh, PA","location":null,"child_ids":[],"parent_id":null},{"id":4000912009,"name":"San Jose, CA","location":null,"child_ids":[],"parent_id":null}]},{"absolute_url":"https://job-boards.greenhouse.io/efficientcomputer/jobs/4236891009","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4138388009,"location":{"name":"Austin, TX, Pittsburgh, PA, San Jose, CA"},"metadata":null,"id":4236891009,"updated_at":"2026-06-01T17:30:38-04:00","requisition_id":"45","title":"Lead RTL Design Engineer","company_name":"Efficient Computer","first_published":"2026-04-30T13:19:58-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;Efficient is developing the world’s most energy-efficient general-purpose computer processor. Efficient’s patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years. Our platform’s unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;We are looking for a Lead RTL Design Engineer to own microarchitecture definition and RTL implementation across the dataflow execution fabric, memory subsystem, on-chip interconnect/NoC, low-power logic, and standard peripheral IP (RiscV, NVM, I2S, I2C) integration. You will work from architecture spec through synthesis-ready RTL, collaborating with architects, microarchitects, DV leads, physical design, and firmware teams to tape out an industry leading power-efficient SoC.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This is a unique opportunity to be a part of a newly formed HW engineering org and have an influence on our products and processes as we move from the initial stages of product development to market release and scaled volume production.\u0026amp;nbsp; Join our team and help us shape the future of computing at the edge and beyond!\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Microarchitecture definition (core focus):\u0026lt;/strong\u0026gt; Own the design and definition of processor and compute-unit microarchitecture, including dataflow pipelines, execution units, and interfaces. Set performance, power, and area targets, and guide the team toward achieving them.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;On-chip interconnects and system integration:\u0026lt;/strong\u0026gt; Define and drive the design of on-chip networks and data movement across the fabric, balancing performance, scalability, and implementation constraints in collaboration with physical design.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Memory subsystem \u0026amp;amp; system architecture:\u0026lt;/strong\u0026gt; Define the interface to the memory subsystem, including data movement, ordering, and synchronization behavior, ensuring a clean and scalable model for software and future system expansion.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Reconfiguration and execution model:\u0026lt;/strong\u0026gt; Lead the architecture of configuration, scheduling, and execution of workloads on the fabric, including multi-kernel support and interaction with host systems.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Power management and low-power design:\u0026lt;/strong\u0026gt; Drive power architecture across the design, including clocking, reset, power domains, and low-power strategies to meet aggressive energy and efficiency goals.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;HW/SW co-design:\u0026lt;/strong\u0026gt; Collaborate closely with compiler and software teams to define the hardware execution model, ensuring efficient mapping of workloads onto the architecture.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Specifications, Documentations and Reviews: Author and own uArch specification documents for assigned blocks; drive design reviews with architecture, compiler, DV, and physical design stakeholders.\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Mentoring and process improvement:\u0026lt;/strong\u0026gt; Mentor senior and junior RTL engineers; review RTL, flag microarchitecture risks, and enforce coding style and lint-clean standards across the team.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Driving PPA Metrics:\u0026lt;/strong\u0026gt; Participate in PPA analysis loops: synthesize blocks regularly, review area/timing/power reports, and make data-driven tradeoffs against performance and feature requirements.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;DV Collaboration:\u0026lt;/strong\u0026gt; Collaborate with DV leads to define/review verification plans; provide directed test scenarios for graph execution corner cases, back-pressure conditions, and power state transitions.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Silicon Bring-up: \u0026lt;/strong\u0026gt;Support silicon bring-up: contribute scan/ATPG guidelines, review DFT insertion, and provide RTL-level debug assistance during lab validation.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Qualifications \u0026amp;amp; Experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;8+ years of RTL design experience with tape-out ownership of dataflow based design, on chip networks, memory subsystems\u0026amp;nbsp; or peripheral integration on a processor or accelerator SoC.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep proficiency in SystemVerilog for RTL — synthesis-clean, lint-clean, timing-aware; able to design complex state machines, arbiters, token flow controllers, and datapath logic from scratch.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Solid understanding of parallel execution models: dataflow, SIMD, or systolic array architectures; familiarity with the hardware challenges of token-based firing-rule evaluation and producer-consumer synchronization.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience with on-chip memory design: SRAM wrappers, scratchpad/TCM, banking, and memory-mapped register interfaces.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with low-power RTL techniques: UPF-driven flows, clock gating, power domains, retention registers, and AON wakeup logic.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with at least one standard on-chip bus protocol (AXI, AHB, APB, TileLink, or NoC equivalent) at the RTL implementation level.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience taking RTL through synthesis and timing closure; ability to read and act on SDC constraints, STA reports, and synthesis QoR summaries.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong written communication skills; able to produce uArch specs and design review material independently.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with memory compiler toolchains\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Desired Qualifications \u0026amp;amp; Experience Requirements\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Prior RTL ownership of a dataflow engine, neural processing unit (NPU), or streaming DSP architecture with explicit producer-consumer token management.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience collaborating with compiler or graph-optimization teams to co-design hardware execution models and graph IR representations.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with NVM controller RTL (MRAM, RRAM) including ECC, program/erase sequencing, and model weight storage use cases.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with IoT-class power budgets (sub-10 mW active, sub-100 µW standby) and the RTL design choices they necessitate.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with functional safety standards (ISO 26262, IEC 61508) as applied to execution fabric error detection and power domain isolation.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Exposure to AI framework graph formats (ONNX, TFLite) and understanding of how graph compilation maps to hardware execution primitives.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Tape-out credits on an edge-AI, IoT, or wearable SoC at 12nm or below.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with formal verification of flow-control logic, deadlock freedom, or bus protocol compliance.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;We offer a competitive salary for this role, generally ranging from $160,000 to $250,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Why Join Efficient?\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Efficient offers a\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;competitive compensation and benefits package\u0026lt;/strong\u0026gt;, including\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;401K match, company-paid benefits, equity program, paid parental leave, and flexibility\u0026lt;/strong\u0026gt;. We are committed to personal and professional development and strive to grow together as people and as a company.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4001384009,"name":"Digital Design","child_ids":[],"parent_id":4001383009}],"offices":[{"id":4030274009,"name":"Austin, TX","location":"Austin, TX","child_ids":[],"parent_id":null},{"id":4000913009,"name":"Pittsburgh, PA","location":null,"child_ids":[],"parent_id":null},{"id":4000912009,"name":"San Jose, CA","location":null,"child_ids":[],"parent_id":null}]},{"absolute_url":"https://job-boards.greenhouse.io/efficientcomputer/jobs/4140431009","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4092184009,"location":{"name":"San Jose, CA OR Pittsburgh, PA OR Austin, TX"},"metadata":null,"id":4140431009,"updated_at":"2026-04-08T13:45:18-04:00","requisition_id":"36","title":"Lead STA Engineer","company_name":"Efficient Computer","first_published":"2026-02-20T12:09:30-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;Efficient is developing the world’s most energy-efficient general-purpose computer processor. Efficient’s patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years. Our platform’s unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;Efficient is seeking a\u0026lt;em\u0026gt; Lead STA Engineer\u0026amp;nbsp;\u0026lt;/em\u0026gt;to join our growing team. The Timing Lead will work on timing convergence and methodology hands on for the world’s\u0026amp;nbsp;\u0026lt;strong\u0026gt;most energy-efficient, general-purpose processor\u0026lt;/strong\u0026gt;. This role will be in the \u0026lt;strong\u0026gt;newly formed hardware engineering group\u0026lt;/strong\u0026gt; and will focus on designing in state of the art finfet technologies. The role is cross functional and we are a integrated highly interdisciplinary team of world class engineers.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This is a unique opportunity to get in at the early stages of a hardware engineering organization and have influence on our products as we move from initial stages of product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond!\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Drive and develop Timing flows, methodology for state of the art finfet and multi patterning\u0026amp;nbsp; based technologies from scratch in Cadence Tempus or Synopsys Primetime.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Own and drive timing convergence of IP, Subsystem and SOC blocks.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Define timing margining, PVTRC corner definitions, extraction methodology , signoff timing to SYN/PNR correlation.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop slew rate, glitch noise checks to ensure robust design quality.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop custom timing checks as pertains to Efficients proprietary Ultra low power architecture.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work closely with RTL team, DFT and IP vendors to define and drive SDC constraints.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Have an in-depth understanding of all collaterals for all hard and soft IPs used by the design.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Partner with post-si products bring up team to ensure good pre-si to post-si correlation from a timing perspective.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work with 3rd party vendor resources and coordinate their work in the timing domain.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Continuously work on improving flow consistency and efficiency in the context of multiple product type swim lanes.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Master\u0026#39;s degree in Electrical Engineering with 5+ years of industry experience or PhD in Electrical Engineering with 3+ years of industry experience\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven track record of delivering IP/SS (or SoC) STA sign-off for multiple tape-outs in 12nm or below process technologies.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with EDA flow using Cadence/Synopsys/Mentor tools for STA/simulations (PT/Hspice) with hierarchical design and abstraction techniques\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience in\u0026amp;nbsp; timing convergence of high-frequency and low power designs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Expert knowledge of static timing analysis, defining constraints and exceptions, corners/voltage definitions and timing margining.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with low power implementation typical in industry and how timing convergence impacts power draw ensuring we are making optimal tradeoffs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent scripting skills in TCL, shell and python.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Desired Qualifications\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of computer architecture\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of physical design and ASIC implementation\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience in full chip sign-off budgeting\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of circuit design, device physics, deep sub-micron technology, and SOI technology and its implications to physical design\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency with industry-grade physical design flow and hands-on building CAD flow infrastructure for PD engineers.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Definition of design constraints for static timing analysis (synthesis, pre/post‑cts, sign‑off) and corners/voltage definitions.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience in integrating analog or mixed-signal macro on top-level design.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;We offer a competitive salary for this role, generally ranging from $200,000 to $250,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Why Join Efficient?\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Efficient offers a\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;competitive compensation and benefits package\u0026lt;/strong\u0026gt;, including\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;401K match, company-paid benefits, equity program, paid parental leave, and flexibility\u0026lt;/strong\u0026gt;. We are committed to personal and professional development and strive to grow together as people and as a company.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4001386009,"name":"Physical Design","child_ids":[],"parent_id":4001383009}],"offices":[{"id":4030274009,"name":"Austin, TX","location":"Austin, TX","child_ids":[],"parent_id":null},{"id":4000913009,"name":"Pittsburgh, PA","location":null,"child_ids":[],"parent_id":null},{"id":4000912009,"name":"San Jose, CA","location":null,"child_ids":[],"parent_id":null}]},{"absolute_url":"https://job-boards.greenhouse.io/efficientcomputer/jobs/4140439009","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4092189009,"location":{"name":"San Jose, CA OR Pittsburgh, PA OR Austin, TX"},"metadata":null,"id":4140439009,"updated_at":"2026-06-01T16:39:41-04:00","requisition_id":"38","title":"Physical Design - CAD Lead","company_name":"Efficient Computer","first_published":"2026-02-20T12:20:46-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;Efficient is developing the world’s most energy-efficient general-purpose computer processor. Efficient’s patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years. Our platform’s unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026amp;nbsp;Efficient is seeking a\u0026lt;em\u0026gt; CAD Lead - PD flows/infrastructure\u0026amp;nbsp; \u0026lt;/em\u0026gt;to join our growing team. The ideal CAD Lead would have worked on significant portion of the full gamut of Physical Design flows and flow infrastructure (flowtracer etc). \u0026amp;nbsp;This role is in a newly formed hardware engineering group and is the seed hire for this discipline. You will get to setup CAD flows and infra from scratch and influence and shape this aspect in the future.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This is a unique opportunity to get in at the early stages of a hardware engineering organization and have influence on our products as we move from initial stages of product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond!\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Drive and develop PD flows, methodology for state of the art finfet and multi patterning\u0026amp;nbsp; based technologies from scratch in Cadence Tempus or Synopsys Primetime.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Help develop repeatable, predictable , design and process agnostic PD flows.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop state of the art flow infrastructure to enable consistent and rapid design under tight schedule constraints for multiple product lines in the energy efficient edge AI computing market.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work closely with PD team leads to propose and develop end to end build and signoff flows.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Build regression frameworks for ensuring high quality flows and achieve hardware engineering vision of spending 90% or more time on actual design tasks and NOT wrestling with tools.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop collateral quality checking utils to ensure high design efficiency.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop and deploy a unified environment for specifying all collaterals (stdcell, memory, PDK, hardips…)\u0026amp;nbsp; and all flow dependencies (cycle time, PVTRC corners, per flow design and process dependent configuration).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work with 3rd party vendor resources and coordinate their work.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Continuously work on improving flow consistency and efficiency in the context of multiple product lines.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Master\u0026#39;s degree in Electrical Engineering with 5+ years of industry experience or PhD in Electrical Engineering with 3+ years of industry experience\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong python other scripting programming skills.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience in developing workflow orchestration infrastructure or tools for hardware development (Airflow, flowtracer etc)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with kubernetes and containerization\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience implementing regression frameworks\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;SQL or other database proficiency (MongoDB ..)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Intimate knowledge of hardware design workflows for Physical Design and RTL/DV.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent scripting skills in TCL, shell and python.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Desired Qualifications \u0026amp;amp; Experience Requirements\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience in full chip RTL/DV and PD flows.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of circuit design, device physics, deep sub-micron technology, and SOI technology and its implications to physical design\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency with industry-grade physical design flow and hands-on building CAD flow infrastructure for PD engineers.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Definition of design constraints for static timing analysis (synthesis, pre/post‑cts, sign‑off) and corners/voltage definitions.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience in integrating analog or mixed-signal macro on top-level design.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience in verifying IP collaterals.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;We offer a competitive salary for this role, generally ranging from $180,000 to $220,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Why Join Efficient?\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Efficient offers a\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;competitive compensation and benefits package\u0026lt;/strong\u0026gt;, including\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;401K match, company-paid benefits, equity program, paid parental leave, and flexibility\u0026lt;/strong\u0026gt;. We are committed to personal and professional development and strive to grow together as people and as a company.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4001386009,"name":"Physical Design","child_ids":[],"parent_id":4001383009}],"offices":[{"id":4030274009,"name":"Austin, TX","location":"Austin, TX","child_ids":[],"parent_id":null},{"id":4000913009,"name":"Pittsburgh, PA","location":null,"child_ids":[],"parent_id":null},{"id":4000912009,"name":"San Jose, CA","location":null,"child_ids":[],"parent_id":null}]},{"absolute_url":"https://job-boards.greenhouse.io/efficientcomputer/jobs/4140425009","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4092179009,"location":{"name":"San Jose, CA OR Pittsburgh, PA OR Austin, TX"},"metadata":null,"id":4140425009,"updated_at":"2026-02-20T12:04:21-05:00","requisition_id":"35","title":"Physical Design - Front End Lead","company_name":"Efficient Computer","first_published":"2026-02-20T12:04:21-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;Efficient is developing the world’s most energy-efficient general-purpose computer processor. Efficient’s patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years. Our platform’s unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;Efficient is seeking a\u0026lt;em\u0026gt; Physical Design - Front End Lead\u0026amp;nbsp; \u0026lt;/em\u0026gt;to join our growing team. The ideal candidate would drive front-end PD methodology (Synthesis, LEC, CLP, Low Power Design) hands on. We believe in a correct-by-construction philosophy and place a great emphasis on ensuring frontend flows accurately model signoff considerations. The Front End lead will ensure that we have methodologies in place to ensure the design built considers the right tradeoff between timing and power and optimizes for both aspects. The role is cross functional and we are an integrated highly interdisciplinary team of world class engineers.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This is a unique opportunity to get in at the early stages of a hardware engineering organization and have influence on our products as we move from initial stages of product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond!\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Drive and develop frontend flows and methodology for the industry defining Energy efficient general purpose processors.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ensure synthesis flows accurately model all aspects of PPA to enable highly optimized and correct by construction design to enable tight and quick design loops and design convergence\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop LEC flows to continuously assess logical correctness of the design as the design progresses to mature thru the design lifecycle.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Define UPF methodology and develop and converge UPF for all complex subsystems and SOC in collaboration with RTL\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop Conformal based ECO flows with an aim to address ALL ECOs rapidly..\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop flows for rapid uarch prototyping in conjunction with RTL.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deploy power and physical aware synthesis flows.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work with 3rd party vendor resources and coordinate their work.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Continuously work on improving flow consistency and efficiency in the context of multiple product lines.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Master\u0026#39;s degree in Electrical Engineering with 5+ years of industry experience or PhD in Electrical Engineering with 3+ years of industry experience\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with EDA flow using Cadence/Synopsys/Mentor tools for frontend flows, like Genus, Fusion Compiler, Design Compiler, Conformal, Formality.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with hierarchical design and modelling\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience in convergence of high-frequency and low power designs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of static timing analysis, defining constraints and exceptions and low power design techniques (isolation, level shifting, power switches..).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with low power implementation typical in industry,\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent scripting skills in TCL, shell and python.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Desired Qualifications \u0026amp;amp; Experience Requirements\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience in design space exploration for maximizing PPA using synthesis flows. Doing feasibility level sweeps to figure out optimal design build points.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency with industry-grade physical design flow.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Definition of design constraints.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of technology fundamentals and its implications to physical design\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;We offer a competitive salary for this role, generally ranging from $200,000 to $230,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Why Join Efficient?\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Efficient offers a\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;competitive compensation and benefits package\u0026lt;/strong\u0026gt;, including\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;401K match, company-paid benefits, equity program, paid parental leave, and flexibility\u0026lt;/strong\u0026gt;. We are committed to personal and professional development and strive to grow together as people and as a company.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4001386009,"name":"Physical Design","child_ids":[],"parent_id":4001383009}],"offices":[{"id":4030274009,"name":"Austin, TX","location":"Austin, TX","child_ids":[],"parent_id":null},{"id":4000913009,"name":"Pittsburgh, PA","location":null,"child_ids":[],"parent_id":null},{"id":4000912009,"name":"San Jose, CA","location":null,"child_ids":[],"parent_id":null}]},{"absolute_url":"https://job-boards.greenhouse.io/efficientcomputer/jobs/4259727009","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4151971009,"location":{"name":"San Jose, CA"},"metadata":null,"id":4259727009,"updated_at":"2026-06-02T12:11:35-04:00","requisition_id":"49","title":"Senior Product Manager - Hardware","company_name":"Efficient Computer","first_published":"2026-05-26T22:27:14-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;Efficient is developing the world’s most energy-efficient general-purpose computer processor. Efficient’s patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years. Our platform’s unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;div\u0026gt;The Hardware Product Manager defines the silicon product strategy and roadmap for Efficient Computer\u0026#39;s next-generation spatial computing platforms. This role sits at the intersection of architecture, silicon engineering, software, applications, and customer engagement by translating market and customer insight into actionable silicon product decisions.\u0026lt;br\u0026gt;\u0026lt;br\u0026gt;The Hardware PM owns product direction, market requirements, customer priorities, tradeoffs, and roadmap decisions. Engineering owns implementation and execution, with the Hardware PM partnering closely on technical decisions.\u0026lt;br\u0026gt;This role carries significant influence on company strategy and product direction. It is best suited for candidates with strong product strategy, customer-facing, and technical decision-making experience.\u0026lt;br\u0026gt;\u0026lt;br\u0026gt;\u0026lt;strong\u0026gt;Success looks like:\u0026lt;/strong\u0026gt;\u0026lt;br\u0026gt;The\u0026amp;nbsp; roadmap reflects real customer requirements and competitive insight\u0026lt;br\u0026gt;Product specifications are complete, aligned and approved tapeout\u0026lt;br\u0026gt;The Hardware PM is the person engineering, sales, and customers all go to for board, silicon and IP product direction\u0026lt;br\u0026gt;\u0026lt;br\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Define and own the silicon product roadmap, from near-term tape-out requirements to multi-generation platform strategy, based on customer requirements, competitive positioning, and architectural opportunity.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Translate customer needs, market dynamics, and competitive insight into clear product specifications.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Own the Market Requirements Document (MRD) process.with tradeoffs and ownership explicitly documented.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Partner with engineering to define performance targets, power envelopes, memory architecture, interface requirements, and feature prioritization for each product generation.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead customer discovery and requirements-gathering for silicon and IP capabilities.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Represent Efficient\u0026#39;s silicon in technical customer discussions, evaluation engagements, and design-win conversations.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive alignment between product requirements and engineering execution priorities. Own the cross-functional product review process and ensure tradeoff decisions are made explicitly, documented, and communicated as well as provide clear product direction when tradeoff decisions are required.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Partner with the Software PM on hardware-software co-design requirements and ensure silicon and IP roadmap decisions support a usable and scalable developer experience\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Own competitive analysis, benchmarking strategy, and product differentiation narrative.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Define platform requirements, including silicon, development systems, evaluation kits and reference designs, to enable customer adoption and successful deployment.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;div\u0026gt;Required Qualification\u0026lt;/div\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;7+ years of experience in semiconductor product management, silicon architecture, or related technical leadership roles with direct ownership of product requirements, roadmap, and customer engagements\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience managing at least one full silicon product cycle from requirements definition through customer sampling, including spec ownership and tradeoff decisions\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Working knowledge of SoC architecture concepts: memory hierarchy, power domains, on-chip interconnects, compute accelerators, and interface standards, etc. sufficient to engage substantively with engineering teams\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Direct customer engagement experience: translating customer application requirements and deployment constraints into concrete silicon and IP product requirements\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong cross-functional leadership across architecture, design, verification, software, and applications teams, with the ability to drive alignment and make decisions without always having formal authority\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ability to establish credibility with silicon architects, hardware engineers, and technically sophisticated customers through clear thinking, genuine technical depth, and accurate product judgment\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;div\u0026gt;We do not expect candidates to arrive with deep expertise in every area listed above. Strong product judgment, technical credibility, customer orientation, and the ability to learn quickly matter more than checking every box.\u0026lt;br\u0026gt;\u0026lt;br\u0026gt;Preferred Qualification:\u0026lt;/div\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience with MCUs, embedded AI processors, DSPs, FPGAs, spatial computing architectures, or dataflow accelerators\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience in a startup environment with high ownership, incomplete information, and rapidly evolving product requirements\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with embedded AI deployment workloads and edge inference application requirements, including power budgets, latency targets, and memory constraints\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with silicon benchmarking methodology and competitive analysis in the edge AI or embedded compute space\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with compiler-hardware co-design or hardware-software interface definition for novel compute architectures\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;We offer a competitive salary for this role, generally ranging from $180,000 to $210,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Why Join Efficient?\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Efficient offers a\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;competitive compensation and benefits package\u0026lt;/strong\u0026gt;, including\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;401K match, company-paid benefits, equity program, paid parental leave, and flexibility\u0026lt;/strong\u0026gt;. We are committed to personal and professional development and strive to grow together as people and as a company.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4000976009,"name":"Product","child_ids":[],"parent_id":null}],"offices":[{"id":4000913009,"name":"Pittsburgh, PA","location":null,"child_ids":[],"parent_id":null},{"id":4000912009,"name":"San Jose, CA","location":null,"child_ids":[],"parent_id":null}]},{"absolute_url":"https://job-boards.greenhouse.io/efficientcomputer/jobs/4254539009","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4148797009,"location":{"name":"San Jose, CA"},"metadata":null,"id":4254539009,"updated_at":"2026-05-20T18:47:55-04:00","requisition_id":"48","title":"Senior Product Manager - Software","company_name":"Efficient Computer","first_published":"2026-05-20T18:47:55-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;Efficient is developing the world’s most energy-efficient general-purpose computer processor. Efficient’s patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years. Our platform’s unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p data-start=\u0026quot;0\u0026quot; data-end=\u0026quot;458\u0026quot;\u0026gt;The \u0026lt;strong\u0026gt;Senior Product Manager - Software \u0026lt;/strong\u0026gt;owns the strategy and direction for Efficient Computer’s developer platform - including the compiler, SDK, runtime integrations, model enablement stack, and overall developer experience. This role is critical to customer adoption and long-term ecosystem growth, translating Efficient’s hardware capabilities into a scalable, developer-ready platform that enables customers to build, optimize, and deploy applications efficiently.\u0026lt;/p\u0026gt;\n\u0026lt;p data-start=\u0026quot;460\u0026quot; data-end=\u0026quot;864\u0026quot;\u0026gt;Success in this role requires thinking beyond individual features and approaching the platform as a complete developer ecosystem. The Software PM is responsible for defining product direction, prioritization, customer requirements, and developer experience outcomes, while partnering closely with software engineering, silicon architecture, applications engineering, marketing, and customer-facing teams.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This is a highly cross-functional product leadership role focused on strategy, platform evolution, and business impact — not project management or sprint administration. The Software PM defines what should be built, why it matters, how success is measured, and how priorities align with customer and company goals, while engineering teams own implementation and execution.\u0026lt;br\u0026gt;\u0026lt;br\u0026gt;\u0026lt;strong\u0026gt;Success looks like:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Developers achieve production-ready applications quickly, without white-glove engineering support\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;The compiler and SDK become a competitive advantage, not an adoption bottleneck\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Framework support and tooling reduce evaluation friction and accelerate customer design-ins\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Software capabilities directly influence customer wins and silicon roadmap decisions\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Define the product roadmap for the compiler, SDK, runtime, model conversion and enablement tooling, and developer platform. Set priorities based on customer requirements, competitive positioning, and strategic platform needs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead framework and model enablement strategy across PyTorch, ONNX, ExecuTorch, LiteRT, and future runtimes, including compatibility, validation coverage, performance expectations, and support commitments.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive reduction in time-to-first-working-application (TTFWA) across customer segments. Define the metric, baseline it, track it, and own the roadmap items that move it.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Establish SDK governance: surface area, versioning, API stability commitments, and deprecation policy. Define release quality criteria, validation expectations, and backward compatibility standards.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive developer confidence through reproducible benchmarking, deterministic tooling behavior, clear diagnostics, and strong documentation.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Participate in customer engagements to understand workflow friction, deployment blockers, and framework requirements. Represent software platform strategy in technical customer discussions and ecosystem partnerships.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Gather and prioritize developer feedback across evaluation, onboarding, optimization, and deployment phases. Maintain structured mechanisms to feed this directly into roadmap decisions.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Partner with Applications Engineering to define the software platform capabilities necessary for production-quality reference applications and customer evaluation flows, including AI inference, vision, audio, and sensor-processing pipelines.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Define requirements for profiling, debugging, and performance analysis workflows that allow developers to understand and optimize application behavior on Efficient hardware.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Balance long-term platform investments against near-term customer enablement and revenue-driving requirements. Understand when the right call is shipping a polished narrow capability vs. a rough broad one.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Influence silicon decisions based on software needs and constraints. Partner with the Hardware PM and architecture team when compiler or runtime requirements have silicon implications.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Establish and own developer success metrics and developer workflow metrics and diagnostics: build success rates, TTFWA, workflow completion rate, and friction points.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Define and own the SDK release cadence, packaging, distribution, and support lifecycle.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;7+ years of product management experience for developer-facing software platforms - SDKs, compilers, runtimes, APIs, ML tooling, or embedded developer ecosystems\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026amp;nbsp;Experience shipping tools and platforms used directly by external developers, including operating through the customer-zero phase\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Demonstrated ownership of developer adoption, onboarding success, workflow completion, or related developer productivity metrics\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of modern ML inference and deployment pipelines (PyTorch, ONNX, ExecuTorch, LiteRT (formerly TensorFlow Lite), TensorRT, or equivalent)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience translating customer workflows and technical constraints into actionable product requirements that engineering can build from without ambiguity\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with software performance tradeoffs involving memory, latency, throughput, power, and hardware utilization\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ability to work effectively with compiler, runtime, systems software, and silicon architecture teams and to influence without authority across all of them\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ability to establish credibility with highly technical developers, compiler engineers, and ML practitioners through clear thinking, technical depth, and strong customer empathy.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience with compiler toolchains, IRs, and deployment flows (LLVM, MLIR, TOSA, XLA, or equivalent)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with embedded AI deployment pipelines and edge inference workflows\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience at a semiconductor or AI hardware company building developer tools for a novel architecture\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with embedded software ecosystems (FreeRTOS, CMSIS-NN, MCU SDK patterns) and Linux-based embedded development environments and cross-compilation workflows\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with performance profiling tools, compiler traces, and benchmark-driven optimization workflows\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with benchmarking methodologies (MLPerf or equivalent) - including designing, running, and publishing credible results\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience operating in early-stage environments with incomplete requirements and rapidly evolving architectures\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience in startup environments with hybrid PM + DevRel responsibilities\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;We offer a competitive salary for this role, generally ranging from $160,000 to $210,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Why Join Efficient?\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Efficient offers a\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;competitive compensation and benefits package\u0026lt;/strong\u0026gt;, including\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;401K match, company-paid benefits, equity program, paid parental leave, and flexibility\u0026lt;/strong\u0026gt;. We are committed to personal and professional development and strive to grow together as people and as a company.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4000976009,"name":"Product","child_ids":[],"parent_id":null}],"offices":[{"id":4000913009,"name":"Pittsburgh, PA","location":null,"child_ids":[],"parent_id":null},{"id":4000912009,"name":"San Jose, CA","location":null,"child_ids":[],"parent_id":null}]},{"absolute_url":"https://job-boards.greenhouse.io/efficientcomputer/jobs/4021312009","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4016478009,"location":{"name":"San Jose, CA OR Pittsburgh, PA"},"metadata":null,"id":4021312009,"updated_at":"2026-06-01T19:26:47-04:00","requisition_id":"23","title":"Senior Software Optimization Engineer","company_name":"Efficient Computer","first_published":"2025-09-08T15:47:21-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;Efficient is developing the world’s most energy-efficient general-purpose computer processor. Efficient’s patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years. Our platform’s unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;We are seeking a \u0026lt;strong data-start=\u0026quot;497\u0026quot; data-end=\u0026quot;538\u0026quot;\u0026gt;Senior Software Optimization Engineer\u0026lt;/strong\u0026gt; to join our growing team. Efficient’s Senior Software Optimization Engineer will design, optimize, and deploy applications for the world’s most energy-efficient programmable processor (the “Fabric”). In this role, you will take ownership of complex, performance-critical applications, working closely with Efficient’s compiler team to implement customer requirements, validate software quality, and provide deep technical insight into compiler interactions. This position is a unique opportunity to work on cutting-edge hardware/software co-design, while making an immediate impact in building the next generation of embedded applications.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-start=\u0026quot;1217\u0026quot; data-end=\u0026quot;1354\u0026quot;\u0026gt;Independently design and implement complex embedded applications based on customer requirements, specifications, and existing code.\u0026lt;/li\u0026gt;\n\u0026lt;li data-start=\u0026quot;1357\u0026quot; data-end=\u0026quot;1461\u0026quot;\u0026gt;Drive application optimization using Efficient’s compiler and software stack targeting the Fabric.\u0026lt;/li\u0026gt;\n\u0026lt;li data-start=\u0026quot;1464\u0026quot; data-end=\u0026quot;1572\u0026quot;\u0026gt;Deploy and validate applications on the Fabric across software simulation and FPGA emulation environments.\u0026lt;/li\u0026gt;\n\u0026lt;li data-start=\u0026quot;1575\u0026quot; data-end=\u0026quot;1724\u0026quot;\u0026gt;Own performance and energy-efficiency analysis, developing benchmarks and methodologies to evaluate applications against customer requirements.\u0026lt;/li\u0026gt;\n\u0026lt;li data-start=\u0026quot;1727\u0026quot; data-end=\u0026quot;1849\u0026quot;\u0026gt;Identify, reproduce, and distill issues into minimum-viable test cases, conveying precise feedback to the compiler team.\u0026lt;/li\u0026gt;\n\u0026lt;li data-start=\u0026quot;1852\u0026quot; data-end=\u0026quot;1941\u0026quot;\u0026gt;Collaborate deeply with the compiler team to test, debug, and refine compiler features.\u0026lt;/li\u0026gt;\n\u0026lt;li data-start=\u0026quot;1944\u0026quot; data-end=\u0026quot;2052\u0026quot;\u0026gt;Contribute advanced optimizations to frameworks and libraries in domains such as DSP and machine learning.\u0026lt;/li\u0026gt;\n\u0026lt;li data-start=\u0026quot;2055\u0026quot; data-end=\u0026quot;2167\u0026quot;\u0026gt;Provide architectural feedback based on hands-on experience to influence both software and hardware evolution.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Qualifications \u0026amp;amp; Experience Requirements\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Must be an excellent embedded engineer with 8+ years of work experience\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;3+ years of C/C++ experience\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep knowledge of at least one embedded platform, such as MSP430, STM32, Ambiq Apollo, PIC32, or similar\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience developing and deploying applications under resource constraints\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience using non-standard build environments and compiler toolchains, especially for embedded systems\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience using industry standard development and debugging tools for embedded development\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong attention to detail, good work ethic, ability to work on multiple projects simultaneously, and good communication skills\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Good problem solving skills\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Desired Qualifications \u0026amp;amp; Experience Requirements\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience using LLVM, MLIR, GCC, or a similar compiler framework to develop compiler passes\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience building TinyML models and deploying models under severe resource constraints (e.g. limited memory)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience writing optimized BLAS and DSP kernels\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of computer architecture\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;We offer a competitive salary for this role, generally ranging from $160,000 to $210,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Why Join Efficient?\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Efficient offers a\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;competitive compensation and benefits package\u0026lt;/strong\u0026gt;, including\u0026lt;span class=\u0026quot;Apple-converted-space\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;401K match, company-paid benefits, equity program, paid parental leave, and flexibility\u0026lt;/strong\u0026gt;. We are committed to personal and professional development and strive to grow together as people and as a company.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4004090009,"name":"Optimization","child_ids":[],"parent_id":4001383009}],"offices":[{"id":4000913009,"name":"Pittsburgh, PA","location":null,"child_ids":[],"parent_id":null},{"id":4000912009,"name":"San Jose, CA","location":null,"child_ids":[],"parent_id":null}]}],"meta":{"total":13}}