{"jobs":[{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4702146005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4438884005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":"Hardware Engineering","value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Hardware Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4702146005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2611","title":"Active Electric Cable / Smart Cable Module Lead, AVP","company_name":"Astera Labs","first_published":"2026-06-03T19:03:01-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;div\u0026gt;\n\u0026lt;div id=\u0026quot;content\u0026quot; class=\u0026quot;highlighter-context page view\u0026quot; data-inline-comments-target=\u0026quot;true\u0026quot; data-testid=\u0026quot;page-content-only\u0026quot;\u0026gt;\n\u0026lt;div class=\u0026quot;_1bsb1osq _19pkidpf _2hwx1wug _otyridpf _18u01wug\u0026quot;\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;div id=\u0026quot;main-content\u0026quot; class=\u0026quot;wiki-content css-ki3ac2 e5xcnr80\u0026quot; data-testid=\u0026quot;pageContentRendererTestId\u0026quot; data-test-appearance=\u0026quot;full-width\u0026quot;\u0026gt;\n\u0026lt;div class=\u0026quot;renderer-overrides\u0026quot;\u0026gt;\n\u0026lt;div class=\u0026quot;ak-renderer-wrapper is-full-width cc-tmc94p\u0026quot;\u0026gt;\n\u0026lt;div class=\u0026quot;cc-1cnb4qn\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;h1 data-local-id=\u0026quot;6fd549ccf151\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;heading\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot; data-pm-slice=\u0026quot;1 3 []\u0026quot;\u0026gt;AVP, AEC/SCM Lead\u0026lt;/h1\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;91c09b895c72\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;We are seeking a highly experienced leader to drive high-speed product development and technology strategy across a portfolio of advanced interconnect solutions. This role is ideal for someone who combines deep technical expertise with strong cross-functional leadership, deep familiarity with cable manufacturing, and a track record of bringing complex products from concept through qualification and launch.\u0026lt;/p\u0026gt;\n\u0026lt;h2 data-local-id=\u0026quot;33027b6108ff\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;heading\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Role Overview\u0026lt;/h2\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;5a02ff70beb7\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;The AEC/SCM Lead will lead development across a range of high-speed electrical connectivity products, with primary focus on:\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;99a7002f-d1a8-4958-888a-fed716474a76\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;bd8099fb-4647-46b4-8956-c3edb8237e65\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;20820b4a6604\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Active electrical cables (AEC)\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;debc6e4c-8518-43fa-a9ff-7c8ba594dfac\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;a77c5f0143df\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Active copper cables (ACC)\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;b4e8578d-9996-4495-9bde-6e33b7b0c057\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;d5e0163318e0\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Smart cable modules (SCM)\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;22b66d88-7eaa-4a1e-950f-386443e73948\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;a6dde1653ee4\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Linear re-driver cables\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;004b759bafbd\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;This leader will own both technology roadmapping and execution, managing multidisciplinary teams spanning hardware, firmware, testing, and mechanical engineering.\u0026lt;/p\u0026gt;\n\u0026lt;h2 data-local-id=\u0026quot;60d1140a9347\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;heading\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/h2\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;32cfbac5-05c5-4f12-adbb-d282686a1a16\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;fcc6e1a3-b7c1-4d87-b949-4c0c62316cdd\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;a6f318d421f9\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Lead cross-functional engineering teams across Mechanical Engineering, Testing Engineering, Hardware Engineering, and Firmware Engineering.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;6cdb0c3d-f628-4753-93a9-1e8bc40002db\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;21ef8cb7d549\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Drive R\u0026amp;amp;D and new product development for active and passive high-speed electrical interconnect technologies.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;748f6229-9dbc-45ce-8ff9-455829c63ffe\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;aa92d6c4ea60\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Define and manage the technology roadmap and strategic planning aligned with customer and market needs.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;f2f11340-34d0-471c-a738-fa5dae4efe04\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;170bb7d6dcf7\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Oversee products through the full lifecycle, from concept, design, and qualification to launch.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;d9f10312-b4c8-40af-b7df-724a7f76e643\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;0231ee3ef18f\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Collaborate with Signal Integrity, NPI, QA, validation, and manufacturing teams to ensure product performance, quality, and reliability.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;b1938c57-0375-4421-84ad-bbdb891b17c7\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;3aee32359378\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Build and lead a strong technical team with competencies spanning:\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;2171a56a-ebfa-4202-ab22-17554e233746\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;6ef12c7a-1db3-489a-b92e-6d95f6b38d19\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;bf8b02b83319\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Schematic and layout design\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;1014d8c1-3307-4ccb-8b6d-ee78e556b224\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;88432bc91610\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;High-speed electrical interconnect design\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;4150b70c-33f5-4610-9193-a4b04a660ded\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;a1a1666911d6\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Firmware and software development\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;761a4971-f931-4df3-a6b1-17804da4395f\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;ac5a03ae539a\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;High-speed standards compliance\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;46b4868a-76ab-42bd-91ca-d400f6706dbe\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;48819bb197a6\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;FMEA, DFM, DFA\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;32aec81b-4949-4500-abd5-327b09bb5df9\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;b5565ebff35f\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Program management\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;0ec7bb40-27d9-4cd7-a1ed-e37310fdf682\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;3e29beef480c\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Product qualification\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;560bb608-76e0-4950-b558-0d7abfe32a7e\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;34cbf716c5ed\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Make both technical and business decisions to align product development with company strategy, customer requirements, and manufacturing realities.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h2 data-local-id=\u0026quot;24709cbe2ca6\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;heading\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Required Qualifications\u0026lt;/h2\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;5e7ff7b3-e304-4116-8867-2e2fcca7539e\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;a73f15dc-026b-4eda-a28a-b3c74c19c0f5\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;0940d67b9404\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Proven experience leading engineering development for high-speed electrical interconnect products, including significant experience with cable manufacturing.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;b195142c-09ec-4042-a885-9416036564f7\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;ff3bcf4968fb\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Strong background in R\u0026amp;amp;D, product development, and technology strategy.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;0256a558-35fe-462e-a762-4b89ece0cb86\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;1c00cb3d35f6\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Experience managing multidisciplinary engineering teams and cross-functional stakeholders.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;76a8c157-f6e8-45ac-ada8-241ab54570a1\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;3c215392f969\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Deep understanding of product quality, reliability, manufacturability, and validation processes.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;2db66428-137f-4d80-abda-15cc48061613\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;5f9919591c9e\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Ability to make both technical and business decisions.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;e24fafe3-b8f1-472d-a01b-3e5e7468688e\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;7cc4a8bc8967\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Experience with overseas (Asia) contract manufacturers\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h2 data-local-id=\u0026quot;a8af99bbdb6c\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;heading\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Preferred Qualifications\u0026lt;/h2\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;3eaaebc4-13ab-44ca-a7da-a7ff60a8dd3a\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;45bc633f-27cb-45ac-87d4-71b73806a5a8\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;878930bf57f1\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Advanced degree in Electrical Engineering, Mechanical Engineering, or a related field.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;be1493a1-bf9c-4901-8472-7676f1d8703b\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;a7a76d0d3f3b\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Experience with optical products and optical interconnect technologies is a plus.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;2812e71c-17d8-4236-b2c7-b78c0ab54752\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;2a3782b03189\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Mandarin language proficiency.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h2 data-local-id=\u0026quot;ecc91315b014\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;heading\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Ideal Candidate Profile\u0026lt;/h2\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;de8cfa77dd15\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;The ideal candidate is a technical leader who can balance innovation, execution, and team development. They should be comfortable driving both strategic roadmaps and day-to-day engineering decisions while partnering closely with product, operations, manufacturing, and customer-facing teams.\u0026lt;/p\u0026gt;\n\u0026lt;h2 data-local-id=\u0026quot;8d6ca1e90486\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;heading\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;What Success Looks Like\u0026lt;/h2\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;f35a4d3a-5535-4af7-aba9-1b99fcd4fa9b\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;680579e2-d9ab-42e7-9a92-56d9c10b82e5\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;51786291f4ed\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;A clear and differentiated technology roadmap\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;06450435-b6ec-4b70-b6b1-9d425a4ddfb8\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;fecc2d2c113a\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Efficient execution of new product development programs\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;e3ce559b-40f3-4076-bc1b-c81a504a5c92\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;8be4b05ff4e8\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Strong collaboration across engineering, validation, NPI, QA, and manufacturing\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;2e6d0fae-a7b9-46e6-91ab-7529a153a922\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;c3d4380d3993\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Successful launch of reliable, high-performance products aligned with market needs\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Base salary range is $280,000 to $310,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025526005,"name":"Hardware Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4738757005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4456871005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"Taiwan","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Taipei","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Product Applications Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4738757005,"updated_at":"2026-09-28T21:23:52-04:00","requisition_id":null,"title":"AE| Principal Product Application Engineer (Scorpio)","company_name":"Astera Labs","first_published":"2026-09-28T21:17:31-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Job Description:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As an Astera Labs Principal Product Application Engineer, you will need to provide technical guidance to ODMs to overcome design challenges, generate collateral for existing and new products, and drive innovation by providing insightful feedback to other internal teams to continuously improve products and processes. We need experience supporting the development and designing-in of semiconductor products for PCIe/CXL. There are opportunities to support key ODMs directly, and also to dive deep in the lab to address the challenges associated with leading edge semiconductor products.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, Master’s is preferred.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Minimum of 10 years’ experience designing in complex SoC/silicon products with a high speed (preferably PCIe) interface.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!\u0026lt;strong\u0026gt;\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Experience\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong working knowledge of PCIe LTSSM at a physical layer level, associated standards, and debug. Most recent experience with PCIe 4.0 at a minimum, some experience with 5.0/CXL preferred.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Silicon/System bring-up and debug experience in customer systems.\u0026amp;nbsp;\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Technical ownership of issue resolution: Driving and directing internal teams, and driving communication to customers through FAE and sales teams.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Firsthand experience with lab equipment such as protocol analyzers/exercisers, high-speed oscilloscopes, or BERTs.\u0026amp;nbsp;\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Technical writing skills to generate clear, precise documentation including application notes and similar guides for internal and customer-facing audiences.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Global customer engagement support, with travel as required for on-site activities, reviews, and system bring-up.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred experience\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Triaging complex customer reported issues which require taking into account multiple layers of conditions; for instance, silicon, firmware, hardware board design, and system environment.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Development/support for PCIe or Ethernet Switch or Retimer products.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;PCIe compliance testing methodology and troubleshooting.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Comfort working with software/firmware associated with semiconductor products, such as; Firmware development with C-language, scripting with Python or other equivalent programming languages.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Understanding of Data Center systems like Servers, JBOGs/JBODs, Networking switches/routers/interconnects etc.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184703005,"name":"Fabrics \u0026 Controllers Products (US_F\u0026C Prod)","child_ids":[],"parent_id":null}],"offices":[{"id":4002874005,"name":"Taiwan","location":"Taipei, Taiwan","child_ids":[4061060005,4009035005],"parent_id":null}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4733710005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4454493005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Design Verification","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4733710005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2026-517","title":"Design Verification Tech Lead- SerDes/PHY IP","company_name":"Astera Labs","first_published":"2026-09-21T13:11:39-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;div class=\u0026quot;job__header\u0026quot;\u0026gt;\n\u0026lt;div class=\u0026quot;job__title\u0026quot;\u0026gt;\n\u0026lt;h1 class=\u0026quot;section-header section-header--large font-primary\u0026quot;\u0026gt;Design Verification Tech Lead- SerDes/PHY IP\u0026lt;/h1\u0026gt;\n\u0026lt;div class=\u0026quot;job__location\u0026quot;\u0026gt;\n\u0026lt;div\u0026gt;San Jose, California, United States\u0026lt;/div\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;job__description body\u0026quot;\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;h2 class=\u0026quot;wnfdnth _1ibi0s33y _1ibi0s34u\u0026quot; data-pm-slice=\u0026quot;1 1 []\u0026quot;\u0026gt;Role Overview\u0026lt;/h2\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Astera Labs is hiring a Principal Design Verification Engineer to own functional verification of our high-speed SerDes/PHY IP — the connectivity engine powering rack-scale AI infrastructure. You will architect verification environments, drive coverage closure, and ensure first-pass silicon success on the analog/digital boundary that defines next-generation AI systems.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;This is a high-impact, hands-on role at the heart of Astera Labs\u0026#39; hyper-growth story. You\u0026#39;ll partner directly with PHY analog/mixed-signal designers, digital architects, and SoC integration teams to verify multi-Gbps SerDes blocks that ship into the world\u0026#39;s most advanced AI platforms, including UALink, UCIe, PCIe Gen 6/Gen 7, and Ethernet-based connectivity products.\u0026lt;/p\u0026gt;\n\u0026lt;h2 class=\u0026quot;wnfdnth _1ibi0s33y _1ibi0s34u\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/h2\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdnte\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Verification Architecture \u0026amp;amp; Strategy\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Architect UVM-based verification environments for SerDes/PHY IP, including PMA, PCS, and PHY-MAC interface layers\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Define verification plans, coverage models, and sign-off criteria for high-speed serial link blocks\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Drive methodology decisions across analog/mixed-signal co-simulation, gate-level simulation, and emulation flows\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdnte\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Execution \u0026amp;amp; Coverage Closure\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Develop SystemVerilog/UVM testbenches, sequences, scoreboards, and reference models for multi-Gbps SerDes lanes\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Execute functional, performance, and corner-case verification across equalization, CDR, training, and link bring-up scenarios\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Lead coverage analysis and closure, debug failures with designers, and drive regressions to clean tape-out\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdnte\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Physical Layer \u0026amp;amp; Protocol Verification\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Verify PHY behavior against industry specifications including PCIe Gen 6/Gen 7, UALink, UCIe, and Ethernet PHY standards\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Model and validate channel behavior, link training state machines, and analog handoff scenarios\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Partner with analog/AMS designers on Real Number Modeling (RNM) and behavioral models for SerDes blocks\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdnte\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional Leadership\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Mentor junior DV engineers and set technical direction across the verification team\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Collaborate with SoC integration, firmware, post-silicon validation, and customer engineering teams\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Contribute to verification IP reuse strategy and tooling improvements across product lines\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h2 class=\u0026quot;wnfdnth _1ibi0s33y _1ibi0s34u\u0026quot;\u0026gt;Basic Qualifications\u0026lt;/h2\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, Computer Engineering, or related field\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;5+ years of design verification experience on high-speed SerDes, PHY, or mixed-signal IP\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Strong understanding of the physical layer, including equalization (CTLE, DFE, FFE), CDR, training sequences, and link bring-up\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Expert-level proficiency in SystemVerilog and UVM\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Hands-on experience with analog/mixed-signal co-simulation and Real Number Modeling (RNM)\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Working knowledge of one or more high-speed serial protocols: PCIe, UALink, UCIe, Ethernet, or CXL\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h2 class=\u0026quot;wnfdnth _1ibi0s33y _1ibi0s34u\u0026quot;\u0026gt;Preferred Qualifications\u0026lt;/h2\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;MS or PhD in Electrical Engineering or Computer Engineering\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Experience verifying PCIe Gen 6/Gen 7, UALink, or UCIe SerDes/PHY IP\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Familiarity with emulation platforms (Palladium, Veloce, or ZeBu) and gate-level simulation flows\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Scripting proficiency in Python or Perl for verification automation and regression management\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Experience supporting post-silicon bring-up and correlating pre-silicon coverage with silicon results\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Proven ability to lead technically across a multi-disciplinary team in a fast-paced environment\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Salary range is $160,000 to $200,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184262005,"name":"Design Verification SCE","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4723233005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4449065005,"location":{"name":"Bengaluru, Karnataka, India"},"metadata":[{"id":12122734005,"name":"Country","value":"India","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Bengaluru","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"DFT","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4723233005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":null,"title":"DFT Engineer","company_name":"Astera Labs","first_published":"2026-09-21T02:18:41-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p8i6j01 paragraph\u0026quot;\u0026gt;Astera Labs is hiring a \u0026lt;strong\u0026gt;Tech Lead Design Engineer\u0026lt;/strong\u0026gt; to help architect and deliver the connectivity silicon powering the world\u0026#39;s largest AI clusters. You\u0026#39;ll own design execution on complex blocks across our purpose-built products, working at the cutting edge of PCIe, CXL, Ethernet, and emerging rack-scale interconnect technologies.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p8i6j01 paragraph\u0026quot;\u0026gt;This is a high-impact technical role at a hyper-growth company. You\u0026#39;ll partner closely with architecture, verification, DFT, and physical design teams to take features from spec to silicon, while contributing to the design methodology that scales with our roadmap. If you want to ship silicon that defines AI infrastructure, this is the team.\u0026lt;/p\u0026gt;\n\u0026lt;h3 class=\u0026quot;_9k2iva0 p8i6j0c _1ibi0s314 heading3 _9k2iva1\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/h3\u0026gt;\n\u0026lt;ul class=\u0026quot;p8i6j07 p8i6j02\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;p8i6j0a\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;RTL Design \u0026amp;amp; Implementation\u0026lt;/strong\u0026gt;\n\u0026lt;ul class=\u0026quot;p8i6j08 p8i6j02\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;p8i6j0a\u0026quot;\u0026gt;Own RTL design for assigned blocks from microarchitecture through synthesis sign-off\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;p8i6j0a\u0026quot;\u0026gt;Develop high-quality, synthesizable Verilog/SystemVerilog with strong attention to PPA\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;p8i6j0a\u0026quot;\u0026gt;Drive design reviews, lint, CDC, and timing closure activities to silicon-ready quality\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;p8i6j0a\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional Execution\u0026lt;/strong\u0026gt;\n\u0026lt;ul class=\u0026quot;p8i6j08 p8i6j02\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;p8i6j0a\u0026quot;\u0026gt;Partner with architecture to translate specifications into implementation-ready microarchitecture\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;p8i6j0a\u0026quot;\u0026gt;Collaborate with verification on testplans, coverage closure, and bug triage\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;p8i6j0a\u0026quot;\u0026gt;Work with DFT and physical design teams on scan, BIST, floorplanning, and timing closure\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;p8i6j0a\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Technical Leadership \u0026amp;amp; Quality\u0026lt;/strong\u0026gt;\n\u0026lt;ul class=\u0026quot;p8i6j08 p8i6j02\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;p8i6j0a\u0026quot;\u0026gt;Mentor junior engineers and contribute to design methodology, scripts, and best practices\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;p8i6j0a\u0026quot;\u0026gt;Debug complex pre-silicon and post-silicon issues across RTL, gate-level, and emulation environments\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;p8i6j0a\u0026quot;\u0026gt;Drive structured, data-driven design decisions in support of aggressive tapeout schedules\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h3 class=\u0026quot;_9k2iva0 p8i6j0c _1ibi0s314 heading3 _9k2iva1\u0026quot;\u0026gt;Basic Qualifications\u0026lt;/h3\u0026gt;\n\u0026lt;ul class=\u0026quot;p8i6j07 p8i6j02\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;p8i6j0a\u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, Computer Engineering, or related field\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;p8i6j0a\u0026quot;\u0026gt;5+ years of digital design experience, including at least one full chip from spec to tapeout\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;p8i6j0a\u0026quot;\u0026gt;Strong proficiency in Verilog/SystemVerilog, RTL coding, and synthesis flows\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;p8i6j0a\u0026quot;\u0026gt;Hands-on experience with timing closure, CDC, lint, and low-power design techniques\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;p8i6j0a\u0026quot;\u0026gt;Solid understanding of high-speed serial interfaces (PCIe, Ethernet, or similar) and SoC integration\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h3 class=\u0026quot;_9k2iva0 p8i6j0c _1ibi0s314 heading3 _9k2iva1\u0026quot;\u0026gt;Preferred Qualifications\u0026lt;/h3\u0026gt;\n\u0026lt;ul class=\u0026quot;p8i6j07 p8i6j02\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;p8i6j0a\u0026quot;\u0026gt;MS or PhD in Electrical Engineering or Computer Engineering\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;p8i6j0a\u0026quot;\u0026gt;Experience with PCIe Gen5/Gen6, CXL, UALink, UCIe, or Ethernet MAC/PCS designs\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;p8i6j0a\u0026quot;\u0026gt;Familiarity with formal verification, emulation, or assertion-based methodologies\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;p8i6j0a\u0026quot;\u0026gt;Background in advanced process nodes (7nm, 5nm, or below)\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;p8i6j0a\u0026quot;\u0026gt;Strong debug skills across pre-silicon and post-silicon environments\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p class=\u0026quot;p8i6j01 paragraph\u0026quot;\u0026gt;Salary range is $133,200 to $185,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184263005,"name":"Design for Test CCE1","child_ids":[],"parent_id":null}],"offices":[{"id":4049113005,"name":"Bengaluru","location":"India","child_ids":[],"parent_id":4052109005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4649842005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4414084005,"location":{"name":"Tel Aviv-Yafo, Tel Aviv District, Israel"},"metadata":[{"id":12122734005,"name":"Country","value":"Israel","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Tel-Aviv","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":"Silicon Engineering CCE2","value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Physical Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4649842005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2200","title":"DFT Engineer","company_name":"Astera Labs","first_published":"2026-01-15T18:57:49-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is establishing a strategic R\u0026amp;amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical \u0026#39;data bottlenecks\u0026#39; enabling the future of AI at scale. As we expand our presence in Israel, we\u0026#39;re seeking a visionary\u0026lt;strong\u0026gt;\u0026amp;nbsp;DFT Engineer \u0026lt;/strong\u0026gt;to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world\u0026#39;s largest AI clusters.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As a\u0026amp;nbsp;\u0026lt;strong\u0026gt;DFT Engineer\u0026lt;/strong\u0026gt;\u0026amp;nbsp;at Astera Labs, you will be at the intersection of architecture, design, and production. You won\u0026#39;t just run tools—you will be a foundational member of the team responsible for the entire lifecycle of our silicon\u0026#39;s reliability. From defining initial DFT architecture to supporting post-silicon bring-up, your work ensures that the backbone of AI infrastructure connectivity is flawless and scalable. If you thrive on solving complex challenges in deep-submicron processes and want to establish world-class DFT methodologies, this is your opportunity.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;strong data-olk-copy-source=\u0026quot;MessageBody\u0026quot;\u0026gt;DFT Architecture \u0026amp;amp; Strategy\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Be part of the DFT journey from high-level architecture definition and RTL design to backend implementation and post-production support\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop comprehensive Design-for-Testability (DFT) strategies for next-generation connectivity platforms, ensuring chips meet the highest quality standards\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Design and implement DFT architectures including JTAG/iJTAG, MBIST, Scan, and ATPG for high-end devices\u0026lt;br\u0026gt;\u0026lt;br\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;strong\u0026gt;Test Pattern Development \u0026amp;amp; Optimization\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Generate and optimize high-quality test and debug patterns for production\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Perform Static Timing Analysis (STA) for DFT modes and conduct gate-level simulations to ensure robust performance\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive test coverage and quality metrics to meet stringent manufacturing requirements\u0026lt;br\u0026gt;\u0026lt;br\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional Collaboration \u0026amp;amp; Methodology Innovation\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Act as a multidisciplinary bridge, collaborating closely with Architecture, Verification, and Backend teams to ensure seamless integration and optimal QoR\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Participate in developing and maintaining cutting-edge DFT implementation flows\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Automate and improve methodologies using advanced scripting and tools\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-olk-copy-source=\u0026quot;MessageBody\u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering or related technical field\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;4+ years of hands-on experience in DFT roles at semiconductor companies\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Experience in DFT flows and architectures including JTAG/iJTAG, MBIST, Scan, and ATPG\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Good understanding of logic design, verification, debug, and Static Timing Analysis (STA)\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Scripting proficiency in Tcl, Perl, Python, or Shell for automation and innovation\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-olk-copy-source=\u0026quot;MessageBody\u0026quot;\u0026gt;Master\u0026#39;s degree in\u0026amp;nbsp;Electrical Engineering or related field\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Experience with industry-standard EDA tools from Synopsys (TestMAX) or Siemens (Tessent)\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Experience in chip\u0026amp;nbsp;bring-up and mass production activities\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Background in advanced process technologies (7nm and below)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Knowledge of high-speed interface protocols (PCIe, Ethernet, CXL, UALink) and their specific test requirements\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Excellent communication skills with ability to work effectively in global team environments\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184339005,"name":"Silicon Engineering CCE2","child_ids":[],"parent_id":null}],"offices":[{"id":4008937005,"name":"Israel","location":"Israel","child_ids":[4052111005,4061058005,4056876005],"parent_id":null}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4731807005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4453484005,"location":{"name":"Toronto, Ontario, Canada"},"metadata":[{"id":12122734005,"name":"Country","value":"Canada","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Toronto","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Digital Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4731807005,"updated_at":"2026-10-08T03:48:23-04:00","requisition_id":"2026-010","title":"Digital Design Manager","company_name":"Astera Labs","first_published":"2026-09-15T13:32:48-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;This role will lead day-to-day DFT architecture and execution for Astera Labs\u0026#39; signal-conditioning products, helping deliver highly testable, high-quality silicon for rack-scale AI infrastructure. You will partner with design, verification, physical design, packaging, product engineering, and manufacturing teams to improve coverage, yield, diagnostics, and production readiness across advanced multi-die products.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;As Astera Labs scales its purpose-built connectivity platform, you will help establish practical DFT methods for high-speed PCIe and Ethernet signal-conditioning products, with a strong focus on SerDes physical-layer performance, signal integrity, and production robustness. The role offers hands-on technical ownership, opportunities to mentor engineers, and direct influence on products that keep next-generation AI systems connected, observable, and reliable.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdntf\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;DFT Architecture \u0026amp;amp; Planning\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdntf\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Define DFT plans for signal-conditioning products supporting high-speed PCIe and Ethernet connectivity and advanced multi-die packaging configurations.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Develop test-access, coverage, observability, and diagnostic strategies for die-to-die interfaces, interposers, and package-level integration.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Partner with design and physical design teams to balance DFT area, timing, routing, and manufacturability.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;DFT Implementation \u0026amp;amp; Silicon Readiness\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdntf\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Drive scan insertion, ATPG, compression, MBIST, LBIST, JTAG/IJTAG, and high-speed SerDes BIST requirements.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Establish coverage targets and review ATPG results, pattern quality, test time, and ATE cost.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Support tape-out, wafer sort, packaged-device test, silicon bring-up, characterization, and production ramp.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Quality, Yield \u0026amp;amp; Diagnostics\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdntf\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Collaborate with product, manufacturing, assembly, and test engineering on yield learning, failure analysis, and root-cause resolution.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Develop pre-bond, post-bond, and package-level test approaches for known-good-die screening and advanced packaging.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Improve diagnostic capabilities for silicon, package, and system-level issues.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Technical Leadership \u0026amp;amp; Collaboration\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdntf\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Mentor DFT engineers and coordinate execution across product development milestones.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Partner with OSATs, ATE vendors, packaging partners, and internal stakeholders to resolve technical issues and maintain schedules.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Communicate risks, trade-offs, and recommendations clearly to cross-functional teams.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdntf\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;10-15 years of experience in Digital Design engineering or related semiconductor design and test work.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Hands-on experience with scan, ATPG, compression, MBIST, LBIST, JTAG, and/or IJTAG methodologies.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Understanding of the ASIC design flow from RTL through GDS and DFT signoff.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Experience with DFT EDA tools such as Synopsys DFT Compiler, TetraMAX, DFTMAX, Siemens Tessent, or equivalent.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Understanding of high-speed signal conditioning, SerDes physical-layer behavior, signal integrity, die-to-die connectivity, or advanced packaging test requirements.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdntf\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Master’s or PhD in Electrical Engineering, Computer Engineering, or a related field.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Experience with 2.5D or 3D integration, silicon interposers, TSVs, hybrid bonding, micro-bumps, chiplets, or known-good-die strategies.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Knowledge of IEEE 1838, IEEE 1149.1, IEEE 1687, and relevant JEDEC standards for multi-die testing.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Experience with PCIe, Ethernet, UALink, and high-speed SerDes physical-layer validation or test.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Familiarity with ATE platforms, wafer probe, OSAT engagement, production test economics, and yield analysis.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Salary range is CAD $198,000 to CAD $220,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184340005,"name":"Silicon Engineering SCE","child_ids":[],"parent_id":null}],"offices":[{"id":4000119005,"name":"Toronto","location":"Canada","child_ids":[],"parent_id":4004709005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4716946005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4445886005,"location":{"name":"Taipei, Taiwan"},"metadata":[{"id":12122734005,"name":"Country","value":"Taiwan","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Taipei","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Engineering Operations","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4716946005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":null,"title":"Director Engineering Operations","company_name":"Astera Labs","first_published":"2026-07-21T13:08:25-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;PDq2pG_selectionAnchorContainer\u0026quot; data-section-id=\u0026quot;1v6q7mi\u0026quot; data-start=\u0026quot;170\u0026quot; data-end=\u0026quot;193\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Job Description\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p data-start=\u0026quot;195\u0026quot; data-end=\u0026quot;852\u0026quot;\u0026gt;As the\u0026lt;strong\u0026gt; \u0026lt;/strong\u0026gt;Director of Product \u0026amp;amp; Test Engineering, you will lead Astera Labs\u0026#39; Product and Test Engineering organization supporting new product introductions (NPI) and high-volume manufacturing across our Asia OSAT partners. You will build and develop a high-performing engineering team responsible for product qualification, ATE test development, characterization, yield improvement, and manufacturing support throughout the product lifecycle. Working closely with Design Engineering, Silicon Validation, Quality, Manufacturing, and Supply Chain teams, you will drive operational excellence while ensuring successful product execution and customer delivery.\u0026lt;/p\u0026gt;\n\u0026lt;p data-section-id=\u0026quot;19emh4z\u0026quot; data-start=\u0026quot;859\u0026quot; data-end=\u0026quot;887\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul data-start=\u0026quot;889\u0026quot; data-end=\u0026quot;1606\u0026quot;\u0026gt;\n\u0026lt;li data-section-id=\u0026quot;14wybrm\u0026quot; data-start=\u0026quot;889\u0026quot; data-end=\u0026quot;1026\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;Minimum of 12+ years of experience in post-silicon product development dealing with high-speed XCVR (product, test, or validation).\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-section-id=\u0026quot;1mbjop4\u0026quot; data-start=\u0026quot;1027\u0026quot; data-end=\u0026quot;1073\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;Experience working with PCIe Gen4 and above.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-section-id=\u0026quot;kzwdop\u0026quot; data-start=\u0026quot;1074\u0026quot; data-end=\u0026quot;1166\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;5+ years of leadership experience managing Product and Test Engineering organizations.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-section-id=\u0026quot;5qmhnu\u0026quot; data-start=\u0026quot;1167\u0026quot; data-end=\u0026quot;1253\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;Experience defining and running standards-based qualification (product and package).\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-section-id=\u0026quot;1jlte2a\u0026quot; data-start=\u0026quot;1254\u0026quot; data-end=\u0026quot;1366\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;Strong academic/technical background in Electrical or Computer Engineering; Bachelor\u0026#39;s required; MS preferred.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-section-id=\u0026quot;h0k622\u0026quot; data-start=\u0026quot;1367\u0026quot; data-end=\u0026quot;1474\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;Strong problem-solving skills involving system-level analysis with test hardware, test programs, and DUT.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-section-id=\u0026quot;1nz7a1d\u0026quot; data-start=\u0026quot;1475\u0026quot; data-end=\u0026quot;1524\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;Digital and analog circuit-level understanding.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-section-id=\u0026quot;r9hy81\u0026quot; data-start=\u0026quot;1525\u0026quot; data-end=\u0026quot;1606\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;Excellent communication, leadership, and cross-functional collaboration skills.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p data-section-id=\u0026quot;hmpmoc\u0026quot; data-start=\u0026quot;1613\u0026quot; data-end=\u0026quot;1640\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Required Experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul data-start=\u0026quot;1642\u0026quot; data-end=\u0026quot;2559\u0026quot;\u0026gt;\n\u0026lt;li data-section-id=\u0026quot;mt75hu\u0026quot; data-start=\u0026quot;1642\u0026quot; data-end=\u0026quot;1729\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;Build, lead, and grow a strong Product \u0026amp;amp; Test Engineering organization in Taiwan.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-section-id=\u0026quot;se5h2q\u0026quot; data-start=\u0026quot;1730\u0026quot; data-end=\u0026quot;1807\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;Define engineering priorities and resource planning supporting NPI and HVM.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-section-id=\u0026quot;d64fdz\u0026quot; data-start=\u0026quot;1808\u0026quot; data-end=\u0026quot;1954\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;Proven track record supporting seamless production of semiconductor products through global OSAT partners across the complete product lifecycle.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-section-id=\u0026quot;2p3s6i\u0026quot; data-start=\u0026quot;1955\u0026quot; data-end=\u0026quot;2058\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;Hands-on experience with Advantest V93000 ATE platform and developing wafer sort/final test programs.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-section-id=\u0026quot;dyphu2\u0026quot; data-start=\u0026quot;2059\u0026quot; data-end=\u0026quot;2155\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;Strong knowledge of PCIe Gen4+, PAM4 SerDes, Ethernet (25G+), and/or LPDDR4/LPDDR5 interfaces.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-section-id=\u0026quot;5918ew\u0026quot; data-start=\u0026quot;2156\u0026quot; data-end=\u0026quot;2254\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;Drive product qualification, yield improvement, manufacturing readiness, and production release.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-section-id=\u0026quot;1uvckqr\u0026quot; data-start=\u0026quot;2255\u0026quot; data-end=\u0026quot;2389\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;Partner closely with Design, Validation, Quality, Manufacturing, and Supply Chain teams to resolve product and manufacturing issues.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-section-id=\u0026quot;dd684e\u0026quot; data-start=\u0026quot;2390\u0026quot; data-end=\u0026quot;2461\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;Strong data analysis skills using JMP, Spotfire, or equivalent tools.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-section-id=\u0026quot;1ujfl3w\u0026quot; data-start=\u0026quot;2462\u0026quot; data-end=\u0026quot;2559\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;Mentor engineering managers and senior engineers while building a high-performing organization.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184278005,"name":"Engineering Operations CCE1","child_ids":[],"parent_id":null}],"offices":[{"id":4009035005,"name":"Taipei","location":"Taiwan","child_ids":[],"parent_id":4002874005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4704344005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4439956005,"location":{"name":"Hyderabad, Telangana, India"},"metadata":[{"id":12122734005,"name":"Country","value":"India","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Hyderabad","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":"Physical Design CCE1","value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Physical Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4704344005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2634","title":"Director, Physical Design","company_name":"Astera Labs","first_published":"2026-06-19T06:03:51-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Director, Physical Design\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Location:\u0026lt;/strong\u0026gt; Hyderabad, India\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;About Astera Labs\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is a global leader in purpose-built connectivity solutions for AI and cloud infrastructure. Our semiconductor products power the world\u0026#39;s leading cloud service providers, hyperscalers, and server OEMs. As we scale our next-generation ASIC programs, we are building a world-class Physical Design team in Hyderabad to drive silicon success from RTL to GDSII.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is seeking a \u0026lt;strong\u0026gt;Director, Physical Design\u0026lt;/strong\u0026gt; to lead and grow our Physical Design function in Hyderabad. This is a senior leadership role responsible for building and managing a high-performing PD team, driving physical implementation of complex, high-speed connectivity ASICs, and establishing best-in-class design methodology and flows.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;The ideal candidate brings deep hands-on expertise in full-chip physical design at advanced nodes, a proven track record of successful tapeouts, and the leadership ability to scale a team and deliver results in a fast-paced, high-growth environment. This role will work closely with global PD, RTL, DV, DFT, and packaging teams to ensure first-pass silicon success.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Leadership \u0026amp;amp; Team Building\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Build, lead, and mentor a high-performing Physical Design team in Hyderabad across PnR, STA, EMIR/Power Integrity, and CAD/methodology functions\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Define team structure, hiring roadmap, and career development paths for PD engineers\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Foster a culture of technical excellence, ownership, and continuous improvement\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Partner with global PD leadership (US and Israel sites) to align on strategy, methodology, and execution priorities\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Physical Design Execution\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Own end-to-end physical implementation of complex SoCs/ASICs from floor planning through GDSII signoff\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive floor planning, placement, clock tree synthesis (CTS), routing, timing closure, power analysis (IR drop/EM), and physical verification (DRC/LVS)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead timing closure across multiple corners and modes (MMMC), ensuring robust STA signoff at advanced nodes (5nm and below)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Oversee power integrity and reliability analysis (IR drop, EM) to meet design quality and manufacturability targets\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Manage tapeout schedules,milestones, and cross-functional dependencies to deliver on time and within PPA targets\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Methodology \u0026amp;amp; CAD\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Establish and continuously improve PD flows, methodologies, checklists, and best practices for first-pass success\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Evaluate and deploy EDA tools (Cadence Innovus, Synopsys Fusion Compiler, PrimeTime, Calibre, RedHawk/Voltus, StarRC, etc.)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive automation and scripting (Tcl, Python, Perl) to improve turnaround time and design quality\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with EDA vendors on tool evaluation, adoption, and methodology improvements\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional Collaboration\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Partner closely with RTL, DV, DFT, packaging, and architecture teams to enable seamless integration of complex subsystems (SerDes, high-speed PHYs, die-to-die interfaces, etc.)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Provide physical design input during architecture and floorplan feasibility studies, die sizing, and IP evaluation\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Represent the Hyderabad PD team in global design reviews, tapeout readiness reviews, and leadership forums\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor\u0026#39;s or master’s degree in electrical engineering, Electronics, or Computer Science\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;18+ years of experience in ASIC physical design, with at least 5 years in a leadership or management role\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Should be hands on with a proven track record of multiple successful tapeouts at advanced nodes (7nm or below); experience at 5nm/3nm strongly preferred\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep hands-on expertise in full-chip physical design: floorplanning, PnR, CTS, STA, IR/EM analysis, and physical verification\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong proficiency with industry-standard EDA tools: Cadence Innovus, Synopsys Fusion Compiler/IC Compiler, PrimeTime, Calibre, RedHawk/Voltus\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with high-speed interface IPs such as SerDes, PCIe, CXL, or die-to-die (D2D/UCIe) interconnects\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong scripting skills in Tcl, Python, or Perl\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Demonstrated ability to build and lead global, cross-functional engineering teams\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience with chiplet architecture, UCIe interfaces, or die-to-die physical integration\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with low-power design techniques (UPF/CPF, multi-voltage domains)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience working with TSMC advanced nodes and TSMC tapeout processes\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Background in networking, storage, or AI/ML SoC designs\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong cross-functional collaboration skills with RTL, DFT, packaging, and silicon operations teams\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience establishing a PD center of excellence or greenfield PD team\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Why Astera Labs\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Work on cutting-edge connectivity ASICs powering the world\u0026#39;s largest AI and cloud infrastructure\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Join a high-growth, publicly traded semiconductor company with a strong innovation culture\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead and shape a strategic PD center in Hyderabad with global impact\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Competitive compensation including base salary, performance bonus, and RSU equity.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4065038005,"name":"Hyderabad","location":"India","child_ids":[],"parent_id":4052109005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4719143005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4438937005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Business Operations","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4719143005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2615","title":"Director, Pricing Strategy","company_name":"Astera Labs","first_published":"2026-07-28T12:33:06-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;h3 class=\u0026quot;wnfdnth _1ibi0s33y _1ibi0s34u\u0026quot; data-pm-slice=\u0026quot;1 1 []\u0026quot;\u0026gt;Role Overview\u0026lt;/h3\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Astera Labs is seeking a highly strategic and commercially focused \u0026lt;strong\u0026gt;Director, Pricing Strategy\u0026lt;/strong\u0026gt; to define and drive the company\u0026#39;s global pricing strategy across its semiconductor, connectivity, software, and platform solutions portfolio.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;This role sits at the center of Astera Labs\u0026#39; commercial decision-making and is accountable for three outcomes:\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdnte\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Define pricing and monetization strategies that strengthen competitive positioning, reflect customer value, and support profitable growth across existing and emerging businesses.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Institutionalize pricing governance through clear policies, guardrails, approval models, and decision frameworks that improve speed, consistency, and discipline.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Build a scalable pricing capability over time, including the processes, metrics, tools, and organizational foundations needed to support the company\u0026#39;s next phase of growth.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;The ideal candidate combines deep semiconductor industry experience with strong business acumen, financial expertise, market insight, and executive presence. This individual understands how technology differentiation, product performance, customer value, competitive dynamics, costs, and market demand interact to influence pricing decisions.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;This leader must be equally effective shaping internal strategy and representing Astera Labs externally in senior-level customer and partner pricing discussions. They should be comfortable engaging directly with customer procurement, business, and product stakeholders, especially in complex or ambiguous situations where pricing positions are still being developed.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;h3 class=\u0026quot;wnfdnth _1ibi0s33y _1ibi0s34u\u0026quot; data-pm-slice=\u0026quot;1 3 []\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/h3\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdnte\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Pricing Strategy \u0026amp;amp; Monetization\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdnte\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Define and evolve Astera Labs\u0026#39; global pricing strategy across semiconductor products, software offerings, connectivity solutions, and strategic commercial programs.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Develop pricing methodologies that balance customer value, competitive positioning, market adoption, profitability, and long-term business objectives.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Partner with Product Management to develop pricing, packaging, and monetization strategies for new products, platforms, and emerging business opportunities.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Analyze market dynamics, customer buying behavior, competitive offerings, and industry trends to identify pricing opportunities and risks.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Develop and maintain pricing models that incorporate value-based pricing, competitive benchmarking, product cost structures, and financial objectives.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Evaluate price-per-performance positioning and other key market metrics to ensure Astera Labs remains competitively positioned across target markets and customer segments.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Develop pricing recommendations using customer value, competitive intelligence, market positioning, cost structures, and strategic objectives.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Influence product portfolio strategy through pricing insights, profitability analysis, market intelligence, and commercial recommendations.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Pricing Governance \u0026amp;amp; Frameworks\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdnte\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Develop and own Astera Labs\u0026#39; pricing governance framework, including pricing policies, discount governance, pricing authority levels, approval processes, and exception management.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Establish scalable pricing processes that balance business agility with financial discipline and margin objectives.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Define pricing approval workflows and governance models for strategic customer opportunities, pricing exceptions, discount approvals, and new product introductions.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Create and maintain pricing guardrails, discount thresholds, pricing corridors, and escalation procedures that improve pricing consistency across the organization.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Partner with Executive Leadership, Finance, Sales, and Product Management to ensure pricing governance aligns with company strategy and growth objectives.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Provide guidance on discounting policies, customer segmentation strategies, list pricing, pricing structures, and deal governance.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional \u0026amp;amp; Executive Partnership\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdnte\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Facilitate cross-functional pricing reviews for strategic opportunities, major customer negotiations, new product introductions, and significant commercial initiatives.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Support executive reviews of strategic customer opportunities, pricing exceptions, and complex commercial agreements.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Partner with Finance and Operations to understand product cost drivers, manufacturing economics, supply chain dynamics, and gross margin performance.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Collaborate closely with Sales, Product Management, Finance, Marketing, Operations, and Executive Leadership to drive alignment on commercial decisions.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Customer Engagement \u0026amp;amp; Scaling the Function\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdnte\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Engage directly in senior-level customer and partner pricing discussions where needed, particularly for strategic accounts, new market opportunities, or complex negotiations.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Establish key pricing performance metrics and reporting frameworks to monitor pricing effectiveness, win rates, margin performance, and price realization.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Help build and scale Astera Labs\u0026#39; pricing capabilities, processes, tools, and organizational expertise over time.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h3 class=\u0026quot;wnfdnth _1ibi0s33y _1ibi0s34u\u0026quot;\u0026gt;Basic Qualifications\u0026lt;/h3\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdnte\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Business, Economics, Finance, Engineering, Marketing, or a related field.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;10+ years of experience in pricing strategy, product marketing, business management, corporate strategy, finance, product management, commercial operations, or related leadership roles.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Significant experience within the semiconductor industry or adjacent technology sectors relevant to AI infrastructure, connectivity, networking, data center, compute, or cloud infrastructure markets.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Demonstrated experience developing and executing pricing strategies for semiconductor or highly technical technology products.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Strong understanding of semiconductor business models, pricing frameworks, customer buying behavior, and competitive market dynamics.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Experience developing pricing strategies that incorporate technology differentiation, customer value, market positioning, cost structures, and profitability objectives.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Experience evaluating market price points, price-per-performance positioning, and competitive product benchmarks to support commercial decision-making.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Experience developing and implementing pricing governance frameworks, pricing policies, commercial approval processes, or deal governance programs.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Strong financial modeling, profitability analysis, and business case development capabilities.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Experience presenting recommendations and influencing executive-level business decisions.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Experience participating in or leading customer-facing pricing and commercial discussions.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Exceptional analytical, strategic thinking, communication, negotiation, and presentation skills.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Proven ability to work effectively across Sales, Product Management, Finance, Marketing, Operations, and Executive Leadership organizations.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h3 class=\u0026quot;wnfdnth _1ibi0s33y _1ibi0s34u\u0026quot;\u0026gt;Preferred Qualifications\u0026lt;/h3\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdnte\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Experience supporting AI infrastructure, networking, connectivity, interconnect, semiconductor, data center, or cloud infrastructure products.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Deep understanding of semiconductor pricing strategies, product lifecycle management, cost structures, packaging and test economics, yield considerations, and gross margin optimization.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Experience evaluating price-performance positioning and competitive differentiation in highly technical markets.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Experience supporting hyperscalers, OEMs, ODMs, enterprise infrastructure customers, or strategic technology accounts.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Experience developing value-based pricing methodologies and commercial frameworks for differentiated technology products.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Experience building pricing organizations, pricing centers of excellence, or commercial excellence functions.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Experience developing pricing governance models within semiconductor, infrastructure technology, networking, or enterprise hardware businesses.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Experience supporting executive pricing councils, deal review boards, or commercial governance committees.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;MBA or advanced degree preferred.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Experience working within a high-growth public technology company is a plus.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot; data-pm-slice=\u0026quot;1 1 []\u0026quot;\u0026gt;Base salary range is $200,000 to $250,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4000201005,"name":"Business Operations","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4723517005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4449219005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Technology Product Marketing","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4723517005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":null,"title":"Director, Product Line Management - Custom Silicon ","company_name":"Astera Labs","first_published":"2026-08-14T14:54:49-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;About the Role\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is seeking an experienced Director, Product Line Management - Custom Silicon\u0026amp;nbsp;to lead strategic customer engagements for our growing Custom Solutions business. This is a senior individual contributor role, equivalent in scope to a Director-level position, with no direct people management responsibility.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This is not a traditional product management role focused on a single merchant product line. You will serve as the business and technical leader for custom silicon opportunities—partnering directly with hyperscalers, AI labs, and emerging AI infrastructure companies to understand their architectures, identify opportunities, define engagement and commercial models, and guide programs from concept through production.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;What You’ll Do\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Own product and business strategy for Astera Labs’ Custom Solutions portfolio.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Build trusted relationships with hyperscalers, AI infrastructure providers, AI labs, and other strategic customers.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Understand customer architectures and translate technical and business requirements into differentiated custom silicon solutions.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Define solution roadmaps, product strategies, and customer engagement models for custom silicon programs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead customer roadmap discussions, executive business reviews, and technical strategy sessions.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Partner with Architecture, ASIC Design, Firmware, Software, Validation, Product Applications, Sales, Marketing, and Operations to execute customer programs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop business cases, commercial frameworks, pricing strategies, and lifecycle plans for custom engagements.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive competitive analysis, market intelligence, and positioning across the custom silicon landscape.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Create customer-facing materials, including solution briefs, white papers, executive presentations, and technical messaging.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Identify and cultivate new opportunities that expand Astera Labs’ presence across hyperscale, AI, and cloud infrastructure customers.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Influence cross-functional execution from initial opportunity assessment through production ramp, without direct people-management responsibility.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;What Success Looks Like in the First Year\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Secure multiple custom silicon design wins.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Build a strong pipeline of qualified strategic customer opportunities.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Expand Astera Labs’ footprint with hyperscalers, AI companies, and emerging infrastructure providers.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Establish durable customer relationships that create opportunities for repeat business.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Leverage Astera Labs’ existing silicon IP and platform capabilities to win increasingly complex custom programs.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;12+ years of experience in semiconductor product management, product line management, technical marketing, applications engineering, business development, or a similar customer-facing technical leadership role.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience leading custom silicon or advanced semiconductor products from concept through production.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of semiconductor architectures and AI infrastructure, networking, compute, storage, or memory technologies.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience working directly with hyperscalers, AI companies, cloud service providers, or major system OEMs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Demonstrated success developing custom silicon opportunities and securing semiconductor design wins.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of competitive positioning, market analysis, product strategy, and commercial models.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Exceptional communication, executive presentation, and customer-engagement skills.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Demonstrated ability to influence technical and commercial stakeholders across functions without direct reporting authority.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience with custom ASICs, AI accelerators, networking silicon, storage silicon, memory silicon, SmartNICs, DPUs, XPUs, or other custom infrastructure silicon.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of chiplet architectures, HBM, advanced packaging, heterogeneous computing, and high-performance semiconductor design.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience developing customer-facing technical collateral and strategic messaging.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience developing commercial structures, pricing strategies, and business cases for semiconductor programs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;MBA or advanced engineering degree.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p8i6j01 paragraph\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p8i6j01 paragraph\u0026quot;\u0026gt;Salary range is $195,000 to $250,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives, and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4000702005,"name":"Product Applications","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4720386005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4447641005,"location":{"name":"Germany (Onsite)"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":null,"value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4720386005,"updated_at":"2026-09-24T18:41:01-04:00","requisition_id":"2700","title":"Distinguished ASIC Design Engineer","company_name":"Astera Labs","first_published":"2026-08-02T08:44:18-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;h1\u0026gt;\u0026lt;strong\u0026gt;Distinguished ASIC Design Engineer/ Senior Principal \u0026lt;/strong\u0026gt;\u0026lt;/h1\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Location:\u0026lt;/strong\u0026gt; Germany (on-site)\u0026lt;/p\u0026gt;\n\u0026lt;h2\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/h2\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is building purpose-built silicon for rack-scale AI infrastructure. As a Distinguished Engineer, you will be a senior technical leader driving ASIC design for next-generation Ethernet and Scale-Up (ESUN) connectivity products.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;You will set technical direction across the full ASIC design flow, spanning high-speed Ethernet, UALink, UCIe, and PCIe Gen 6/7. You will solve complex scale-up networking challenges, mentor senior engineers, and turn ambitious product goals into robust, manufacturable silicon.\u0026lt;/p\u0026gt;\n\u0026lt;h2\u0026gt;\u0026lt;strong\u0026gt;Technical Leadership \u0026amp;amp; Architecture\u0026lt;/strong\u0026gt;\u0026lt;/h2\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Define and drive ASIC architecture for Ethernet/ESUN connectivity products across UALink, UCIe, PCIe Gen 6/7, and Ethernet.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead architecture and microarchitecture for high-performance Ethernet controllers, MACs, NIC datapaths, packet processing pipelines, and AI interconnect fabrics.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Define scalable, low-latency, high-bandwidth data movement, scheduling, buffering, congestion management, QoS, reliability, and flow control.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Architect hardware acceleration for NIC functions, RDMA, DMA, virtualization, and protocol offloads.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead tradeoff analysis across performance, power, area, latency, scalability, resiliency, and programmability.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Serve as a technical authority across digital, networking, and system domains.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h2\u0026gt;\u0026lt;strong\u0026gt;ASIC Design \u0026amp;amp; Execution\u0026lt;/strong\u0026gt;\u0026lt;/h2\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Lead RTL design and microarchitecture development for Ethernet controllers, MACs, NIC datapaths, protocol engines, and AI networking subsystems.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Design packet processing architectures, DMA engines, queue management, scheduling, buffering, and memory subsystem interfaces.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop hardware mechanisms for RDMA, zero-copy data movement, congestion control, transport reliability, and protocol acceleration.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Design scalable architectures supporting virtualization, multi-tenant isolation, traffic management, and quality of service.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Partner with firmware and software teams to define hardware/software interfaces for initialization, management, telemetry, performance monitoring, and diagnostics.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive execution from architecture through RTL, integration, verification, tapeout, and post-silicon bring-up.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Partner cross-functionally to meet performance, timing, power, area, manufacturability, and reliability targets.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h2\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/h2\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;15+ years of ASIC/SoC design experience, with a track record of delivering complex, high-speed networking or connectivity silicon from architecture through production.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep expertise in RTL design and microarchitecture for high-performance networking and connectivity ASICs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Extensive experience designing Ethernet controllers, MACs, NIC architectures, packet processing engines, or network interface subsystems.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of RDMA architectures and transport protocols such as RoCE, InfiniBand concepts, or similar low-latency networking technologies.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience designing hardware for packet parsing, scheduling, buffering, DMA, queue management, flow control, congestion management, and transport acceleration.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of high-speed interconnects and protocols, including Ethernet, PCIe, and AI scale-up fabrics.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience across the complete ASIC development flow, including architecture, RTL design, integration, synthesis, timing closure, physical implementation, tapeout, and post-silicon validation.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Demonstrated technical leadership across multiple teams and product programs.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h2\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/h2\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Master’s or PhD in Electrical Engineering, Computer Engineering, or a related technical discipline.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Direct experience with UALink, UCIe, PCIe Gen 6/7, and/or advanced Ethernet architectures and protocols.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience designing Ethernet MACs, controllers, SmartNICs, DPUs, NICs, switch datapaths, or packet processing engines.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience developing Ethernet-based scale-up networking solutions for AI and HPC systems.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience leading architecture or design for multiple successful advanced-node ASIC tapeouts.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent communication, collaboration, and mentorship skills.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184256005,"name":"Design Engineering CCE2","child_ids":[],"parent_id":null}],"offices":[{"id":4065803005,"name":"Germany (Onsite)","location":"Germany","child_ids":[],"parent_id":4056755005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4664853005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4420966005,"location":{"name":"San Jose, CA"},"metadata":[{"id":12122734005,"name":"Country","value":"India","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Bangalore","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":"Compute Connectivity Engineering 1","value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Formal Verification","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4664853005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2309","title":"Distinguished Formal Verification","company_name":"Astera Labs","first_published":"2026-02-23T13:43:57-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;Astera Labs is seeking a \u0026lt;strong\u0026gt;Distinguished Engineer, Formal Verification\u0026lt;/strong\u0026gt; to join our world-class engineering team in San Jose, California. As a hyper-growth leader in AI infrastructure connectivity, we\u0026#39;re revolutionizing how data centers handle explosive AI workloads through cutting-edge PCIe Gen 6/7, CXL, Ethernet, UCIe, and UALink technologies. This is a rare opportunity to shape the formal verification strategy across our entire product portfolio while working on the most advanced connectivity solutions powering the AI revolution.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;In this highly strategic role, you\u0026#39;ll serve as Astera Labs\u0026#39; technical authority on formal verification, defining methodologies and best practices that ensure the highest quality standards across all our next-generation connectivity products. You\u0026#39;ll work at the intersection of innovation and reliability, leading efforts to catch critical corner-case bugs that traditional verification methods miss, while mentoring a global team of engineers and representing Astera Labs as a thought leader in the formal verification community. This position offers exceptional scope for impact—your work will directly enable the rack-scale AI infrastructure that\u0026#39;s transforming cloud computing and enterprise data centers worldwide.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Strategic Leadership \u0026amp;amp; Methodology Development\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Define and evolve formal verification strategy, methodologies, and best practices across all product lines for PCIe, CXL, Ethernet, UCIe, and UALink protocols\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Serve as technical authority on formal verification, providing expert guidance to engineering leadership on risk mitigation and design quality\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Represent Astera Labs in industry forums, standards bodies, and technical conferences as a thought leader in formal verification\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive cross-functional collaboration to influence technical direction across the organization\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Technical Execution \u0026amp;amp; Innovation\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Develop detailed formal verification test plans based on design specifications and collaborate with design teams to refine micro-architecture specifications\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Identify key logic components and critical micro-architectural properties essential for ensuring design correctness\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Implement formal verification models, abstractions, assertions, and utilize assertion-based model checking to detect corner-case bugs\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Apply complexity reduction techniques using industry-standard EDA tools to achieve proof convergence or sufficient depth\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop and maintain scripts to enhance FV productivity and streamline verification processes\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Team Development \u0026amp;amp; Cross-Functional Partnership\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Mentor Principal and Lead Engineers across global sites in advanced formal verification techniques\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Assist design teams with the implementation of assertions and formal verification testbenches for RTL at unit/block levels\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Participate in design reviews and collaborate with design teams to optimize design quality and performance, power, area (PPA) metrics based on formal analysis feedback\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Prepare and deliver customer meetings and executive presentations with minimal supervision\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;15+ years of experience in formal verification or 18+ years of experience in traditional design verification with significant formal verification specialization\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong proficiency in SystemVerilog/Verilog with deep understanding of hardware design verification\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Advanced scripting abilities with Python or Perl for automation and productivity enhancement\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven ability to manage and prioritize multiple high-impact tasks in a dynamic, fast-paced environment with minimal supervision\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong cross-functional collaboration skills with demonstrated ability to influence technical direction and drive consensus\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Entrepreneurial mindset with proactive, customer-focused attitude and ability to think and act quickly while maintaining high quality standards\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Master\u0026#39;s or PhD in Electrical Engineering, Computer Engineering, Computer Science, or Mathematics with focus on formal methods or verification\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience with formal verification tools such as Synopsys VCFormal and Cadence JasperGold\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with both bug hunting and static proof verification techniques\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with automating formal verification workflows within a CI/CD environment\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep knowledge of high-speed serial protocols: PCIe Gen 4/5/6/7, CXL, Ethernet (100G/400G/800G), UCIe, UALink\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Participation in industry standards bodies (PCI-SIG, CXL Consortium, IEEE, UCIe Consortium)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Patents or publications in formal verification or hardware verification methodologies\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Track record of recruiting, mentoring, and developing formal verification talent across distributed teams\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Salary range is $230,000 to $285,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184232005,"name":"Compute Connectivity Engineering 1","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4674947005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4425619005,"location":{"name":"Taipei, Taiwan"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":"Global Sales","value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Sales","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4674947005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2388","title":"Executive Sales Representative","company_name":"Astera Labs","first_published":"2026-03-19T06:50:42-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;Regional Sales Executives will work closely with Field Sales Engineers (FAEs) and the sales management team to develop and execute an account strategy to effectively engage with leading cloud service providers on Astera Labs’ portfolio of connectivity products.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Develop a customer specific sales plan that identifies revenue generating opportunities and outlines steps to effectively develop relationships within key influencers in R\u0026amp;amp;D, Procurement, Executive level GM/CTO\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive sales efforts by teaming up with FAEs engaging with customers to provide roadmap updates, technology training, product sampling, technical support and gather customer forecasts\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Be a strong voice for your customers to communicate their product roadmap feedback, customer support issues and to drive a timely response from Astera Labs HQ\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Establish regular communication with your customer’s procurement, ODM ecosystem and other industry partners to be able to accurately forecast your region’s quarterly revenue and annual demand forecast\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s degree, preferred electrical/computer engineering and MBA.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;5+ years’ experience selling complex SoC/silicon products to Cloud Services Providers, Server or Network OEMs\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Demonstrated ability to prepare and execute customer account plans to win complex silicon design wins that contribute significant revenue growth\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Established relationships with some of our key target customers including Cloud Service Providers, Server, Storage \u0026amp;amp; Networking OEMs\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent communication and project management skills\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiar and at least 3+ years working experience with Taiwan Data Center ODMs like Quanta, Wistron, Wiwynn, Foxconn, and Inventec\u0026#39;s supply chain management\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Your base salary will be determined based on your experience and the pay of employees in similar positions\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184285005,"name":"Global Sales","child_ids":[],"parent_id":null}],"offices":[{"id":4009035005,"name":"Taipei","location":"Taiwan","child_ids":[],"parent_id":4002874005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4664075005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4420608005,"location":{"name":"Israel"},"metadata":[{"id":12122734005,"name":"Country","value":"Israel","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Tel Aviv","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":"Compute Connectivity Engineering 2","value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Packaging Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4664075005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2305","title":"Expert IC Package Design Lead","company_name":"Astera Labs","first_published":"2026-02-22T03:09:38-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is establishing a strategic R\u0026amp;amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical \u0026#39;data bottlenecks\u0026#39; enabling the future of AI at scale. As we expand our presence in Israel, we\u0026#39;re seeking a visionary \u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Expert IC Package Design Lead\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;strong\u0026gt;\u0026amp;nbsp;\u0026lt;/strong\u0026gt;to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, leading the physical implementation strategy for chips that power the world\u0026#39;s largest AI clusters.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;As an \u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Expert IC Package Design Lead\u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;, you will be a core technical contributor in the development of advanced IC packaging solutions for high-performance connectivity silicon.\u0026amp;nbsp;\u0026lt;br\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;You will own package flow, architecture, design, and qualification from concept through production, working closely with silicon, signal integrity, power integrity, mechanical, manufacturing, and external OSAT partners.\u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;You will be responsible for defining package technologies that meet aggressive electrical, thermal, mechanical, and cost targets, enabling Astera Labs’ products to operate reliably in the world’s most demanding AI and cloud environments.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:160}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Own end-to-end IC package design, from early architecture and feasibility through detailed design, qualification, and high-volume manufacturing\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:160}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Define package architecture and technology selection (organic substrates, advanced laminate, interposers, multi-die/chiplet packaging, CoWoS - 2.5D/3D integration)\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:160}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Lead signal integrity (SI), power integrity (PI), and thermal considerations at the package level for high-speed, high-power devices\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:160}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Drive package layout, substrate routing, bump/ball maps, stack-ups, materials selection, and mechanical constraints\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:160}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Collaborate closely with silicon design, SerDes, system, SI/PI, and reliability teams to optimize overall product performance\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:160}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Interface with OSATs, substrate vendors, and manufacturing partners to ensure design-for-manufacturability (DFM), yield, and cost targets\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:160}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Lead package-related risk assessment, failure analysis, and corrective actions during bring-up and production ramp\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:160}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Support NPI, qualification, and product sustainment activities, including vendor audits and technical reviews\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:160}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;10+ years of hands-on IC BIG package design experience\u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt; for high-performance semiconductor products, with full ownership from concept through tape-out\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:160}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Expert proficiency in IC package design tools\u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt; (Cadence APD / SiP or equivalent) and experience designing complex packages (BGA, FCBGA, FCCSP)\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:160}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Strong package architecture \u0026amp;amp; integration expertise\u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;, including stack-ups, ball/bump maps, constraints, SMT integration, and package BOM ownership\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:160}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Deep understanding of signal, power, and thermal integrity\u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt; at the package level, with ability to drive design tradeoffs based on analysis\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:160}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Proven manufacturing and release experience\u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;, including DRC/LVS/DFM, OSAT engagement, and delivering production-ready package designs\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:160}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Experience with AI, networking, PCIe, CXL, or other high-speed data center interfaces\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:160}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Familiarity with package reliability standards and qualification (JEDEC, IPC, thermal cycling, HTOL, etc.)\u0026lt;/span\u0026gt;\u0026lt;span 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Type","value":null,"value_type":"single_select"}],"id":4720171005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2026-325","title":"Fabric Modeling and Analysis Engineer for Scale Up Fabric ","company_name":"Astera Labs","first_published":"2026-07-30T19:56:16-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-size: 14pt;\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 1\u0026quot;\u0026gt;Fabric Modeling and Analysis Engineer- Scale Up Fabric\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335559738\u0026amp;quot;:360,\u0026amp;quot;335559739\u0026amp;quot;:80}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot; data-ccp-parastyle-defn=\u0026quot;{\u0026amp;quot;ObjectId\u0026amp;quot;:\u0026amp;quot;eeed19a5-d5cb-52b4-b7a2-054cd7cfbffb|1\u0026amp;quot;,\u0026amp;quot;ClassId\u0026amp;quot;:1073872969,\u0026amp;quot;Properties\u0026amp;quot;:[201342446,\u0026amp;quot;1\u0026amp;quot;,201342447,\u0026amp;quot;5\u0026amp;quot;,201342448,\u0026amp;quot;1\u0026amp;quot;,201342449,\u0026amp;quot;1\u0026amp;quot;,469777841,\u0026amp;quot;Aptos\u0026amp;quot;,469777842,\u0026amp;quot;Arial\u0026amp;quot;,469777843,\u0026amp;quot;Aptos\u0026amp;quot;,469777844,\u0026amp;quot;Aptos\u0026amp;quot;,201341986,\u0026amp;quot;1\u0026amp;quot;,469769226,\u0026amp;quot;Aptos,Arial\u0026amp;quot;,268442635,\u0026amp;quot;24\u0026amp;quot;,469775450,\u0026amp;quot;First Paragraph\u0026amp;quot;,201340122,\u0026amp;quot;2\u0026amp;quot;,134234082,\u0026amp;quot;true\u0026amp;quot;,134233614,\u0026amp;quot;true\u0026amp;quot;,469778129,\u0026amp;quot;FirstParagraph\u0026amp;quot;,335572020,\u0026amp;quot;1\u0026amp;quot;,335559739,\u0026amp;quot;180\u0026amp;quot;,335559738,\u0026amp;quot;180\u0026amp;quot;,469775498,\u0026amp;quot;Body Text\u0026amp;quot;,469778324,\u0026amp;quot;Normal\u0026amp;quot;]}\u0026quot;\u0026gt;Role Overview\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:180,\u0026amp;quot;335559739\u0026amp;quot;:180}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Body Text\u0026quot;\u0026gt;Astera Labs is powering the connectivity behind rack-scale AI, and our Scorpio Scale-Up Fabric is central to how tomorrow’s GPU clusters scale. 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data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;10\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:0,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Strong communication skills with a track record of influencing architectural decisions and contributing to IP/patents\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot;\u0026gt;Salary range is $185,000 to $240,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:180,\u0026amp;quot;335559739\u0026amp;quot;:180}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184226005,"name":"CTO Office","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4674945005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_optional","internal_job_id":4425617005,"location":{"name":"Taipei, Taiwan"},"metadata":[{"id":12122734005,"name":"Country","value":"Taiwan","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Taipei","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Field Applications Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4674945005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2387","title":"Field Applications Engineer","company_name":"Astera Labs","first_published":"2026-03-19T06:51:00-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;As an Astera Labs Principal Field Applications Engineer, you will support the world’s leading cloud service providers, server and network OEMs by working with them to design solutions that use Astera Labs’ portfolio of connectivity products. In this role, you will need to identify and understand customer requirements, propose Astera Labs solutions that provide clear value to the customer and provide hands-on design-in support. You will drive innovation by listening to the customer requirements, working with our engineering teams to implement into the product roadmap and delivering the results back to the customer.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026amp;nbsp;Basic qualifications:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;BS in electrical engineering. Master’s degree in engineering is preferred.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Minimum of 8 years’ experience working with Cloud service providers and server OEM customers to design in complex SoC/silicon products for Server, Storage, and/or Networking applications.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Customer-oriented, Goal-driven, Self-motivated, be able to work independently and be able to travel frequently to customer sites\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Fluent in Mandarin and English\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Entrepreneurial, open-mind behavior and can-do attitude. Think and act with the customer in mind!\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required experience:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Hands-on, thorough knowledge of high-speed protocols like PCIe \u0026amp;amp; Ethernet\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Silicon/System bring-up and debug experience in customer systems.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with lab equipment including protocol analyzers and oscilloscopes.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;A strong background in high-speed board design techniques, and understanding of Data Center systems like Servers, JBOGs/JBODs, Networking switches/routers etc.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Intermediate level of proficiency in Python for automating system validation and link optimization.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Able to step through embedded firmware at the SerDes (SoC) or MCU level for debugging.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Firsthand experience with lab equipment including traffic generators, analyzers, and high-speed oscilloscopes.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Business travel to Asia and the North America region may be required as needed.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred experience:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong working knowledge of a high speed interface at a physical layer level, associated standards, and debug. Most recent experience with 12G NRZ signaling at a minimum, some experience with 25G NRZ/56G PAM4 preferred.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Development, support, and experience with PCIe ICs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience in embedded SW debug or development with firmware, drivers, and BIOS using PCIe technology.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4134751005,"name":"Field Applications","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4009035005,"name":"Taipei","location":"Taiwan","child_ids":[],"parent_id":4002874005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4726996005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4450968005,"location":{"name":"Bengaluru, Karnataka, India"},"metadata":[{"id":12122734005,"name":"Country","value":"India","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Bengaluru","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"System Validation","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4726996005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":null,"title":"Firmware Engineer Tech Lead","company_name":"Astera Labs","first_published":"2026-09-01T14:56:09-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Firmware Engineer Tech Lead\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Bangalore, India\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at\u0026amp;nbsp;\u0026lt;a href=\u0026quot;http://www.asteralabs.com/\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;The mission of this role is to architect and develop firmware and microcontroller subsystems for Astera Labs’ SoC and systems products. As a\u0026amp;nbsp;\u0026lt;strong\u0026gt;Firmware Engineer Tech Lead\u0026amp;nbsp;\u0026lt;/strong\u0026gt;you are responsible for implementing the major differentiating features of Astera Labs’ products. As such, firmware is considered equally important to the hardware, and the firmware team is often customer-facing accordingly to ensure the needs of the customer are fully comprehended.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong academic and technical background in electrical engineering. At a minimum, a Bachelor’s in EE or Computer Science is required, and a\u0026amp;nbsp;Master’s\u0026amp;nbsp;is preferred.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Minimum 5 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience developing firmware to\u0026amp;nbsp;execute in\u0026amp;nbsp;on-chip microcontrollers as well as C-language software development kits (SDKs) to execute on system management controllers (e.g. BMC).\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience working with logic designers to architect and verify HW-SW interfaces on complex SoCs.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer meetings in advance, and to work with minimal guidance and supervision.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Experience\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience working on PCIe-Express (Gen-3 and above) protocol, including working with analyzers and exercisers to debug protocol issues.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;High level of proficiency in C (preferred) or C++, including development of C-based SDKs.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;High level of proficiency in Python for automating pre-processors/post-processors and FW QC.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Working knowledge of software/firmware build environments,\u0026amp;nbsp;gcc/Make,\u0026amp;nbsp;Doxygen, and GitHub. \u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with SoC interfaces to common IP blocks such as PCIe Controllers, DDR Controllers, NVME Controllers, AMBA/AHB interfaces, on-chip memory interfaces, and other similar interfaces.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Experience\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience with PAM4 SerDes with working knowledge of Tx/Rx equalization, adaptation, CDR and SerDes link budgets.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience with PCIe devices in Server, Storage, and/or Networking equipment. \u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience developing embedded firmware for PCIe or Ethernet Switch products.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184368005,"name":"Firmware \u0026 Software SCE","child_ids":[],"parent_id":null}],"offices":[{"id":4049113005,"name":"Bengaluru","location":"India","child_ids":[],"parent_id":4052109005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4711413005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4443312005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":"Silicon Engineering SCE","value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Firmware Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4711413005,"updated_at":"2026-10-08T03:33:32-04:00","requisition_id":"2026-234","title":"Firmware Engineer Tech Lead","company_name":"Astera Labs","first_published":"2026-07-16T19:27:25-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;The mission of this role is to architect and develop firmware and microcontroller subsystems for Astera Labs’ SoC and systems products. As a\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Firmware Engineer Tech Lead \u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;you are responsible for implementing the major differentiating features of Astera Labs’ products. As such, firmware is considered equally important to the hardware, and the firmware team is often customer-facing accordingly to ensure the needs of the customer are fully comprehended.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Basic Qualifications\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Strong academic and technical background in electrical engineering. At a minimum, a Bachelor’s in EE or Computer Science is required, and a\u0026amp;nbsp;Master’s\u0026amp;nbsp;is preferred.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Minimum 5 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience developing firmware to\u0026amp;nbsp;execute in\u0026amp;nbsp;on-chip microcontrollers as well as C-language software development kits (SDKs) to execute on system management controllers (e.g. BMC).\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience working with logic designers to architect and verify HW-SW interfaces on complex SoCs.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer meetings in advance, and to work with minimal guidance and supervision.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;7\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Authorized to work in the US and start immediately.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Required Experience\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience working on PCIe-Express (Gen-3 and above) protocol, including working with analyzers and exercisers to debug protocol issues.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;High level of proficiency in C (preferred) or C++, including development of C-based SDKs.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;High level of proficiency in Python for automating pre-processors/post-processors and FW QC.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Working knowledge of software/firmware build environments,\u0026amp;nbsp;gcc/Make,\u0026amp;nbsp;Doxygen, and GitHub. \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Familiarity with SoC interfaces to common IP blocks such as PCIe Controllers, DDR Controllers, NVME Controllers, AMBA/AHB interfaces, on-chip memory interfaces, and other similar interfaces.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Preferred Experience\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience with PAM4 SerDes with working knowledge of Tx/Rx equalization, adaptation, CDR and SerDes link budgets.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Hands-on experience with PCIe devices in Server, Storage, and/or Networking equipment. \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience developing embedded firmware for PCIe or Ethernet Switch products.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Base salary range is $160,000 to $200,000 depending on experience, level, and business need. This role is eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184340005,"name":"Silicon Engineering SCE","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4671900005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4424159005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"Canada","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Vancouver","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"System Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4671900005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2356","title":"Firmware Engineer Tech Lead","company_name":"Astera Labs","first_published":"2026-03-11T15:06:29-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Job Description:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;The mission of this role is to architect and develop firmware and microcontroller subsystems for Astera Labs’ SoC and systems products. Firmware is responsible for implementing the major differentiating features of Astera Labs’ products. As such, firmware is considered equally important to the hardware, and the firmware team is often customer-facing accordingly to ensure the customer\u0026#39;s needs are fully comprehended.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic qualifications:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong academic and technical background in electrical engineering. At a minimum, a Bachelor’s in EE or Computer Science is required.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Minimum 5 years\u0026#39; experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience developing firmware to execute with on-chip microcontrollers and C-language software development kits (SDKs) to execute on system host CPUs and embedded microprocessors.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience working with logic designers to implement and test HW-SW interfaces on complex SoCs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Professional attitude with the ability to prioritize a dynamic list of multiple tasks, and to work with minimal guidance and supervision.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Can start immediately.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required experience:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;High level of proficiency in C (preferred) or C++, including development of C-based SDKs and firmware.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience developing boot-ROM and familiarity working in pre-Silicon environments (Simulation and emulation).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with secure boot flows (authentication, attestation \u0026amp;amp; standards like DICE, Caliptra) is an asset.\u0026amp;nbsp;\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficient in Python for scripting.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ability to design, implement, and write unit-level tests.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Working knowledge of software build environments, gcc/make.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with developer workflows, SCM (preferably git), code reviews, CI.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with SoC interfaces to various HW blocks, on-chip memory interfaces, and other similar interfaces that are common to chip design.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred experience:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Firmware development experience using RTOS.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Base salary range is $160,000 to $240,000 depending on experience, level, and business need. This role is eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025528005,"name":"Software Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4719507005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4447191005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"FP\u0026A","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4719507005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":null,"title":"FP\u0026A Business Unit Controller","company_name":"Astera Labs","first_published":"2026-07-29T11:48:57-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p class=\u0026quot;p8i6j01 paragraph\u0026quot;\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As a \u0026lt;strong\u0026gt;FP\u0026amp;amp;A Business Unit Controller\u0026lt;/strong\u0026gt; you will be primarily responsible for managing the business partnering relationships for the R\u0026amp;amp;D business units including their annual budgets and quarterly forecast updates and actual performance. The ideal candidate has a strong understanding of financial processes and complex transaction flows with a desire to grow and contribute in a high-growth, fast-paced environment. This role must communicate and organize tasks well to be effective.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Primary Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Establish strong partnership with leadership to help business owners manage their business effectively\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead all forecasting and analysis activities for the business owners including: annual plan, quarterly forecast updates and strategic planning\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop, analyze, and interpret financial data to evaluate operating results against budget and profitability metrics\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Provide analytical insights, assess risks, and guide senior leadership in strategic decision-making\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with Corporate Finance on various projects as needed\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Provide business analysis and support where needed\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;8+ years experience in FP\u0026amp;amp;A and business partnering, preferably in semiconductor or other manufacturing\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent financial modeling and business partnering skills\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong analytical and problem solving skills\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Great organization and communication skills, able to work effectively with the business to meet deadlines\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with basic GAAP concepts (revenue recognition, accruals, capitalization vs expense)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Advanced Excel skills\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiar with Oracle planning tools\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of financial transaction flows and financial reporting\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong feeling of ownership over business processes and desire to improve and make them more efficient\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s degree in Finance or related field\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Salary range is $160,000 to $200,000 depending on experience, level, and business need. This role is eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184221005,"name":"Business Finance","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4704546005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4440072005,"location":{"name":"Taipei, Taiwan"},"metadata":[{"id":12122734005,"name":"Country","value":"Taiwan","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Taipei","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":"Hardware Engineering","value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Hardware Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4704546005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2637","title":"Hardware Design Engineering, Director - OEM, Silicon Validation Platforms \u0026 Rack-Scale Design - Taiwan","company_name":"Astera Labs","first_published":"2026-06-09T20:48:42-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;ff02c8680261\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot; data-pm-slice=\u0026quot;1 3 []\u0026quot;\u0026gt;We are hiring a \u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Director of Hardware Design Engineering — OEM, Silicon Validation Platforms \u0026amp;amp; Rack-Scale Design\u0026lt;/strong\u0026gt; to establish and lead Astera Labs\u0026#39; Taiwan hardware engineering center. This role serves as the primary hardware engineering hub for OEM customer engagement across Asia, while simultaneously owning the design and development of Silicon Validation Platforms (SVB/EVB) and rack-scale products (AI chassis, switch trays, CEM cards).\u0026lt;/p\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;d22607f66bf4\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;This is a high-impact leadership role that combines three critical functions:\u0026lt;/p\u0026gt;\n\u0026lt;ol class=\u0026quot;ak-ol\u0026quot; data-local-id=\u0026quot;7ca0f63f-e051-4023-872d-d6049db1f210\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;orderedList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;e1ddeb3c-0a6e-4e8f-9723-430d417eb822\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;080bb45cc698\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;OEM Design Enablement \u0026amp;amp; Customer Support\u0026lt;/strong\u0026gt; — Serving as the front-line hardware engineering partner for OEM customers in Asia (hyperscale cloud, server/switch OEMs, cable/module manufacturers) who are integrating Astera Labs silicon into their own products\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;29100fa1-0983-4882-ad74-f227dde90495\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;2a59166bfb7c\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Silicon Validation Platform Design (SVB/EVB)\u0026lt;/strong\u0026gt; — Designing and delivering the evaluation boards and system validation platforms that enable silicon bring-up, characterization, customer evaluation, and reference design seeding\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;94764436-e242-480f-8bdf-9bfef05cb8d2\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;7b4ab558b56f\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Rack-Scale Product Design\u0026lt;/strong\u0026gt; — Designing AI chassis-class systems, switch trays, CEM cards, and system-level hardware that showcase Astera Labs\u0026#39; full connectivity portfolio\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ol\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;3acae3361cd2\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;You will build and lead a multidisciplinary hardware engineering team in Taiwan — spanning electrical/PCB design, mechanical engineering, validation, and customer applications engineering. You\u0026#39;ll serve as the senior Astera Labs hardware engineering leader in Asia, partnering with OEM customers, ODM partners, and contract manufacturers while maintaining tight alignment with the Santa Clara-based engineering organization.\u0026lt;/p\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;37f66edde872\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Reporting to the Senior Director of Hardware Design Engineering, you\u0026#39;ll operate with significant autonomy while ensuring strategic alignment on technology roadmap, design standards, and customer priorities.\u0026lt;/p\u0026gt;\n\u0026lt;hr data-local-id=\u0026quot;2cf3c1f4-1c6b-4873-ab5c-6f047a3ace40\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;rule\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;h2 data-local-id=\u0026quot;f8b4fbd3d9db\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;heading\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/h2\u0026gt;\n\u0026lt;h3 data-local-id=\u0026quot;ad8e6a98fb97\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;heading\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Taiwan Engineering Center Leadership\u0026lt;/h3\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;a6c77598-bfb7-4ce6-b008-482da4983db1\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;63f40f6f-e80e-4735-ab58-6b156beb5788\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;5271a0eaa7ac\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Establish, build, and lead Astera Labs\u0026#39; Taiwan hardware engineering center as the company\u0026#39;s primary Asia-based hub for OEM engagement, silicon platform design, and rack-scale product development\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;3db1a81e-5743-44b3-bf3b-b582b75d8ea4\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;735cc9d49f00\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Recruit, hire, and develop a high-caliber multidisciplinary engineering team in Taiwan, including:\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;54fcf572-1221-45c1-900f-dd0b5dc96bb8\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;157007ab-7f52-448e-bb39-b5c5e7e54025\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;c0d36c184d27\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Hardware/PCB design engineers\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;7db78ba1-cb61-4404-8188-dd7cf3470066\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;dd85030e20e5\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Mechanical engineers\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;4084dd4c-1a8b-4d2b-8f0a-c557f4872cfd\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;361dccc439cb\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Validation engineers\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;2d75b717-9381-4806-98cc-7f6bbbd73317\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;066c495f64ef\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Customer/applications hardware engineers\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;be9cf446-3861-4f13-baf9-42457321fc02\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;7015c235e713\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Lab engineers\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;8ca590cc-d702-4cb6-8364-91f715a39dcb\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;87d15dafac92\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Define organizational structure, hiring roadmap, and operating model for the Taiwan center — balancing local autonomy with global alignment\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;e5909a7a-789d-4818-9cf6-8cb1dc1bc63e\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;52a01423264e\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Establish lab infrastructure in Taiwan to support silicon platform bring-up, customer demonstrations, OEM design reviews, interoperability testing, and rack-scale system validation\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;ffe26a9f-6486-400d-bec1-ba961738eab6\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;c3ad6f282dac\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Drive engineering culture that emphasizes customer responsiveness, design excellence, and tight collaboration with Santa Clara headquarters\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;91575870-1e99-4bda-8ebb-2872c41c79a2\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;9c7e86247542\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Serve as the senior Astera Labs engineering leader in Asia — representing the company with customers, partners, and industry stakeholders in the region\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h3 data-local-id=\u0026quot;c26bcfe6d81c\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;heading\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;OEM Design Enablement \u0026amp;amp; Customer Engagement\u0026lt;/h3\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;718c41b6-7614-42e9-b204-b25a82bec32f\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;97cf4625-18ec-4964-bcfc-2e38a14b94da\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;c3e9a1602500\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Customer Design Support:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;c5965bb1-3887-4481-912b-142ab142fa99\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;eb5b2b4f-420b-4ded-a878-1224772502ee\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;061d0180c696\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Serve as the primary hardware engineering interface for OEM customers in Asia who are designing Astera Labs silicon (retimers, re-drivers, connectivity ASICs) into their own products\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;2a14329e-80a2-4391-8823-4f7b22b28f57\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;479c30e3d14a\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Provide expert-level design review support for customer hardware designs — reviewing schematics, PCB layouts, stackups, power delivery networks, thermal solutions, and signal integrity\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;c57bf697-ab83-47bb-a6b9-988382dcb71d\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;c726a89f3db2\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Deliver hands-on technical engagement during customer design cycles — from initial architecture consultation through prototype bring-up, debug, and production readiness\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;501b9fae-c6b0-4b0e-ab28-3106d96cd067\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;526913d4432e\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Support customer hardware debug and troubleshooting when integration challenges arise — coordinating across internal teams (silicon, firmware, SI, validation) to provide rapid root-cause analysis and corrective guidance\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;d12a2e04-582c-48e5-970f-d1f5b0cda881\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;7bcecc21dc7b\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Travel to customer sites across Asia (Taiwan, China, Japan, Korea) to provide on-site design review, bring-up support, and integration assistance for critical programs\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;6f773730-caef-4a8f-b8a8-8a1e3d22dd22\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;af5804cefc16\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Reference Design \u0026amp;amp; Design Collateral Development:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;1cf0d4ab-c3d9-43df-b7de-2a6faf3daffa\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;bbb8ae16-4e56-4605-b98e-f48f2d37446a\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;278c282e3985\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Develop and maintain production-quality reference designs for Astera Labs silicon — including reference schematics, recommended PCB layouts, stackup guidelines, power delivery reference circuits, and thermal design examples\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;deb62950-e4fa-477e-b6f3-322fe95a8573\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;a515242d6e22\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Create comprehensive hardware design guides, integration manuals, application notes, and best-practice documentation that enable OEM customers to achieve first-pass success\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;975caa92-842f-4d4d-83e4-5ebdda14c033\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;7f84091252dd\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Develop design review checklists and self-assessment tools for OEM customers, supplemented by Astera Labs expert review at critical milestones\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;e9b98479-4821-4a82-a375-91d9051f84fd\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;d951ec49b85a\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Ensure reference designs and collateral evolve with each silicon generation and incorporate lessons learned from customer engagements\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;c4ae28a4-a4b8-4bc3-aebe-752d08f16093\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;8ecbf5e4c579\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;OEM Relationship Management:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;0fcc0e91-2162-4d1a-876c-2ff175576d61\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;d6b4d043-bc38-4bd2-bb88-2c3e5835a5d5\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;23e5bffce0ee\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Build deep, trust-based technical relationships with hardware engineering teams at key OEM customers — becoming their preferred technical partner for Astera Labs silicon integration\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;45c2b2c2-354a-4983-b6df-17cfdbc99e85\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;28a81e31f268\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Partner with Sales, FAE, and Product Management teams to identify high-value customer engagements and prioritize hardware engineering support resources\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;f7df217e-7aaa-4e69-9d7b-b532bdce84fd\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;e7809096af56\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Participate in customer roadmap discussions, providing hardware engineering perspective on future silicon requirements, package options, and platform integration considerations\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;dd09035b-a51d-4cf3-854a-1ca5e522e95a\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;af51b47d16e1\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Capture common customer design challenges, failure modes, and feature requests — feeding these back into reference designs, design guides, evaluation platforms, and silicon requirements\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;28d3f0a5-34d4-420f-a04f-82ec204fdea5\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;4ec3dc43f06f\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Support joint development programs with strategic OEM partners — including co-designed products, custom form factors, and platform-specific optimizations\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h3 data-local-id=\u0026quot;cad69294add4\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;heading\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Silicon Validation Platform Design (SVB/EVB)\u0026lt;/h3\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;33dd6d42-f557-4895-a5c1-7cf1512a18b9\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;3768ce85-3e93-440e-9bb2-33d34a9c894a\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;a433c65aaae4\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Platform Architecture \u0026amp;amp; Design:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;8804b61c-4d58-454b-954b-68cb4de62928\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;84cea6ff-901f-42ab-a954-fa4202a5b5d7\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;07d0490abfec\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Own the architecture, design, and delivery of Silicon Validation Boards (SVB) and Evaluation Boards (EVB) for all Astera Labs silicon products — retimers, re-drivers, PCIe/CXL switches, and connectivity ASICs\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;0c39ae20-123e-4615-941b-fa6c2dfc339d\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;65e13c82c06e\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Design complex multi-layer PCBs optimized for silicon bring-up, characterization, and performance demonstration — including high-speed channel routing, configurable topology options, comprehensive power delivery, and debug/instrumentation access\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;1da73208-d406-4709-a50c-0c871da4cb19\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;9c4da9d5a9a8\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Ensure evaluation platforms provide optimal silicon exercising capability — enabling full characterization of all silicon features, performance modes, and operational corners\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;41795b04-4159-48fd-9703-b6e5c5b0eb2f\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;db3098868b0e\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Design platforms that serve dual purposes: internal silicon validation and external customer evaluation/demonstration\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;e6176846-e2cf-4606-83a4-016fbe5c46e2\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;faa1712761d5\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Create modular, scalable platform architectures that can be efficiently adapted across silicon generations with minimal redesign\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;f75941d1-b83f-46ce-9477-8426621919c7\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;9969390d0fb4\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Silicon Bring-Up \u0026amp;amp; Characterization Support:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;3244112e-64d4-4d5f-942c-f110e14d043f\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;8ab230d2-7ff1-4500-9e61-c98596fdf50b\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;4d070894a9fe\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Partner with silicon design and validation teams to ensure SVB/EVB designs support all required bring-up sequences, test modes, and characterization scenarios\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;09cc201d-b3d0-43f3-ab41-655246aba7b8\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;ddd77e603d51\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Support initial silicon bring-up activities on new platforms — providing hardware debug expertise and rapid board-level modifications as needed\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;dc8ce785-b01a-4a19-9e12-28d63dac36e0\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;1005928ba7c0\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Ensure platform designs enable comprehensive performance characterization — including high-speed link testing, power measurement, thermal characterization, and margin analysis\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;cf1d0612-4db7-42a5-bc3e-e2f3ae1b9c4d\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;329d60bfcc58\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Design instrumentation access (probe points, headers, measurement interfaces) that enables efficient silicon debug without compromising signal integrity\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;1280c68b-b2fc-4682-9ff9-70954f64cca2\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;55c17d2ac2bf\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Customer Evaluation Enablement:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;febebc0a-c300-44c2-a8de-4aacf56d83bf\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;c8e8cddd-8ad5-4556-8cf5-9a10c1d59862\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;57885f27e838\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Design evaluation platforms that provide customers a compelling, easy-to-use experience for evaluating Astera Labs silicon in their target applications\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;393a0cd8-3876-4061-93b7-d3682a5d01dc\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;58488e917af6\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Include customer-relevant interfaces, connectors, and configurations that match real deployment scenarios (OSFP, QSFP-DD, PCIe/CXL slots, network interfaces)\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;e83d6f68-27f3-4426-8ca8-42b50236d0f2\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;6f9e9f26a4ec\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Develop evaluation platform documentation including user guides, quick-start instructions, test procedures, and application examples\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;4223601c-bf97-4160-962c-eec7d73de6d1\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;2ac3399378bb\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Support customer evaluation activities — providing technical guidance, interpreting results, and facilitating customer design-in decisions\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h3 data-local-id=\u0026quot;6725b4a91265\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;heading\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Rack-Scale Product Design\u0026lt;/h3\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;5b9e8207-5a2e-4154-b780-b37c1df5574a\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;266a3a97-72a1-4dec-9505-c0e5fc8688ad\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;eafb43f6588f\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Chassis \u0026amp;amp; System-Level Design:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;bac22b94-0d18-483a-8ae4-b29ae4ae68f3\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;fbcfdba4-f3ed-4991-a660-6b3a1568a6c4\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;47ffce023244\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Lead the hardware design of rack-scale products including AI chassis-class systems, switch trays, CEM cards, and integrated connectivity platforms\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;c47aced7-42bc-4b3f-bf6d-4ccef6262c63\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;cba64f99d9a5\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Own system-level architecture decisions — including backplane/midplane topology, slot configurations, power distribution architecture, cooling strategy, and management interfaces\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;c75a5745-e5fa-4635-9087-707e4a934eaf\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;8bc9139dd133\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Design high-density backplane/midplane PCBs with high-speed interconnect routing supporting 112G/224G PAM4 signaling\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;85c22e44-dc84-4d12-8143-fa08f4c7af4b\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;b22a3e6df915\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Drive power distribution design for rack-scale systems — including AC/DC conversion, point-of-load regulation, power sequencing, hot-swap protection, and power budgeting\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;c453c206-0b4e-43f5-8cfc-df365ec93691\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;c93faefc6c4b\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Design BMC/management subsystems for chassis products — including platform monitoring, thermal management, fault detection, and remote management interfaces\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;860e4ff4-2794-4616-853f-18db49ba88ca\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;787b23017b46\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Mechanical \u0026amp;amp; Thermal Design:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;018d8378-425b-4fde-a91e-95ccfbd0b162\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;8128fcb8-9853-4f6a-807e-fd3a2b5fb555\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;3f4bd8ff0018\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Direct mechanical engineering for rack-scale products — chassis sheet metal, card cages, cable management, hot-swap mechanisms, rack mounting, and serviceability\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;100ff8ab-1117-43ac-ba5e-95cae8929a52\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;86b707c1355b\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Drive thermal/airflow architecture for chassis systems — including fan tray design, airflow optimization, thermal sensor placement, and thermal throttling strategies\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;b3ea6e56-45a0-467e-9b6c-d11e86849320\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;b4cb1693265d\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Evaluate and integrate liquid cooling solutions for high-power-density rack-scale AI infrastructure applications\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;7df7cd00-bf8b-4629-bb75-519e85cd5f67\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;4c94b56bfffd\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Ensure mechanical designs comply with relevant rack standards (OCP, Open19, EIA-310) and customer-specific mechanical requirements\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;2b9210bc-7043-4982-abdf-99f1268ca00a\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;364968e5c460\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;ODM Collaboration:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;295b04f0-d527-4a1f-a12f-79aa9bf68f12\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;dec5eae0-d6e5-4aae-9b37-e016cfa48521\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;4688d20c114b\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Partner with ODM manufacturers in Asia for chassis and system-level products — providing design specifications, reviewing ODM designs, and driving joint development\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;70766c06-8a93-4e3b-8df2-cfe2bf5a544a\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;ad0eebc29c2b\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Manage technical ODM relationships for rack-scale products, navigating the differences from traditional CM engagement models\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;dcc61394-3f85-4873-8312-c41fed3c9ac2\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;e9d67b9ad363\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Conduct design reviews of ODM-proposed solutions, ensuring alignment with Astera Labs\u0026#39; performance, quality, and reliability requirements\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;72d57272-0f5a-4d52-8b56-ec328193b974\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;e6aee6462585\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Leverage proximity in Taiwan to maintain close, high-cadence collaboration with ODM engineering teams\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h3 data-local-id=\u0026quot;5451fb236dbd\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;heading\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Hardware Validation (Platform \u0026amp;amp; Rack-Scale)\u0026lt;/h3\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;f9fc19ed-880c-446b-af18-9ac28eca7434\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;00ecf54c-5bfd-42b3-8a5c-d96ba4e59937\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;994b6f549711\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Define and execute validation strategies for silicon evaluation platforms and rack-scale products — ensuring comprehensive coverage across electrical performance, signal integrity, power delivery, thermal behavior, mechanical integrity, and environmental reliability\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;fba82da8-7dbf-4695-9b70-d55fba9eeebc\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;b6cfc153b57f\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Establish validation methodologies specific to evaluation platforms — including silicon interface verification, channel characterization correlation, power delivery accuracy, and instrumentation validation\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;9c2478ae-d687-4057-b07c-ac29a5e437c6\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;83febba7f8ec\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Drive rack-scale product validation including system-level thermal testing, power stress testing, mechanical shock/vibration, EMC/EMI compliance, and safety certification\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;4bdcecf4-9a53-4b5f-af8d-f08c6164f526\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;e78dbc13e460\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Support interoperability testing between rack-scale products and the broader ecosystem of host platforms, NICs, switches, and cables\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;217a5321-07a3-4b34-98e2-506a416ea113\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;bb2e15d75e79\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Build validation infrastructure in Taiwan that enables local execution of the majority of validation activities without dependency on Santa Clara labs\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h3 data-local-id=\u0026quot;b44adb34410c\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;heading\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Cross-Functional Collaboration\u0026lt;/h3\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;d9c64a77-12f7-43ce-aac7-fa5ef1661c72\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;6026d811-bc7e-4f86-b5f5-10d4fe395086\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;dd9544ca8a62\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;With Santa Clara HQ:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;2dad45ec-4606-4bdc-908c-d530da2b2903\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;bad2f3c7-ef2e-4905-af7b-20d5932a60d8\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;79ef7cdd8155\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Maintain tight alignment with the Senior Director of Hardware Design Engineering and peer engineering leaders on technology roadmap, design standards, and resource priorities\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;5271a1ef-c653-4f93-83e0-27439e618de7\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;3ad706ac98d7\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Collaborate with AEC/SCM hardware design teams to ensure consistency in design methodologies, component strategies, and validation approaches\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;3c3ee788-df92-4738-a986-3225a1723ccc\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;a2c3a50f02c6\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Partner with Signal Integrity engineering on channel modeling, simulation-to-measurement correlation, and design rule development\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;d11e3fcd-869e-42ee-80fc-e7105467031f\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;f9f191d43a8c\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Coordinate with Firmware Engineering on hardware-firmware co-design for evaluation platforms and rack-scale products (power sequencing, BMC, CMIS, diagnostics)\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;8befb8fb-71c8-43c0-aff2-b88e773963a2\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;27a7dae6446f\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;With Manufacturing \u0026amp;amp; NPI:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;ba50521a-b1f3-47a0-8e33-8e21f5228740\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;82fc30ae-b312-4aff-8471-d404434211ca\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;4cf848dfa20c\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Partner with Manufacturing Engineering and NPI teams to ensure silicon platforms and rack-scale products are manufacturable, testable, and scalable\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;0a2a104e-5681-494a-91a9-f3031036e8f4\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;3f02dd20e723\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Leverage Taiwan proximity to CM/ODM sites to drive efficient DFM/DFA reviews, pilot builds, and production ramp support\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;a305b06d-d278-484d-9cb9-d8fc8bcf0025\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;26e20ced7d25\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Participate in make-vs-buy decisions for rack-scale products — evaluating internal design vs. ODM engagement for each product\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;d1874418-1fbf-4b2b-aa09-ceef4bb41ce9\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;13ce3559184a\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;With Product Management \u0026amp;amp; Sales:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;a975b224-07ff-4c00-852f-e4f770880da3\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;70036541-7b01-447f-af96-fc815817f8e2\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;0381f07d93b5\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Align silicon platform and rack-scale product development priorities with product management roadmap and customer demand\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;2de0999d-ec1d-4faa-b2e4-97a69aa33607\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;4982bab8b03d\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Partner with Sales and FAE teams to prioritize OEM engagements and allocate customer hardware engineering resources\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;cb23b3d8-a025-4d8e-9467-41cbc61eed36\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;1db267637704\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Provide technical input for customer proposals, RFQ responses, and competitive evaluations\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;dabcd552-94be-4632-af2b-df7dbdcd61d8\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;cb12685011e8\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Represent hardware engineering in customer-facing executive discussions and technical reviews\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h3 data-local-id=\u0026quot;9e2f7bd203e3\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;heading\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Lab Infrastructure (Taiwan)\u0026lt;/h3\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;ef9dff34-a88a-4e77-aa2c-786d451ecdb9\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;1308a447-a178-427f-9397-7a2dc0978ad5\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;369983d2db19\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Define and build the Taiwan lab environment to support:\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;e3cbc165-a0ff-47ef-b174-d7845e77a7e2\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;580c0f4d-6a8a-4343-9450-3fa57043180d\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;516f9fa4cccd\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Silicon evaluation platform bring-up and characterization (high-speed oscilloscopes, BER testers, VNAs, power analyzers)\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;897f58ea-c74e-4316-ab54-4163473b40f9\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;d5254486a40e\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Rack-scale system test (power load testing, thermal chambers, airflow measurement, EMC pre-compliance)\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;0d9a1512-6159-4e1d-92ea-a58e58fa4707\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;ce2355610659\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Customer demonstration and interoperability testing\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;25cf6918-76a7-46b5-9c93-d27154c93fc4\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;b9acd25c6551\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;OEM customer joint debug sessions\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;e6dfdc01-1f03-4808-8014-13046959164c\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;fcbfe0d36375\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Drive capital equipment planning and procurement for the Taiwan lab\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;7c830c6f-71a6-4e46-9418-7a7c7761d5b9\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;f98016db7b2e\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Ensure lab capabilities enable the Taiwan team to operate with high autonomy while maintaining measurement correlation with Santa Clara labs\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;hr data-local-id=\u0026quot;33a2ab3d-8789-48f3-accc-3b0039322c22\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;rule\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;h2 data-local-id=\u0026quot;9461f8398413\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;heading\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Basic Qualifications\u0026lt;/h2\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;fad133a0-6410-44c8-b0ed-49ef2616ed8f\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;83a43b9e-f587-4ff1-ac9c-e5a728bea148\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;af63bee29cfb\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, Computer Engineering, or related technical discipline\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;54ce3c0a-0219-49e0-b9b9-55cc755ac279\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;6190d03e4571\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;15+ years of progressive experience in hardware design engineering for high-speed interconnect, server/switch systems, silicon evaluation platforms, or data center infrastructure products\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;ccddaf4f-d3d6-4bed-8202-a23c44468e26\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;9409796783db\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;5+ years in engineering management/leadership roles, including building and leading multi-team hardware engineering organizations\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;25625477-b34d-4a69-b664-e488b849ae74\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;588ecdecfdb5\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Proven track record designing complex high-speed PCBs at 56G/112G PAM4 data rates or above — including evaluation boards, system boards, or backplane/midplane designs\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;41a87ca6-7676-473f-ae63-e7dae646f66a\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;aa4a0188a00b\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Demonstrated experience engaging with OEM customers on hardware design enablement, design reviews, and technical support for silicon/ASIC integration\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;3676e426-1d34-4337-89b9-72cd6a9edc94\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;3c8f6c805035\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Strong background in silicon evaluation platform (EVB/SVB) design — enabling bring-up, characterization, and customer evaluation of complex semiconductor products\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;1f96e49d-3141-42c7-a4f4-70293d17442f\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;d523a87a94db\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Experience with rack-scale or chassis-class system design — including power distribution, thermal management, backplane design, and mechanical packaging\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;30814864-3963-4a9a-a3d5-0b549238ab00\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;2b6f2c23b88d\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Deep understanding of signal integrity, power delivery network design, thermal management, and high-speed PCB design best practices\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;ce0d674c-506b-4deb-b33b-21db543e7941\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;baec9c0850e3\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Proven ability to build engineering teams and establish new engineering site operations\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;1e309c9a-4ec2-4ed3-94a4-d44267f60eb8\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;30f9d180ed88\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Experience working with ODM partners and contract manufacturers in Asia\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;d707fdbc-c2b3-477c-89cb-a5b07188640f\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;2dea080ba85c\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Excellent communication skills in both English and Mandarin (or other relevant Asian languages)\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;37385672-adfb-41f0-9480-30c83a6df561\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;0564aa614a1c\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Based in Taiwan (Hsinchu or Taipei area) with willingness to travel across Asia (China, Japan, Korea) and to US headquarters regularly\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h2 data-local-id=\u0026quot;906106c06cd2\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;heading\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Preferred Qualifications\u0026lt;/h2\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;c33716e5-499b-4520-ba6a-e749aff071b4\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;8ba13896-f1b6-404f-acd8-fe8d90c8a988\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;66ce909cf234\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Master\u0026#39;s or Ph.D. in Electrical Engineering with emphasis on high-speed digital design, signal integrity, or power electronics\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;f115fc0b-143e-4cb0-be43-f90f98363dd4\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;427486dcfd88\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Direct experience designing evaluation platforms for retimer, re-driver, PCIe switch, CXL switch, or high-speed SerDes silicon\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;93426b84-4a42-4017-94c6-5aaad5f81ec3\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;763c03972f80\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Experience developing rack-scale products for hyperscale cloud customers (AWS, Google, Microsoft, Meta) or AI infrastructure applications\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;4c966762-ed62-49a3-b89f-4692011e6a73\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;6a2ac557f236\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Track record at a leading semiconductor company, system OEM, or ODM in a customer-facing hardware engineering leadership role\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;b0d13096-130f-4033-a935-0b1f359f0c25\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;89ca7490ce61\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Experience with 224G/lane interconnect technology and next-generation substrate/connector architectures\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;04d60505-5a40-4a38-ac77-d076da9bd0c4\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;c688192bc356\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Deep familiarity with relevant standards: IEEE 802.3ck/dj, OIF CEI-112G/224G, PCIe 5.0/6.0, CXL 2.0/3.0, SFF-TA (OSFP, QSFP-DD), CMIS, OCP specifications\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;7b518ba4-cca6-4f73-a85a-b32b8364ce30\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;017b600b7fb7\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Experience with server/switch platform design including BMC subsystems, IPMI/Redfish management interfaces, and platform initialization\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;8d5e9a6f-aea6-47ff-b2b9-fba05b2a011d\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;bb35a3a62034\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Background in establishing and scaling engineering operations in Taiwan for US-headquartered semiconductor or systems companies\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;55285902-cebc-42d2-97c8-ba2d2f7725cd\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;ec59b97e4575\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Experience with EDA tools (Cadence Allegro/OrCAD, Ansys HFSS/SIwave, Keysight ADS, SolidWorks/Creo)\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;a01c2e68-d389-4617-8dfd-b453fd527822\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;de570c604676\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Mandarin Chinese fluency (native or near-native) for customer and partner engagement in Greater China\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;32d80a92-fc55-412a-bbb2-25c61fbb27a7\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;49f1e1b57a85\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Japanese or Korean language proficiency for OEM engagement in Japan/Korea\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;1b9e93bd-326e-429b-be44-449a2f4b1e94\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;5ba455ea2f22\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Relationships with key OEM hardware engineering organizations in Asia\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025526005,"name":"Hardware Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4009035005,"name":"Taipei","location":"Taiwan","child_ids":[],"parent_id":4002874005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4702153005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4438888005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":"Hardware Engineering","value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Hardware Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4702153005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2612","title":"Hardware Design Engineering, Senior Director - Signal Connectivity Rack-Scale Platforms","company_name":"Astera Labs","first_published":"2026-06-03T19:01:53-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;div\u0026gt;\n\u0026lt;div id=\u0026quot;content\u0026quot; class=\u0026quot;highlighter-context page view\u0026quot; data-inline-comments-target=\u0026quot;true\u0026quot; data-testid=\u0026quot;page-content-only\u0026quot;\u0026gt;\n\u0026lt;div class=\u0026quot;_1bsb1osq _19pkidpf _2hwx1wug _otyridpf _18u01wug\u0026quot;\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;div id=\u0026quot;main-content\u0026quot; class=\u0026quot;wiki-content css-ki3ac2 e5xcnr80\u0026quot; data-testid=\u0026quot;pageContentRendererTestId\u0026quot; data-test-appearance=\u0026quot;full-width\u0026quot;\u0026gt;\n\u0026lt;div class=\u0026quot;renderer-overrides\u0026quot;\u0026gt;\n\u0026lt;div class=\u0026quot;ak-renderer-wrapper is-full-width cc-tmc94p\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;h2 data-local-id=\u0026quot;bfa8d552ad34\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;heading\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot; data-pm-slice=\u0026quot;1 3 []\u0026quot;\u0026gt;About Astera Labs\u0026lt;/h2\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;676710b25447\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Astera Labs is the connectivity backbone of rack-scale AI infrastructure. Our Active Electrical Cables (AEC), Smart Cable Modules (SCM), Silicon Evaluation Platforms, and rack-scale products deliver purpose-built, high-speed connectivity for the world\u0026#39;s most demanding AI clusters. As our product portfolio expands in complexity, performance, and volume — and as OEM customers increasingly adopt Astera Labs silicon into their own designs — we need a senior engineering leader to build and scale the hardware design engineering organization that creates industry-defining products and enables our customers\u0026#39; success.\u0026lt;/p\u0026gt;\n\u0026lt;hr data-local-id=\u0026quot;40284d0d-d8b7-4192-a4b7-1cc50a2b18d1\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;rule\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;h2 data-local-id=\u0026quot;80dfcceb4234\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;heading\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;About the Role\u0026lt;/h2\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;fead27032118\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;We are hiring a \u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Senior Director, Hardware Design Engineering\u0026lt;/strong\u0026gt; to lead and scale Astera Labs\u0026#39; hardware design engineering organization across Active Electrical Cables (AEC), Smart Cable Modules (SCM), Silicon Evaluation Platforms (SVB/EVB), rack-scale products, and OEM/customer design enablement. This is a senior leadership role with full ownership of the hardware design function — encompassing electrical/PCB design, mechanical engineering, hardware validation, lab infrastructure, and customer hardware engineering support.\u0026lt;/p\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;6ce9a4d52296\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;You will build and lead a world-class, multidisciplinary engineering organization that takes products from concept through design, validation, qualification, and production release — while simultaneously enabling OEM customers and design partners to successfully integrate Astera Labs silicon into their own products. Your teams will own the complete hardware realization of Astera Labs\u0026#39; connectivity products and serve as the technical bridge between Astera Labs\u0026#39; silicon capabilities and the broader ecosystem of customers building next-generation AI infrastructure.\u0026lt;/p\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;e6b466be21ad\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;You will be a key member of the engineering leadership team, driving technology roadmaps, making critical technical and business trade-off decisions, and partnering closely with silicon, firmware, signal integrity, NPI, manufacturing, quality, product management, sales, and customer-facing teams. You\u0026#39;ll also be responsible for attracting, developing, and retaining top engineering talent as Astera Labs scales through hyper-growth.\u0026lt;/p\u0026gt;\n\u0026lt;hr data-local-id=\u0026quot;b52ebcd4-60ad-4d9a-8fab-40208f7518f2\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;rule\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;h2 data-local-id=\u0026quot;8f6c1c30c08a\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;heading\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/h2\u0026gt;\n\u0026lt;h3 data-local-id=\u0026quot;fcf5efc46e06\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;heading\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Engineering Leadership \u0026amp;amp; Organization Building\u0026lt;/h3\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;610d0e7d-3d73-4f6a-a0fe-08ffc7035c06\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;2b942223-e146-47f8-9530-5e44646a4242\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;472546e62b8e\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Lead and scale Astera Labs\u0026#39; hardware design engineering organization, encompassing:\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;8c4a0273-1471-49d0-885b-87ed0eabd75a\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;20cfbe8f-ffec-42a5-960c-68a3d2a2f679\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;f76b8977f7f7\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Electrical/PCB Hardware Design Engineering\u0026lt;/strong\u0026gt; — schematic capture, high-speed PCB/flex/substrate layout, power delivery, component engineering for cable modules through rack-scale systems\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;346dc4f6-a8ea-4827-bdb4-f5d5b1d36440\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;9389fe1bc5c4\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Mechanical Engineering\u0026lt;/strong\u0026gt; — connector design, housing/enclosure design, thermal management, cable strain relief, chassis/sheet metal, form factor compliance, tolerance analysis\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;3237f35c-fc6c-490b-b4ba-f354508cb0db\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;6ed755de95a6\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Hardware Validation Engineering\u0026lt;/strong\u0026gt; — product-level electrical, mechanical, environmental, and reliability qualification and validation across all product lines\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;fca4fee2-d95f-4908-a593-a9570df72be3\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;5072993b0c2c\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Lab Engineering \u0026amp;amp; Infrastructure\u0026lt;/strong\u0026gt; — test lab buildout, capital equipment strategy, measurement capability, and lab operations\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;51257a36-fa39-49fd-a011-092dc1460792\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;e53f6480853a\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Customer Hardware Engineering \u0026amp;amp; OEM Enablement\u0026lt;/strong\u0026gt; — reference design support, design reviews, integration guidance, and hands-on technical engagement with OEM customers adopting Astera Labs silicon\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;e3e33ebd-54ec-4ee0-b860-c0c6013cb55c\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;19dcdd8848b4\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Build, mentor, and lead a team of engineering managers and senior individual contributors across all hardware design disciplines\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;6a71f1ae-cd65-487c-85df-be19a1419b3f\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;4a44c7c4056d\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Define organizational structure, hiring plans, career development frameworks, and technical competency models as the team scales\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;6fda34ad-6e55-49f0-88b0-e13c1128ce5b\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;d1f4147cc922\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Foster a culture of engineering excellence, rigorous design practices, cross-functional collaboration, and customer-centric technical support\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;b6892686-81ed-432c-8890-1ee4bdff1471\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;e748cc1fc6da\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Represent the hardware design engineering function in executive reviews, board updates, and strategic planning sessions\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h3 data-local-id=\u0026quot;78b459607ce5\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;heading\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Technology Roadmap \u0026amp;amp; Strategic Planning\u0026lt;/h3\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;2af95cfa-4444-4f23-b67f-05a3c045dba3\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;2000041d-bd70-4874-8c83-b1078bee5453\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;8b858582f07d\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Define and manage the hardware technology roadmap for AEC, SCM, Silicon Evaluation Platforms, and rack-scale products — aligned with silicon roadmaps, customer requirements, market trends, and competitive dynamics\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;8110848b-c0ea-439c-beb3-90f2aea3fc01\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;b6e73156acce\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Drive technology strategy decisions across interconnect architectures, PCB/substrate technologies, connector platforms, cable constructions, thermal solutions, chassis architectures, and form factors\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;bc3f13ef-a181-48d3-a7fc-e8420f75613a\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;472b0ca2f573\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Identify and invest in next-generation hardware technologies (e.g., 224G/lane substrates, advanced thermal materials, novel connector interfaces, miniaturized form factors, liquid cooling integration) that maintain Astera Labs\u0026#39; competitive differentiation\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;9e9fca17-e21e-4b09-ac05-5bc1c9a61f86\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;6428cec35fd9\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Partner with Product Management and Business Development to translate customer needs, market requirements, and standards evolution into engineering development priorities\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;3524ea09-6576-409e-bd36-775114255acc\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;7648b102a9e4\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Align hardware design roadmap with silicon tape-out schedules, firmware development timelines, manufacturing readiness milestones, and OEM customer design-in timelines\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;91ff5fe9-bfc9-4545-a507-f1da9701ba39\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;abf807623b22\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Incorporate customer and OEM feedback into technology roadmap decisions — ensuring reference designs, evaluation platforms, and design collateral evolve to meet ecosystem needs\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h3 data-local-id=\u0026quot;e58d44dc853d\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;heading\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Product Development \u0026amp;amp; Execution\u0026lt;/h3\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;1c56c4d6-7cb6-41b9-9ccc-17723b3edb5d\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;cfbac81f-27d8-48f6-99ef-3a2e6fc821a8\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;707ed9c94034\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Drive R\u0026amp;amp;D and new product development for the full range of hardware products — from cable-scale modules to rack-scale systems:\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;c8608e42-b04e-478f-814d-03d7d28a5f61\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;31d1b7b6-1530-4f62-9c15-c2554ba0e7c6\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;3ec31153cd26\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Active Electrical Cables (AEC)\u0026lt;/strong\u0026gt; — high-speed active cable products with integrated retimer silicon\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;af623f3d-1de3-4cba-b396-a8e65368d1dd\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;fd20ca26d94f\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Smart Cable Modules (SCM)\u0026lt;/strong\u0026gt; — advanced cable modules with intelligent management and diagnostic capabilities\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;84109ee8-8333-4bb5-bf63-cab0489d98f9\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;c2cfa043d7ec\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Silicon Evaluation Platforms (SVB/EVB)\u0026lt;/strong\u0026gt; — evaluation boards and system validation platforms that enable silicon bring-up, characterization, and customer evaluation\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;5c317407-10c3-4eb7-a793-7c77c20e1971\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;e78775561758\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Rack-Scale Products\u0026lt;/strong\u0026gt; — AI chassis-class systems, switch trays, CEM cards, and associated system-level hardware\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;e903130c-a0bb-4d12-ac3b-61a5a30d5b52\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;a953dcd7674d\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Reference Designs \u0026amp;amp; Customer Enablement Hardware\u0026lt;/strong\u0026gt; — reference schematics, layout guidelines, and demonstration platforms that accelerate OEM adoption of Astera Labs silicon\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;d1f5817b-b577-49f0-ad14-ea1d3fbe5a09\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;b1f31c5f8042\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Oversee products through the full design lifecycle — from architecture definition, schematic/layout design, mechanical design, prototype build, validation, qualification, to production release\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;b90d939e-cd50-461e-bc2d-fa058aa558ba\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;007fc42176fd\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Ensure rigorous design review processes at each stage (architecture, schematic, layout, mechanical, pre-production) with clear entry/exit criteria and cross-functional participation\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;0e7f6dda-ca96-4500-9e1c-2ee5e34a2dbf\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;849fe1b89c68\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Make critical technical trade-off decisions that balance performance, cost, manufacturability, schedule, and risk across the product portfolio\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;db84dd8d-d69e-487b-b518-e96a900add08\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;23830a22ac8d\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Drive schedule discipline and engineering milestone execution — ensuring products hit market windows aligned with customer platform cycles and silicon availability\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h3 data-local-id=\u0026quot;e32ae75fd5b8\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;heading\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Electrical \u0026amp;amp; PCB Design\u0026lt;/h3\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;8dfb068e-bcd0-405b-b389-173bed75107e\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;db259a0c-fb66-406b-9afe-5491bef0e64f\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;4398ea6bf7e1\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Oversee high-speed PCB, flex circuit, and substrate design across the full product portfolio:\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;ccd0dfdd-8b90-4e97-9254-951c212b8f2e\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;09f81a82-8594-4071-bd3e-1d044dc949a7\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;4a9f7d997a06\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;AEC/SCM:\u0026lt;/strong\u0026gt; Retimer integration on flex/substrate, high-speed routing, power delivery, dense component placement in constrained cable module form factors\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;2d9b97df-f5c1-4294-83c8-50620f7d344a\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;4398ec601405\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Silicon Evaluation Platforms:\u0026lt;/strong\u0026gt; Complex multi-layer PCBs for silicon bring-up, high-speed channel characterization, and reference design generation\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;50a74cd2-1887-4d62-99e0-848f57b2f6de\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;2a9e0a9c25e1\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Rack-Scale Products:\u0026lt;/strong\u0026gt; Backplane/midplane design, switch tray PCBs, CEM card layouts, chassis power distribution, and high-density connector interfaces\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;821061f0-8d08-4141-a537-ed5c9ffc6af8\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;4b48bf20ba0e\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Reference Designs:\u0026lt;/strong\u0026gt; Production-quality schematics and layouts that serve as starting points for OEM customers integrating Astera Labs silicon\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;f5bfbc8b-ef9b-496d-b3ea-6d174055f0ee\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;999d5a79a554\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Ensure designs meet signal integrity requirements for 112G and 224G PAM4 lanes, including impedance control, loss budgets, crosstalk isolation, and return loss compliance\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;b9cf7299-7556-4070-ad71-6d47cea85474\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;86c8ee204ac6\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Drive component engineering decisions — selecting connectors, passives, power management ICs, and materials that meet performance, reliability, cost, and availability requirements\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;a053d2fe-f892-4adb-9ce5-233be822f66c\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;801ae5d4a110\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Establish and enforce design rules, layout guidelines, stackup definitions, and PCB/substrate technology selection criteria across all product lines\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;b0a43b46-19ff-4338-bf66-81528974a6f6\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;b35709ff6532\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Partner with Signal Integrity engineering to validate designs through simulation and correlation with measured performance\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h3 data-local-id=\u0026quot;965ee3a5650d\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;heading\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Mechanical Engineering\u0026lt;/h3\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;19883bd2-87ba-4e54-b742-7943f98533d7\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;28ed39b0-17b3-4b34-a078-833ae028bc04\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;8d562d23237c\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Direct mechanical engineering across the full product range:\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;9d1e659c-da06-4bdb-804d-52389f12c512\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;21f2f87e-7d5b-4a96-a3cc-e4c190ede399\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;996abb21a813\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;AEC/SCM:\u0026lt;/strong\u0026gt; Connector mating interfaces, housings, latching mechanisms, cable strain relief, overmold design, and thermal solutions for active cable modules\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;1606140d-2b0c-4690-852c-594fce0b5cd8\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;2a12fe312659\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Silicon Evaluation Platforms:\u0026lt;/strong\u0026gt; Board-level mechanical design, heatsink integration, test fixture compatibility, and debug accessibility\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;51c47b8f-e9e4-4ed7-b727-d4a6e6fb675f\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;c6b28de244a1\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Rack-Scale Products:\u0026lt;/strong\u0026gt; Chassis design, sheet metal, airflow/thermal architecture, cable management, hot-swap mechanisms, rack mounting, and system-level mechanical integration\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;7a48bb6a-2ea6-41a1-a57f-d3f7e5dc09c0\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;e970cdbd351d\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Ensure products meet relevant form factor standards (OSFP, QSFP-DD, OCP, Open19, or proprietary) with full compliance to mechanical interface specifications\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;40dfab5f-3e46-4e6e-9601-838ebaa7de92\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;300b6cea6c6f\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Drive thermal management design across all product lines — from retimer-scale thermal solutions in cable modules to chassis-level airflow and liquid cooling architectures for rack-scale systems\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;47ade640-a018-4f11-a9a8-023e6744b207\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;9df7fddd010f\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Oversee tolerance analysis, FEA/CFD simulation, material selection, and mechanical reliability assessments for all product designs\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;3f69ae8a-fd23-4114-862a-419572f77b6e\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;7df2dfb0d294\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Ensure mechanical designs support manufacturing scalability — DFM, DFA, tooling feasibility, and assembly sequence optimization\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h3 data-local-id=\u0026quot;65f522a36f99\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;heading\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Hardware Validation \u0026amp;amp; Qualification\u0026lt;/h3\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;f2929678-43be-418f-b081-f4ed089a19a4\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;9855eaa8-8e63-459e-8d18-2732793e9c36\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;f23d6e6c2b8b\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Own the hardware validation strategy and execution for all products — including electrical performance validation, mechanical/environmental stress testing, reliability qualification, and standards compliance\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;37e57482-106c-4c24-a574-e46d60745324\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;a2160ad37284\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Define validation plans that provide comprehensive coverage across signal integrity performance, power delivery, thermal behavior, mechanical durability, and environmental resilience\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;41ff10ae-1e69-47e5-9409-35dfcc24e15b\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;81880a59172a\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Establish qualification programs aligned with customer requirements, industry standards (GR-468, IEC, Telcordia, OCP specifications), and internal reliability targets\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;a0d31284-a7dd-4fcf-8e84-058e6a566191\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;fa6bde1d17eb\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Drive a data-driven validation culture — ensuring all design decisions are backed by measured data, all failures are root-caused, and all products ship with complete characterization\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;6d2728ba-898f-4085-9fe0-8da6d7b5e98b\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;f6781359d1e2\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Oversee interoperability testing with customer host platforms, switches, NICs, and system environments\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;c91cee16-63dc-479d-93fc-2d475723640f\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;b32afba6feee\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;For Silicon Evaluation Platforms, ensure validation coverage enables comprehensive silicon characterization and provides customers confidence in Astera Labs\u0026#39; silicon performance\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h3 data-local-id=\u0026quot;196694974329\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;heading\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Lab Engineering \u0026amp;amp; Infrastructure\u0026lt;/h3\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;9b028f00-fb5c-4592-b780-e8fb1e8d5e1b\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;b7d2356d-c751-4dbf-a873-80409fa06016\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;543e29aa38eb\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Define and execute the strategy for Astera Labs\u0026#39; hardware engineering labs — including high-speed electrical measurement, mechanical testing, environmental/reliability chambers, rack-scale system test environments, and production-representative assembly capabilities\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;58397d84-66cf-4340-a7a4-c059381ee78d\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;bc640b25fc7a\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Drive capital equipment planning, procurement, and installation for lab infrastructure that supports 112G/224G characterization (high-bandwidth oscilloscopes, BER testers, VNAs, TDR systems) as well as system-level power, thermal, and mechanical testing\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;8ed62c77-a492-448b-91a6-2073d66a750f\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;ffcc834b9912\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Ensure lab environments support rapid prototyping, debug, validation, and failure analysis workflows across all product lines — from cable modules to full rack configurations\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;5cd3ec05-dee9-457c-b5e0-89399ca3c120\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;71fd647b82bb\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Provide lab resources and environments for customer engagement activities — including joint debug sessions, interoperability testing, and silicon evaluation demonstrations\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;6f38fa9a-2604-4c0f-8b28-2514f0e87d71\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;69040989cc85\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Build and lead a lab engineering team responsible for equipment maintenance, calibration, measurement methodology, and lab operations\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h3 data-local-id=\u0026quot;fe02a18a5573\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;heading\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;OEM Engagement \u0026amp;amp; Customer Design Enablement\u0026lt;/h3\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;5ffead84-6f51-4ae8-a25c-69f1af31760d\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;cb11ec45-ed4a-4689-825c-12c695b05e9b\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;a2eae56e6980\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;OEM Collaboration on Customer Designs Using Astera Labs Silicon:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;7c13018f-fead-493d-877f-c38a5156b9e3\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;1adf5f5d-1383-4a37-bf88-d6769b781f9f\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;dd7f9b67ce26\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Lead hardware engineering engagement with OEM customers who are designing Astera Labs silicon into their own products — including hyperscale cloud providers, server OEMs, switch vendors, and cable/module manufacturers\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;d81f803d-dc9b-46e9-b708-890150ba59f2\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;0d0a3d243391\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Provide design review support for customer hardware designs incorporating Astera Labs retimers, re-drivers, and connectivity ASICs — reviewing schematics, layouts, power delivery, thermal solutions, and signal integrity\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;7481c69a-4aa6-4e2e-89d2-815600280132\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;468c75c4ee6b\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Develop and maintain comprehensive reference design packages — including reference schematics, recommended layouts, stackup guidelines, BOM recommendations, thermal design guides, and application notes\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;5c280c57-0c98-4093-991d-8747c2b50e5a\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;43b916709b03\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Create and publish hardware design guides, integration manuals, and best-practice documentation that enable OEM customers to achieve first-pass success with Astera Labs silicon\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;16966475-07bf-480f-a1ae-0b8258a53433\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;589adabf566a\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Establish design review frameworks and checklists that OEM customers can use for self-assessment, supplemented by Astera Labs expert review at critical milestones\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;8b4a2a5c-810c-4745-9c71-81f255c8e281\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;e4757eaca98c\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Customer Technical Support:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;9ec3417f-394d-43e6-a948-75408e373023\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;8ec599a3-6894-4b80-aec6-4da5519a6419\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;626b551b8101\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Build and lead a customer hardware engineering support function that provides responsive, expert-level technical assistance to OEM customers during their design and integration cycles\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;9dbd1eaa-797d-4c89-941d-81424cb7b1e7\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;8d7c39a6743b\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Support customer bring-up, debug, and troubleshooting activities — providing hands-on engineering engagement when customers encounter hardware integration challenges with Astera Labs silicon\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;6e770313-6501-40b6-8752-d144a18af2be\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;d86eb6e22896\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Drive resolution of customer-reported hardware issues — coordinating across internal teams (silicon, firmware, SI, validation) to provide root cause analysis and corrective guidance\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;dbb26193-66ef-452b-b003-46ed9265be72\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;70c53a50dee4\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Establish escalation processes and service-level expectations for customer hardware engineering support, ensuring timely and high-quality responses\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;ed1b4d0b-fde8-48f3-828c-630357b9d204\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;794ac101b1f6\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Travel to customer sites as needed to provide on-site design review, debug support, or integration assistance for critical programs\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;469e225e-e2b4-41fe-9d06-c15c4a8a89bd\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;402dc2ecad37\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Internal \u0026amp;amp; External Design Collaboration:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;3add3e12-1e42-4d43-b477-4c325a0e1498\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;5c307251-958d-4939-bd11-1522c849dc9a\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;c72407fec742\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Serve as the bridge between Astera Labs\u0026#39; internal product designs and the external ecosystem of customers building with Astera Labs silicon — ensuring learnings flow bidirectionally\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;553578cd-ab19-4efe-af60-bd22978859ff\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;de985534ee12\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Capture common customer design challenges, failure modes, and best practices — feeding these back into reference designs, design guides, evaluation platforms, and silicon requirements\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;fb8397d7-253c-4bb3-a233-fbf696f21003\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;8b548dfb69e1\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Partner with Sales, FAE, and Product Management teams to identify high-value customer engagements and prioritize hardware engineering support resources\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;1474e933-f47e-4be5-9aad-c8cfeaa6fa5b\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;06708f42b5f3\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Collaborate with silicon design teams to provide hardware-level feedback on package design, pin assignment, power requirements, and thermal specifications based on customer and internal design experience\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;bd212ae3-665b-40f6-baab-45ca2a0746d3\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;be6e21d17aa6\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Support joint development programs with strategic OEM partners — including co-designed products, custom form factors, and platform-specific optimizations\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h3 data-local-id=\u0026quot;72ec8aa9174c\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;heading\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Cross-Functional Collaboration\u0026lt;/h3\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;4703627d-0936-4a22-a795-39b45505d917\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;a15b0058-bc63-446e-9b28-1c31d6d86b54\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;bb6cc7c72827\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Partner closely with \u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Signal Integrity\u0026lt;/strong\u0026gt; engineering to ensure designs meet channel performance requirements and simulation-to-measurement correlation is maintained\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;c9c71a2b-b0a9-4f09-9ee0-69312139bcd3\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;959be0b8f4fd\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Collaborate with \u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Firmware Engineering\u0026lt;/strong\u0026gt; to ensure hardware-firmware co-design — including power sequencing, thermal management, CMIS interface implementation, BMC integration (for rack-scale products), and diagnostic feature support\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;a96fd099-772e-48f5-a921-d094978c356f\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;4b8ee416b544\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Work with \u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;NPI and Manufacturing Engineering\u0026lt;/strong\u0026gt; to ensure designs are manufacturable, testable, and scalable at volume — participating in DFM/DFA/DFT reviews and supporting production ramp across CMs and ODMs\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;75d1b462-f5fd-4da0-8fc4-e8b5418bff14\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;c07a5c1de779\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Engage with \u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Quality and Reliability\u0026lt;/strong\u0026gt; teams to ensure products meet Astera Labs\u0026#39; quality standards and customer reliability expectations\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;b6a3e49c-1e1e-4180-bd40-b761356a1d44\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;514406865ca2\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Interface with \u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Product Management\u0026lt;/strong\u0026gt; to align development priorities with market opportunities, customer requirements, and business objectives\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;9df4f9d4-0b14-485d-a791-155c65dbc880\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;f47241f1b8c8\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Partner with \u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Sales and FAE teams\u0026lt;/strong\u0026gt; to support customer design-in activities, provide technical differentiation during competitive evaluations, and ensure customer success drives revenue growth\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;f86ce61d-de38-41d2-b066-13ecac0f27ac\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;70f49bf4c019\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Support \u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Customer Engineering\u0026lt;/strong\u0026gt; and \u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Applications\u0026lt;/strong\u0026gt; teams in resolving platform integration issues and driving design improvements based on field feedback\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;aae449b2-4391-4dad-872f-71d90677a069\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;c3d71288d022\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Collaborate with \u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Silicon Engineering\u0026lt;/strong\u0026gt; to ensure evaluation platforms provide optimal silicon bring-up, characterization, and demonstration capabilities — and that customer hardware integration feedback informs future silicon development\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h3 data-local-id=\u0026quot;2e7fde9265f8\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;heading\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Standards \u0026amp;amp; Industry Engagement\u0026lt;/h3\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;f275ce5c-c330-4e5f-b7fd-caaf852d68cb\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;413ab778-a0a2-4722-ba36-4c50c5dc3fe0\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;930f482b6e2c\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Ensure hardware designs comply with relevant industry standards — IEEE 802.3ck/dj, OIF CEI-112G/224G, SFF-TA (OSFP, QSFP-DD), CMIS, OCP specifications, and emerging rack-scale standards\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;62062356-19dd-45b2-bcd5-2eb0231c40f6\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;c86043cf9887\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Represent Astera Labs in industry standards bodies, MSAs, and technical working groups as appropriate\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;2ca117ae-230f-4e07-af6f-b37353c4bed3\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;088ccbbf1492\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Monitor competitive landscape, emerging technologies, and standards evolution to inform roadmap and design decisions\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;92956315-6d19-4c5d-bba7-ef522e9483af\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;ae8084bf6185\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Engage with OEM customers and industry partners on pre-standard technologies and next-generation specifications\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;hr data-local-id=\u0026quot;b456d42f-dabc-45f6-b6be-df40996cb89f\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;rule\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;h2 data-local-id=\u0026quot;a3c6a4965a42\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;heading\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Basic Qualifications\u0026lt;/h2\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;afcac922-75d2-445e-810c-678b61c947a4\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;f2d91d58-af12-47c1-8aae-ef61849b787d\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;fd213c4c4b8c\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, Computer Engineering, or related technical discipline\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;6cdc1126-c698-4f55-8fee-ea68ddb0ff1a\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;2ac52e4508c2\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;18+ years of progressive experience in hardware design engineering for high-speed interconnect, transceiver/module, cable assembly, evaluation platforms, or rack-scale system products\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;8241105f-8826-4e92-b0fe-e04a214dc8df\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;ced69f265477\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;8+ years in engineering management/leadership roles, including managing managers and building multi-team organizations\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;52afa2a6-fd99-42ef-8bd8-938a6134c2ad\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;c69f544a90c4\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Proven track record leading engineering teams through full product development lifecycle — from concept through qualification and volume production — across product scales from modules to systems\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;7398e14e-0a0c-4e8e-a598-7ec9bc943c6c\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;5bebccea1dc5\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Deep technical expertise in high-speed PCB/substrate design, signal integrity, power delivery, and mixed-signal circuit design at 56G/112G PAM4 data rates or above\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;cdee82b3-44a0-4a67-9ece-914bdd4fae5a\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;22caee269566\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Strong background in mechanical engineering for interconnect and system products — connector design, thermal management, chassis architecture, and form factor compliance\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;923a4dfb-5af4-4a31-aebd-507464fa849a\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;ea426fa09898\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Demonstrated experience establishing and executing hardware validation and qualification programs for high-reliability products\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;08f2947b-5565-442c-b41b-3e36c70cdd1f\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;e2097f0b005e\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Experience building and managing hardware engineering lab infrastructure and measurement capabilities\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;4c013cb7-b086-4d99-8d80-1527c350f242\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;5cfeda6a99e3\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Proven experience engaging with OEM customers on hardware design enablement — including design reviews, reference design development, and customer technical support for silicon/ASIC integration\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;e14f9b5c-7416-4148-abff-ddb04c4d3701\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;30c34675f2d9\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Proven ability to make both strategic technology decisions and detailed technical trade-offs that balance performance, cost, schedule, and manufacturability\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;08d3dfae-9d76-40db-adca-3d04aa54a5bf\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;4ce25d0de049\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Experience managing engineering teams through hyper-growth — scaling organizations, processes, and infrastructure simultaneously\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;7b16d0d1-cff6-4705-a6ef-57c5fd2f97a6\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;2d8b33d627ff\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Strong executive communication skills — able to present technology strategy, program status, and risk assessments to C-level leadership and customer executives\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;2b2efc94-adc3-4281-abf7-730aa69847be\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;cb358ffecbf5\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Experience partnering with contract manufacturers and ODMs in Asia for hardware product realization\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h2 data-local-id=\u0026quot;19918762e1b1\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;heading\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Preferred Qualifications\u0026lt;/h2\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;da2287c4-08ce-46c7-be2d-3dbd55acfed8\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;68ed0eec-a66c-416e-8c72-d0ff8c476318\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;744600075293\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Master\u0026#39;s or Ph.D. in Electrical Engineering with emphasis on high-speed interconnects, electromagnetic design, or mixed-signal systems\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;fda35044-65b6-4f41-86cc-37ac8de8a389\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;705699944b71\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Direct experience developing Active Electrical Cables (AEC), Smart Cable Modules (SCM), optical transceivers, or high-speed cable/connector assemblies\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;e20f4ee3-7d89-451e-84bf-fdc51b260a90\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;c005b5a1a6df\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Experience designing silicon evaluation platforms (EVBs/SVBs) for complex SoCs, ASICs, or connectivity silicon\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;37786ff4-083e-4699-ba76-ff6f99980227\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;f0ba816d50b5\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Experience developing rack-scale or chassis-class hardware products for data center, hyperscale, or AI infrastructure applications (switch chassis, OCP systems, or equivalent)\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;2f54b1a6-cf7f-4062-909e-02d2311bd8e2\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;3189bf168438\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Track record of successful OEM design enablement — helping customers achieve first-pass success integrating complex semiconductor products into their hardware platforms\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;5de9d20b-a620-4326-acaf-ddaa7bb6289b\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;ce8807ebbfc8\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Experience building and scaling customer-facing hardware engineering support organizations\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;5f8c52eb-5738-44b7-bb77-e96df89e1e6c\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;d4a82e0f58e2\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Experience with 224G/lane (1.6T aggregate) interconnect technology and next-generation substrate/connector/cable architectures\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;079415a4-1374-4f43-9bbb-005d529d582f\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;04e261e3a8d1\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Track record delivering connectivity products to hyperscale customers (AWS, Google, Microsoft, Meta, NVIDIA, or equivalent) for AI/ML infrastructure applications\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;d093e146-ab3c-42b8-a756-67249ee48e93\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;a9264ae62d7d\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Experience integrating retimer ASICs into cable module or system-level products\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;7b9fce26-0110-4062-8e91-2d236015dc25\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;ee29aa7978d0\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Deep familiarity with relevant standards: IEEE 802.3ck/dj, OIF CEI-112G/224G, SFF-8636, CMIS 5.x+, OSFP, QSFP-DD, OCP specifications\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;c920beb0-e319-439c-ab7a-d73720fee4e9\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;78f512225af5\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Experience with rack-scale system design including power distribution, thermal/airflow architecture, BMC/management interfaces, and high-density backplane/midplane design\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;ba1453b8-3c69-499e-9f83-c37b286e0b2a\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;7f25a300cce3\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Background in FMEA, DFMEA, robust design methodologies, and six-sigma quality approaches\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;24621550-1d54-4d41-abdd-81e6146c1566\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;65fa2ad30308\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Mandarin language proficiency for direct engagement with manufacturing partners in China\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;62c9df31-d38e-4d57-8041-3ce924569154\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;41e2b92ee4b0\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Experience with simulation and EDA tools (Cadence Allegro/OrCAD, Ansys HFSS/SIwave, Keysight ADS, SolidWorks/Creo, thermal/CFD simulation tools)\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h4 data-local-id=\u0026quot;6fd549ccf151\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;heading\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot; data-pm-slice=\u0026quot;1 3 []\u0026quot;\u0026gt;Base salary range is $220,000 to $280,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/h4\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025526005,"name":"Hardware Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4702155005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4438890005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"India","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Bangalore","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":"Hardware Engineering","value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Manufacturing","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4702155005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2614","title":"Hardware Engineering Operations / Manufacturing, AVP","company_name":"Astera Labs","first_published":"2026-06-04T13:43:23-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;h1 data-local-id=\u0026quot;46934cd55fd6\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;heading\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot; data-pm-slice=\u0026quot;1 3 []\u0026quot;\u0026gt;AVP of Hardware Engineering Operations/Manufacturing\u0026lt;/h1\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;ee96d9e48d5a\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;d9b709a38d57\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Astera Labs is scaling rapidly as the connectivity backbone of rack-scale AI infrastructure, and our hardware manufacturing footprint is scaling with it. Smart Cable Modules (SCM), Active Electrical Cables (AEC), evaluation boards, AI Chassis-class systems, and ODM-built products are central to how we deliver purpose-built connectivity at hyperscale. We\u0026#39;re hiring an AVP of Hardware Engineering Operations/Manufacturing to bring focused, senior leadership to this growing function.\u0026lt;/p\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;fa000c7cc455\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;This is a wide-ranging role spanning the full breadth of Astera Labs\u0026#39; hardware portfolio — from Smart Cable Modules to rack-scale chassis-based products. You\u0026#39;ll own manufacturing strategy and execution across SCM, AEC, evaluation boards (SVB/EVB), AI Chassis-class systems, and ODM-built products such as switch trays and CEM cards. You\u0026#39;ll be the primary leader partnering with our contract manufacturers across China and the rest of Asia, driving quality, capacity, cost, and time-to-market as we scale to meet AI infrastructure demand.\u0026lt;/p\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;1195ca929091\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;86023ea6-89bd-4685-996c-771c9c11be9e\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;4a304489-0eaa-4ce9-830d-99d35bf47ab0\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;974fca778904\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Leadership, Strategy \u0026amp;amp; CM/ODM Partnership\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;32da4247-0ae4-41fa-80f3-3b5475db393f\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;d029e704-3ead-4c09-ae41-bbbca75a1a56\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;0d65384f22b2\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Lead Astera Labs\u0026#39; hardware engineering operations and manufacturing organization across SCM, AEC, evaluation boards, AI Chassis-class systems, and ODM programs\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;93374844-bf3e-47da-82db-f77db2faf0ca\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;15f0a1be38e5\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Own day-to-day partnership with contract manufacturers across China and the rest of Asia — driving cadence, accountability, and site ramps from qualification through full production maturity\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;7f650be4-b50a-45c4-b130-36744678e030\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;390bb0587f16\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Manage ODM engagements for switch trays, CEM cards, chassis-based systems, and adjacent products, navigating the differences from traditional CM models\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;dc6e05b1-1c2e-4a68-9264-180535475111\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;cd826728d242\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Partner with Hardware Engineering, Product, Supply Chain, and Quality leaders, and represent hardware operations in executive reviews\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;5b016da6-6793-4a7d-95b9-6c55b2c370ab\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;f2214f95dad4\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;New Product Introduction (NPI) \u0026amp;amp; Advanced Manufacturing\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;605330a0-d9f7-4504-8007-76d037eb91fe\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;667b8e11-9aca-40b2-b7f5-d01f84d7b2c2\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;c0d383ac9065\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Drive Design for Manufacturability (DFM) reviews on early product designs to validate completeness and manufacturability before release to the floor\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;9cc32427-d074-4ade-8312-60f730b5bf7b\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;84e4f525f380\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Lead production scaling — estimating costs, production times, and staffing requirements for new designs\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;665cf7f9-bc2c-46c9-b938-841065d72be4\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;f2f79a2aeaa3\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Prepare and maintain technical documentation for new manufacturing processes and engineering procedures\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;d3e9d0ed-da5c-48f5-ac7a-34b0d5bc636e\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;d418b0343b2a\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Process \u0026amp;amp; Sustaining Engineering\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;8226bcd9-426a-4b14-86a1-a0d081cbf5e0\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;707d1a7d-fd1c-4192-80f8-f5a621edb5cc\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;c2c8503eab20\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Design factory layouts and analyze workflows to achieve maximum production efficiency\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;aaa5d98f-d918-4162-a1f7-8b1e8eaebc8e\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;9380862416fa\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Troubleshoot operational bottlenecks and investigate material use variances directly on the assembly line\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;d25fd50d-398d-49b5-9c35-87366fd5cde1\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; 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data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Test Engineering\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;32a22bad-018d-467d-bb7f-fb5d397f013e\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;b25c65e9-b8b6-453d-b300-b27fb5a61480\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;2c24f1ea0e69\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Architect test parameters for finished products to validate they meet exact process requirements\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;411f0492-618d-4bcc-9d00-af8ec6cf97b2\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;bc5dc8eb07e2\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Coordinate the design, procurement, build, and debug of automated test equipment\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;86dbcb98-5877-4ee4-aa23-3d3ca0a8f617\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;71811e583443\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Test products to identify anomalies and ensure compliance with functional and safety standards\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;d254e8aa-d050-4e58-b52e-7f7aaf00dfef\u0026quot; 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data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;33e6700c60b7\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Lead failure analysis using statistical methods and recommend changes in designs, tolerances, or processing methods\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;4e924934-eb2b-4303-bdc3-da4ad083e579\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;e478b92a534c\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; 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data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Master\u0026#39;s degree in Electrical Engineering or related field\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;ff607dc7-20ff-46f4-b8f5-4387c250f7e1\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;ffd50728032f\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Direct experience with Active Electrical Cables (AEC), optical transceivers, Smart Cable Modules, or high-speed cable/connector assemblies\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;923ede5c-5945-44ce-83b6-473f5907a74b\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;ea8bc7972070\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Experience manufacturing rack-scale or chassis-class systems for hyperscale or AI infrastructure\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;318228d1-44b2-4b41-b866-8a078eaa107f\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;0c35b636e3db\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Experience with ODM engagement models for system-level products (switch trays, CEM cards, or similar)\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;0f6b13dd-445b-49e0-a3c2-1ed24ac8db32\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;b1b2b2300a99\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Chinese language proficiency (Mandarin) for direct CM partnership in China\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Base salary range is $280,000 to $310,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025526005,"name":"Hardware Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4674439005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4425378005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Hardware Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4674439005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2373","title":"Hardware Lab Engineer","company_name":"Astera Labs","first_published":"2026-04-02T13:46:45-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;u\u0026gt;Overview\u0026lt;/u\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs Inc. is seeking an experienced and self-driven \u0026lt;strong\u0026gt;Hardware Lab Engineer\u0026lt;/strong\u0026gt; to join our dynamic team in developing world class connectivity products for AI infrastructure.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;u\u0026gt;Job Description\u0026lt;/u\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This role will work closely with firmware, system validation, quality, and product engineers to support silicon bring-up, characterization, and debug activities through hands-on lab execution. The ideal candidate will have a deep understanding of circuits, hands-on experience with PCBAs and silicon test environments, and the ability to work on complex, open-ended tasks with minimal oversight.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;u\u0026gt;Key Responsibilities\u0026lt;/u\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Setup and maintain test environments for silicon validation and characterization. Configure and update hardware, software, firmware, and applications. Replicate BKCs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Conduct hands-on testing of silicon devices including PCIe Gen5/6/7, CXL, Ethernet, and other high-speed interfaces\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Install and configure servers, including FW, BIOS, OS, and network\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;RMA intake/triage: inspection, electrical verification, screening (including CSAM inspection), and prioritization\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Manage logistics and communications with external labs\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Organize, track, and distribute lab equipment, hardware, and peripherals\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ad hoc PCBA rework and soldering of fine-pitch SMD components\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop, document, and maintain lab procedures\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;u\u0026gt;Required Qualifications\u0026lt;/u\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, Computer Engineering, or related field\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;5-12+ years of hands-on experience in lab environments supporting silicon validation or hardware development\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency with high-speed test equipment (oscilloscopes, protocol analyzers, BERTs, multimeters)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with high-speed interface testing (PCIe, CXL, DDR, Ethernet, or SerDes)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong programming skills in Python for test automation\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with Linux operating systems and command-line tools\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Demonstrated experience coordinating with third-party testing laboratories and managing logistics, including sample shipping, chain of custody, and scheduling\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong organizational skills for managing multiple RMA cases simultaneously and prioritizing based on severity/impact\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;u\u0026gt;Preferred Qualifications\u0026lt;/u\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience with post-silicon validation of ASICs, SoCs, or Retimer/PHY products\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of analog/mixed-signal circuit testing and debugging techniques\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with JTAG, I2C, SPI, and other embedded interfaces\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with PCB design, schematic reading, and signal integrity concepts\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of data center systems architecture (servers, AI platforms, networking equipment)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Understanding of ATE (Automated Test Equipment) systems and production test methodologies\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with defect screening methodologies including visual inspection, electrical testing, and acoustic imaging\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with complete RMA lifecycle management from intake through root cause analysis and corrective action\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of common semiconductor failure modes and failure analysis techniques including die attach inspection, delamination detection, void analysis, and crack identification\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with formal compliance testing and industry standards\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;The base salary range is $160,000.00 USD – $200,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.\u0026amp;nbsp;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025526005,"name":"Hardware Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4678168005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4427225005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Human Resources","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4678168005,"updated_at":"2026-09-28T18:33:10-04:00","requisition_id":"9027","title":"HR Business Partner","company_name":"Astera Labs","first_published":"2026-03-27T11:10:19-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Astera Labs is seeking an \u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;HR Business Partner\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; to join our People team in San Jose, CA. In this role, you will support Astera’s G\u0026amp;amp;A functions and smaller engineering groups, serving as a trusted advisor, coach, and partner to leaders, managers, and employees. This is an excellent opportunity to build your business partnership skills across multiple client groups in a fast-growing semiconductor company.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;You will bring solid HRBP/Generalist experience, foundational employee relations skills, and working knowledge of US labor and employment law to help ensure our people practices are effective and compliant as we scale. This role is key to supporting the talent strategies, people leader development, and organizational health that enable Astera’s corporate functions and engineering teams to thrive. As you grow in the role, there will be opportunities to expand your client portfolio and take on larger, more complex business groups.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ol\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; Business Partnership \u0026amp;amp; Coaching\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ol\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Serve as a reliable partner to G\u0026amp;amp;A and small engineering people leaders, providing day-to-day coaching on people management, team dynamics, and leadership fundamentals\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559685\u0026amp;quot;:720}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Build strong, trusting relationships with employees and managers, ensuring accessible and credible HR support across your client groups\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559685\u0026amp;quot;:720}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Coach managers on performance conversations, career development discussions, feedback delivery, and navigating common team challenges\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559685\u0026amp;quot;:720}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Develop an understanding of the unique demands of semiconductor product development and corporate functions to deliver practical people solutions\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559685\u0026amp;quot;:720}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Support the onboarding and integration of new managers within your client groups\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559685\u0026amp;quot;:720}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ol\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; Employee Relations \u0026amp;amp; Compliance\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ol\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Serve as a point of contact for employee relations matters across your client groups, handling investigations, performance issues, interpersonal conflict, and conduct concerns with professionalism and care\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559685\u0026amp;quot;:720}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Apply working knowledge of US labor and employment law—including federal, state, and local regulations—to advise leaders and support compliant people decisions, escalating complex matters to senior HRBPs or Employment Counsel as appropriate\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559685\u0026amp;quot;:720}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Conduct fair, thorough, and well-documented workplace investigations, partnering with senior HR team members and Legal on higher-risk matters\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559685\u0026amp;quot;:720}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Help identify compliance risks and partner with HR Operations to ensure policies, practices, and manager actions align with legal requirements\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559685\u0026amp;quot;:720}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Stay current on evolving employment legislation and regulatory changes, surfacing relevant updates to the broader HR team\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559685\u0026amp;quot;:720}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Provide clear, empathetic, and sound guidance to managers navigating terminations, leaves of absence, accommodations, and other sensitive situations, with support from senior partners on complex cases\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559685\u0026amp;quot;:720}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ol\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; Talent Strategy \u0026amp;amp; Organizational Effectiveness\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ol\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Support leaders in your client groups on organizational design, role clarity, and team structure to enable effective execution\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559685\u0026amp;quot;:720}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Contribute to talent reviews, retention planning, and succession planning for roles within your groups, partnering with senior HRBPs on cross-functional initiatives\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559685\u0026amp;quot;:720}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Assist with headcount planning and workforce decisions, helping leaders balance near-term needs with longer-term capability building\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559685\u0026amp;quot;:720}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Identify talent risks early and work proactively with leaders to address retention and engagement challenges within your client groups\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559685\u0026amp;quot;:720}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ol\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; Performance Management\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ol\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Support leaders and managers through performance cycles, calibration sessions, and compensation reviews, helping ensure fair and consistent outcomes\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559685\u0026amp;quot;:720}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Help ensure performance management practices are applied consistently and in compliance with company policy and legal standards across your client groups\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559685\u0026amp;quot;:720}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Partner with Compensation and HR Operations to support equitable pay decisions and address compensation-related questions\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559685\u0026amp;quot;:720}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ol\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; Operational Excellence \u0026amp;amp; Growth\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ol\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Identify gaps in people processes or manager capability within your client groups and propose practical solutions\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559685\u0026amp;quot;:720}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Partner with HR Ops and Centers of Excellence to help simplify, standardize, and scale HR practices as the organization grows\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559685\u0026amp;quot;:720}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Actively seek opportunities to learn and develop, building expertise that prepares you to take on larger, more complex client groups over time\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559685\u0026amp;quot;:720}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Operate with an owner’s mindset—taking accountability for outcomes, not just recommendations\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559685\u0026amp;quot;:720}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Basic Qualifications\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Bachelor’s degree in Human Resources, Business Administration, Organizational Development, or related field\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559685\u0026amp;quot;:720}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;4–6 years of HR Business Partner or HR Generalist experience, ideally with some exposure to engineering or technical organizations\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559685\u0026amp;quot;:720}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Working knowledge of US employment and labor law, including federal and California state regulations (wage and hour, leaves, accommodations, terminations, harassment/discrimination)\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559685\u0026amp;quot;:720}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience handling employee relations matters, workplace investigations, and sensitive personnel issues with sound judgment\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559685\u0026amp;quot;:720}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Demonstrated ability to build trusted relationships with managers and employees at all levels\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559685\u0026amp;quot;:720}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Comfort operating in a fast-paced, evolving environment with the ability to manage multiple priorities\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559685\u0026amp;quot;:720}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Clear and effective communicator who can advise and influence people leaders with credibility\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559685\u0026amp;quot;:720}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Preferred Qualifications\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;PHR, SHRM-CP, or equivalent certification\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559685\u0026amp;quot;:720}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience supporting G\u0026amp;amp;A functions (Finance, Legal, People Ops, IT) in addition to technical teams\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559685\u0026amp;quot;:720}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Exposure to organizations going through rapid scaling or hypergrowth phases\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559685\u0026amp;quot;:720}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Analytical mindset with experience using people data to inform decisions\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559685\u0026amp;quot;:720}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Interest in or experience with the semiconductor, AI, data center, or connectivity technology space\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559685\u0026amp;quot;:720}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;A growth orientation—eagerness to take on new client groups, build new capabilities, and develop toward a senior HRBP role\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559685\u0026amp;quot;:720}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Salary range is $135,000 to $170,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4000202005,"name":"HR","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4720076005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4447498005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"HR Operations","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4720076005,"updated_at":"2026-09-24T15:02:20-04:00","requisition_id":"2026-334","title":"HR Operations Specialist","company_name":"Astera Labs","first_published":"2026-07-30T17:52:10-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot; data-ccp-parastyle-defn=\u0026quot;{\u0026amp;quot;ObjectId\u0026amp;quot;:\u0026amp;quot;276295ed-5df2-5456-988c-5fdbab071054|1\u0026amp;quot;,\u0026amp;quot;ClassId\u0026amp;quot;:1073872969,\u0026amp;quot;Properties\u0026amp;quot;:[201342446,\u0026amp;quot;1\u0026amp;quot;,201342447,\u0026amp;quot;5\u0026amp;quot;,201342448,\u0026amp;quot;1\u0026amp;quot;,201342449,\u0026amp;quot;1\u0026amp;quot;,469777841,\u0026amp;quot;Aptos\u0026amp;quot;,469777842,\u0026amp;quot;Arial\u0026amp;quot;,469777843,\u0026amp;quot;Aptos\u0026amp;quot;,469777844,\u0026amp;quot;Aptos\u0026amp;quot;,201341986,\u0026amp;quot;1\u0026amp;quot;,469769226,\u0026amp;quot;Aptos,Arial\u0026amp;quot;,268442635,\u0026amp;quot;24\u0026amp;quot;,335559739,\u0026amp;quot;180\u0026amp;quot;,335559738,\u0026amp;quot;180\u0026amp;quot;,469775450,\u0026amp;quot;First Paragraph\u0026amp;quot;,201340122,\u0026amp;quot;2\u0026amp;quot;,134234082,\u0026amp;quot;true\u0026amp;quot;,134233614,\u0026amp;quot;true\u0026amp;quot;,469778129,\u0026amp;quot;FirstParagraph\u0026amp;quot;,335572020,\u0026amp;quot;1\u0026amp;quot;,469775498,\u0026amp;quot;Body Text\u0026amp;quot;,469778324,\u0026amp;quot;Body Text\u0026amp;quot;]}\u0026quot;\u0026gt;Role Overview\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:180,\u0026amp;quot;335559739\u0026amp;quot;:180}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Body Text\u0026quot;\u0026gt;As an Immigration and HR Operations Specialist, you will manage employment-based immigration programs while helping employees and leaders navigate critical moments with clarity, empathy, and precision. You will own cases across the employee lifecycle, partner with external immigration counsel, and ensure stakeholders have timely visibility into status, deadlines, and next steps.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:180,\u0026amp;quot;335559739\u0026amp;quot;:180}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Body Text\u0026quot;\u0026gt;You will also strengthen the operating systems behind a fast-growing organization. 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data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;0\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Track case status, deadlines, documentation, and compliance requirements across the employee lifecycle.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Proactively identify risks, communicate impacts, and escalate time-sensitive matters to drive cases to resolution.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Maintain accurate, confidential records and deliver clear reporting on immigration program activity and operational trends.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;HRIS and Process Operations\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;0\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Provide Tier 2/3 support for HRIS-related Jira tickets, including data errors, workflow failures, and access issues, resolving issues within the system whenever possible.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Partner with HRBPs, Payroll, IT, and HR Operations teammates to translate process needs into effective system configuration and workflow changes.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Document system configurations, workflows, and standard operating procedures to support consistency, auditability, and knowledge continuity.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot;\u0026gt;Basic Qualifications\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:180,\u0026amp;quot;335559739\u0026amp;quot;:180}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Bachelor’s degree in Human Resources, Business Administration, or a related field.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;3\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;-5 years of experience in HR operations, program management, or immigration case management.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Demonstrated experience managing employment-based immigration processes and working with external immigration counsel or service providers.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; 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data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;13\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Experience working with HRIS platforms, service desk tools such as Jira, and workflow or case-management systems.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot;\u0026gt;Salary range is $117,000 to $130,000 depending on experience, level, and business need. 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By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. 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This role combines deep technical expertise with strong people leadership and program management skills.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;The successful candidate will be responsible for managing a team of \u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;IP \u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;digital\u0026lt;/span\u0026gt; \u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;design engineers while driving the successful execution of complex \u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;IP \u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;development programs. The role requires close collaboration with Architecture, Verification, Physical Design, DFT, Firmware, Software, Product Engineering, and SoC Integration teams to ensure delivery of high-quality IPs that meet performance, power, area, quality, and schedule objectives.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;This position offers the opportunity to influence product roadmaps, establish engineering best practices, and contribute to the development of industry-leading semiconductor solutions.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Key Roles \u0026amp;amp; Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Technology Background\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Deep understanding of complex networking protocols such as PCIE, UALink, Ethernet is a must\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience of working on latest generations of these protocols is highly desirable.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Expertise of standard front-end design flows / tools / HDLs for digital design\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Technical Leadership\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Lead the end-to-end development of digital Ips / Subsystems from architecture through silicon validation.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Partner with architects and product teams to define IP requirements, features, performance targets, and scalability needs.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Drive microarchitecture development and ensure alignment with overall SoC and product requirements.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;7\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Review and approve architecture specifications, design documents, RTL implementations, and verification plans.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;8\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Ensure IP designs achieve performance, power, area (PPA), reliability, and quality targets.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;9\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Lead technical reviews and provide guidance on complex design challenges.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;10\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Drive design trade-off decisions and risk mitigation strategies.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Lead the post-silicon support once silicon is back in the lab. Prior experience of post-silicon work is highly desirable.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;IP Development \u0026amp;amp; Delivery\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;8\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Own the successful delivery of IP/Subsystem releases according to committed schedules and quality goals.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;8\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Ensure all IP deliverables, including RTL, verification collateral, documentation, synthesis constraints, and integration guides, are completed and released on time.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;8\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Drive IP reuse strategies to maximize engineering efficiency across multiple products and platforms.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;8\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Establish standards for IP packaging, version control, configuration management, and release processes.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;8\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Ensure compliance with internal design methodologies and industry best practices for all front-end flows such as Lint, CDC, Power Analysis, Timing Constraints.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;8\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Work with cross-functional teams to ensure that requirements, dependencies from all stakeholders are met and incorporated into the deliverables\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Team Leadership \u0026amp;amp; People Management\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;9\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Build, lead, and mentor a high-performing IP design team.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;9\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Set clear goals and expectations for team members.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;9\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Conduct performance reviews, development planning, and regular coaching sessions.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;9\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Identify skill gaps and implement training and development initiatives.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;9\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Participate in workforce planning, recruiting, interviewing, hiring, and onboarding activities.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;9\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Foster an inclusive, collaborative, and innovation-driven culture.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;9\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;7\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Promote technical excellence and continuous learning within the organization.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Required Qualifications\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Education\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;14\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, or a related field.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;14\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Master\u0026#39;s degree preferred.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;15\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;15+ years of experience in semiconductor design and development.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;15\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;5+ years of experience managing engineering teams and complex IP development programs.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;15\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Proven track record of successfully delivering multiple IPs into production silicon.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;15\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience managing cross-functional engineering programs across geographically distributed teams.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; 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data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;15\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;7\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience managing multiple concurrent IP development programs.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; 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data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;15\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;9\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience driving IP reuse strategies across multiple product generations.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184256005,"name":"Design Engineering CCE2","child_ids":[],"parent_id":null}],"offices":[{"id":4049113005,"name":"Bengaluru","location":"India","child_ids":[],"parent_id":4052109005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4670099005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4423330005,"location":{"name":"Bengaluru, Karnataka, India"},"metadata":[{"id":12122734005,"name":"Country","value":"India","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Bengaluru","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Design Verification","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4670099005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2343","title":"IP Design Verification Director ","company_name":"Astera Labs","first_published":"2026-03-05T16:50:48-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Job Title: Director of Design Verification\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;We are seeking a seasoned \u0026lt;strong\u0026gt;Director of Design Verification\u0026lt;/strong\u0026gt; with 20+ years of experience to lead verification for a flagship product in our portfolio. This is a hands-on leadership role where you will define the verification strategy, oversee execution, and ensure first-pass silicon success for complex SoC designs in server, storage, and networking domains.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Own and drive the end-to-end verification methodology for a specific product line.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead, mentor, and grow a team of engineers, fostering technical excellence and innovation.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Guide verification of industry-standard protocols such as PCIe and CXL across Physical, Link, and Transaction layers.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Champion advanced methodologies (UVM, formal verification, AI-augmented flows) to accelerate coverage closure and improve efficiency.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate closely with RTL design, architecture, and software teams to debug, refine, and optimize verification processes.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Represent verification in executive reviews, customer engagements, and industry forums.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Shape workforce transformation by building hybrid skill sets and preparing the team for AI-driven verification challenges of the 2030s.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s degree in Electrical or Computer Engineering (Master’s preferred).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;15+ years of experience in design verification, with a proven track record of leading teams and delivering complex SoC/silicon products.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep expertise in PCIe/CXL protocols (Gen3 and above) and experience with third-party Verification IPs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong background in UVM-based test plan development, assertions, coverage analysis, and abstraction layer design.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Demonstrated ability to manage priorities, engage with stakeholders, and drive organizational success.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Hands-on expertise with Verification IPs for PCIe/CXL (Gen3 and above).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep experience in UVM-based test plan development, sequence generation, and coverage analysis.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong background in writing assertions, cover properties, and analyzing coverage data.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience in developing VIP abstraction layers to simplify and scale verification deployments.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Expertise in verifying PCIe/CXL Physical, Link, and Transaction layers, including compliance for EP/RC.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with buffering, queuing, and QoS in complex NoC-based SoCs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;System-level performance analysis on switching fabrics.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with AI-driven verification methodologies and workforce transformation strategies.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184260005,"name":"Design Verification CCE2","child_ids":[],"parent_id":null}],"offices":[{"id":4049113005,"name":"Bengaluru","location":"India","child_ids":[],"parent_id":4052109005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4602437005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4391605005,"location":{"name":"Taipei, Taiwan"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Engineering Operations","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4602437005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"1917","title":"Lead HVM Product Engineer ","company_name":"Astera Labs","first_published":"2025-08-29T01:48:10-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Job Description:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As an Astera Labs HVM Product and Test Engineering, you will support existing products already in HVM (high volume manufacturing) at our Asia OSAT partners. Maintaining smooth manufacturing to ensure on-time customer shipments is one key objective. In this role, you will complement the New Product Introduction Product Engineers as products are released into production and own the engineering manufacturing during mass production. The ideal candidate possesses breadth of industry experience in high-speed product development in the field of product and/or test engineering, can apply fundamentals in circuit, ATE, and test program to aid problem solving, and is a self-driven, result focused go-getter in the pursuit of goals and objectives.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic qualifications:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Minimum of 5 years of experience in the field of post silicon product development dealing with high-speed XCVR (product, test or validation)\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Experience in product and package qualification\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Have gone through at least one cycle of full product development life cycle\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Strong academic/technical background in electrical or computer engineering; Bachelor’s is required; MS preferred\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Strong problem-solving skills that involve system level analysis with test hardware, test program and DUT.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Digital and analog circuit level understanding for DUT.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Excellent team player with great communication skills\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Professional attitude with the ability to prioritize a dynamic list of multiple tasks\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required experience:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Proven track record continuing seamless production of semiconductor products partnering with OSATs supporting high volume manufacturing through the complete product lifecycle\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Hands on experience with using the Advantest 93k ATE platform with specific skills updating ATE test programs for wafer sort and final test solutions\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Familiarity with JEDEC standard and hands on experience in product and package qualification, failure disposition, FIT rate calculation\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Detailed mindset monitoring device ATE test yields, ATE test time, device quality and rolling out new ATE test programs using consistent BKMs\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Strong data analysis skills using tools such as JMP or Spotfire calculating limits and drawing conclusions\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Energetic work mindset meeting the demands of shipping quality parts to Astera Labs’ customers through the manufacturing stage of development\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred experience:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Working with silicon validation teams to ensure device performance meets production requirements.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Firmware development in C/C++, scripting in Python, or other equivalent programming experience.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Hands-on knowledge of NRZ/PAM4 SerDes protocols like PCIe (Gen3 and above), Ethernet (25G and above), etc. and/or memory interfaces such as (LP)DDR5/4.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4009035005,"name":"Taipei","location":"Taiwan","child_ids":[],"parent_id":4002874005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4729060005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4452071005,"location":{"name":"Bengaluru, Karnataka, India"},"metadata":[{"id":12122734005,"name":"Country","value":"India","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Bengaluru","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Digital Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4729060005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":null,"title":"Lead Logic Design Engineer","company_name":"Astera Labs","first_published":"2026-09-10T04:35:10-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Lead Logic Design Engineer – UALink IP/Subsystem\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;6–10\u0026amp;nbsp;years\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Job Summary\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Lead RTL and microarchitecture development for\u0026amp;nbsp;UALink-based IP/subsystems, focusing on high-bandwidth, low-latency data movement and scalable interconnect design.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;27\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Lead\u0026amp;nbsp;UALink\u0026amp;nbsp;IP/subsystem RTL development.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;27\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Translate protocol requirements into detailed microarchitecture.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; 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data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;27\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Work on buffering, arbitration, flow control, ordering, and error handling.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;27\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Develop and review\u0026amp;nbsp;SystemVerilog\u0026amp;nbsp;RTL.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;27\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Drive performance, area, power, and latency optimization.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;27\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;7\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Collaborate with verification, SoC integration, and physical design teams.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; 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data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;27\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;9\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Review RTL and\u0026amp;nbsp;mentor\u0026amp;nbsp;engineers.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;27\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;10\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Support silicon debug and issue resolution.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Required Skills\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;28\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Strong RTL and microarchitecture experience.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; 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data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;29\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Direct\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;UALink\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026amp;nbsp;experience.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;29\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience with PCIe, CXL, CHI, CCIX, Ethernet, or similar technologies.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;29\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience with AI/accelerator or high-performance\u0026amp;nbsp;compute SoCs.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184256005,"name":"Design Engineering CCE2","child_ids":[],"parent_id":null}],"offices":[{"id":4049113005,"name":"Bengaluru","location":"India","child_ids":[],"parent_id":4052109005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4729059005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4452070005,"location":{"name":"Bengaluru, Karnataka, India"},"metadata":[{"id":12122734005,"name":"Country","value":"India","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Bengaluru","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Digital Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4729059005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":null,"title":"Lead Logic Design Engineer","company_name":"Astera Labs","first_published":"2026-09-17T08:29:22-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Lead Logic Design Engineer\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;6-10 years\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Job Summary\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;We are seeking a Lead \u0026lt;strong\u0026gt;Logic Design Engineer\u0026lt;/strong\u0026gt; with deep expertise in micro-architecture and RTL design to lead the development of complex IPs/subsystems. The candidate will provide technical ownership across architecture, microarchitecture, RTL implementation, integration, and silicon bring-up.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Lead RTL/microarchitecture development for \u0026lt;strong\u0026gt;complex connectivity IP/subsystems\u0026lt;/strong\u0026gt;.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Translate specifications and system requirements into robust hardware architecture.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Design high-performance and scalable logic for controllers/subsystems.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work across connectivity IP / subsystem layers including \u0026lt;strong\u0026gt;Transaction, Data Link, and Physical interface integration\u0026lt;/strong\u0026gt; as applicable to the role.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop and review RTL using \u0026lt;strong\u0026gt;SystemVerilog/Verilog\u0026lt;/strong\u0026gt;.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop robust mechanisms for \u0026lt;strong\u0026gt;flow control, ordering, buffering, arbitration, error handling, and reliability\u0026lt;/strong\u0026gt;.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive performance, latency, area, and power optimization.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with verification teams to develop verification strategies and debug complex failures.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work with SoC integration and physical design teams to ensure successful implementation.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead technical reviews and mentor senior engineers.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support post-silicon debug and root-cause analysis.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Skills\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Extensive experience in \u0026lt;strong\u0026gt;complex connectivity IPs such as PCIE, UALink, Ethernet, CXL, UCIe\u0026lt;/strong\u0026gt;.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong RTL design experience using \u0026lt;strong\u0026gt;SystemVerilog/Verilog\u0026lt;/strong\u0026gt;.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep knowledge of PCIe architecture and protocol.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of high-speed data paths, FIFOs, arbitration, flow control, and error handling.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with simulation, lint, CDC, synthesis, and timing considerations.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong debugging and problem-solving skills.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience of working in switching silicon.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience of working on entire cycle from concept to silicon production.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184256005,"name":"Design Engineering CCE2","child_ids":[],"parent_id":null}],"offices":[{"id":4049113005,"name":"Bengaluru","location":"India","child_ids":[],"parent_id":4052109005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4728527005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4451768005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Test Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4728527005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2026-197","title":"Manager, ATE Test Engineering","company_name":"Astera Labs","first_published":"2026-08-28T18:00:38-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is seeking a \u0026lt;strong\u0026gt;Manager, ATE Test Engineering \u0026lt;/strong\u0026gt;to lead our Test engineering organization in San Jose, CA. This is a critical leadership role responsible for driving next-generation high-speed, high-performance products from silicon bring-up through high-volume manufacturing in advanced process nodes.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is looking to build and scale the Test Engineering team responsible for developing scalable ATE solutions for complex mixed-signal silicon products and high-speed products that power next-generation AI infrastructure. You will shape test strategy, guide execution across wafer sort and final test, and ensure products move confidently from design through silicon bring-up and high-volume production.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This is an opportunity to combine technical depth with engineering leadership at a hyper-growth connectivity company. Your decisions will directly influence product quality, manufacturing readiness, and customer experience. You will partner across design, DFT, product engineering, operations, and manufacturing to improve coverage, quality, cost, and test time as Astera Labs scales purpose-built connectivity for rack-scale AI systems.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Team Leadership \u0026amp;amp; Organization Building\u0026lt;/strong\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Build, mentor, and lead a high-performing team of ATE Test engineers owning a diverse portfolio of connectivity products purpose-built for AI infrastructure\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Establish scalable processes, best-known methods (BKMs), and operational excellence frameworks as the organization grows\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Make sound technical and organizational decisions in a fast-paced, dynamic environment with competing priorities\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Test Strategy and Product Ownership\u0026lt;/strong\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Define end-to-end ATE test strategies and plans for high-speed connectivity products from design engagement through high-volume production.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Establish coverage, quality, test-time, cost, and yield objectives, and drive measurable improvements across the product lifecycle.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead silicon and ATE bring-up, bench-to-ATE correlation, production release, and ongoing test optimization.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;ATE Hardware, Software, and Silicon Validation\u0026lt;/strong\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Guide to tester platform selection and development of load boards, interface hardware, and test solutions for wafer sort and final test.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Direct ATE program development, pattern implementation, debug, and resource optimization on Advantest 93k or Teradyne platforms.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive characterization and production test of high-speed SerDes and mixed-signal interfaces, including PCIe, Ethernet, DDR, NVMe, and USB.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Partner with DFT and design teams to implement SCAN, MBIST, SerDes, and functional test methods that maximize defect and parametric coverage.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional Leadership and Manufacturing Execution\u0026lt;/strong\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Build alignment with design, DFT, product engineering, operations, and external manufacturing partners on readiness, risk, and release decisions.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop technical talent, set priorities, and create a culture of ownership, rigorous execution, and continuous improvement.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Use data from production, lab equipment, protocol analyzers, oscilloscopes, and manufacturing systems to resolve issues and improve product quality.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor\u0026#39;s degree in electrical engineering or related technical field.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;8+ years of experience developing and supporting ATE test solutions for complex High-speed products or SoC products.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;3+ years of managerial experience building and leading Test engineering team\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Working knowledge of high-speed protocols and physical-layer behavior, including PCIe, Ethernet, DDR, NVMe, or USB.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with ATE program development, silicon bring-up, bench-to-ATE correlation, production debug, and test-time optimization.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ability to communicate clearly, manage competing priorities, and partner effectively across technical and manufacturing organizations.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Master’s or PhD in Electrical Engineering or related field.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience leading wafer-sort and final-test hardware development, including high-speed load-board design.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong knowledge of DFT techniques such as SCAN, MBIST, SerDes, and functional test, plus control interfaces including I2C, I3C, SPI, MDIO, and JTAG.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience testing high-speed SerDes operating at 16 Gbps or higher, including external loopback at wafer sort.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency in C/C++ or Python for ATE programming, data processing, and automation; familiarity with modern databases and RF testing on ATE platforms.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Demonstrated ability to develop engineers, influence cross-functional decisions, and deliver results in a fast-paced, high-growth environment.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Salary range is $195,000 to $250,000 depending on experience, level, and business need. This role may be eligible for discretionary bonuses, incentives and benefits.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184355005,"name":"Test Engineering","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4729033005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4452058005,"location":{"name":"Tel Aviv-Yafo, Tel Aviv District, Israel"},"metadata":[{"id":12122734005,"name":"Country","value":"Israel","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Tel Aviv","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Design Verification","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4729033005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":null,"title":"Manager Design Verification ","company_name":"Astera Labs","first_published":"2026-09-14T10:20:28-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p8i6j01 paragraph\u0026quot;\u0026gt;Astera Labs is hiring a \u0026lt;strong\u0026gt;Manager Design Engineer\u0026lt;/strong\u0026gt; to help architect and deliver the connectivity silicon powering the world\u0026#39;s largest AI clusters. You\u0026#39;ll own design execution on complex blocks across our purpose-built products, working at the cutting edge of PCIe, CXL, Ethernet, and emerging rack-scale interconnect technologies.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p8i6j01 paragraph\u0026quot;\u0026gt;This is a high-impact technical role at a hyper-growth company. You\u0026#39;ll partner closely with architecture, verification, DFT, and physical design teams to take features from spec to silicon, while contributing to the design methodology that scales with our roadmap. If you want to ship silicon that defines AI infrastructure, this is the team.\u0026lt;/p\u0026gt;\n\u0026lt;h3 class=\u0026quot;_9k2iva0 p8i6j0c _1ibi0s314 heading3 _9k2iva1\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/h3\u0026gt;\n\u0026lt;ul class=\u0026quot;p8i6j07 p8i6j02\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;p8i6j0a\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;RTL Design \u0026amp;amp; Implementation\u0026lt;/strong\u0026gt;\n\u0026lt;ul class=\u0026quot;p8i6j08 p8i6j02\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;p8i6j0a\u0026quot;\u0026gt;Own RTL design for assigned blocks from microarchitecture through synthesis sign-off\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;p8i6j0a\u0026quot;\u0026gt;Develop high-quality, synthesizable Verilog/SystemVerilog with strong attention to PPA\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;p8i6j0a\u0026quot;\u0026gt;Drive design reviews, lint, CDC, and timing closure activities to silicon-ready quality\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;p8i6j0a\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional Execution\u0026lt;/strong\u0026gt;\n\u0026lt;ul class=\u0026quot;p8i6j08 p8i6j02\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;p8i6j0a\u0026quot;\u0026gt;Partner with architecture to translate specifications into implementation-ready microarchitecture\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;p8i6j0a\u0026quot;\u0026gt;Collaborate with verification on testplans, coverage closure, and bug triage\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;p8i6j0a\u0026quot;\u0026gt;Work with DFT and physical design teams on scan, BIST, floorplanning, and timing closure\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;p8i6j0a\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Technical Leadership \u0026amp;amp; Quality\u0026lt;/strong\u0026gt;\n\u0026lt;ul class=\u0026quot;p8i6j08 p8i6j02\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;p8i6j0a\u0026quot;\u0026gt;Mentor junior engineers and contribute to design methodology, scripts, and best practices\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;p8i6j0a\u0026quot;\u0026gt;Debug complex pre-silicon and post-silicon issues across RTL, gate-level, and emulation environments\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;p8i6j0a\u0026quot;\u0026gt;Drive structured, data-driven design decisions in support of aggressive tapeout schedules\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h3 class=\u0026quot;_9k2iva0 p8i6j0c _1ibi0s314 heading3 _9k2iva1\u0026quot;\u0026gt;Basic Qualifications\u0026lt;/h3\u0026gt;\n\u0026lt;ul class=\u0026quot;p8i6j07 p8i6j02\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;p8i6j0a\u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, Computer Engineering, or related field\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;p8i6j0a\u0026quot;\u0026gt;5+ years of digital design experience, including at least one full chip from spec to tapeout\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;p8i6j0a\u0026quot;\u0026gt;Strong proficiency in Verilog/SystemVerilog, RTL coding, and synthesis flows\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;p8i6j0a\u0026quot;\u0026gt;Hands-on experience with timing closure, CDC, lint, and low-power design techniques\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;p8i6j0a\u0026quot;\u0026gt;Solid understanding of high-speed serial interfaces (PCIe, Ethernet, or similar) and SoC integration\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h3 class=\u0026quot;_9k2iva0 p8i6j0c _1ibi0s314 heading3 _9k2iva1\u0026quot;\u0026gt;Preferred Qualifications\u0026lt;/h3\u0026gt;\n\u0026lt;ul class=\u0026quot;p8i6j07 p8i6j02\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;p8i6j0a\u0026quot;\u0026gt;MS or PhD in Electrical Engineering or Computer Engineering\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;p8i6j0a\u0026quot;\u0026gt;Experience with PCIe Gen5/Gen6, CXL, UALink, UCIe, or Ethernet MAC/PCS designs\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;p8i6j0a\u0026quot;\u0026gt;Familiarity with formal verification, emulation, or assertion-based methodologies\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;p8i6j0a\u0026quot;\u0026gt;Background in advanced process nodes (7nm, 5nm, or below)\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;p8i6j0a\u0026quot;\u0026gt;Strong debug skills across pre-silicon and post-silicon environments\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p class=\u0026quot;p8i6j01 paragraph\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184260005,"name":"Design Verification CCE2","child_ids":[],"parent_id":null}],"offices":[{"id":4056876005,"name":"Tel Aviv","location":"Israel","child_ids":[],"parent_id":4008937005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4678037005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4427158005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Dallas","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Engineering Operations","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4678037005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2414","title":"Manager, Package Design Engineering","company_name":"Astera Labs","first_published":"2026-03-26T17:39:13-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is seeking a Manager, Package Design Engineering to lead and scale our Package Design team in San Jose. In this high-impact role, you\u0026#39;ll own the end-to-end delivery of advanced IC packaging solutions—from early architecture definition through production ramp—enabling the next generation of AI infrastructure and connectivity products.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As the semiconductor industry races toward chiplet-based architectures, 2.5D/3D integration, and ever-increasing bandwidth demands, packaging has become a critical differentiator. You\u0026#39;ll build and mentor a high-performing team while driving cross-functional execution with silicon architecture, SIPI, PCB, validation, manufacturing, and external partners including substrate vendors and OSATs. Your work will directly impact Astera Labs\u0026#39; ability to deliver industry-leading PCIe, CXL, and Ethernet connectivity solutions to the world\u0026#39;s most demanding hyperscale and AI customers.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This role offers the opportunity to shape design methodology, establish scalable standards, and enable chip-package-board co-design frameworks across multiple product lines in a fast-moving, innovation-driven environment.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Team Leadership \u0026amp;amp; Execution\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Build, mentor, and scale a high-performing package design engineering team with clear ownership, accountability, and execution flows\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Establish design templates, standards, and best-known methods (BKMs) across multiple concurrent programs\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead design reviews, audits, and issue resolution through bring-up and production ramp\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Package Design Delivery\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Own end-to-end package design execution including FCBGA/FCCSP, monolithic, multi-die, and chiplet-based designs from concept feasibility through tape-out and production\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Define and review substrate stack-ups, pad stacks, routing strategies, and design constraints to meet electrical, thermal, mechanical, and manufacturability requirements\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive technical tradeoffs across performance, cost, yield, and schedule, ensuring high-quality design closure and on-time delivery\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Cross-Functional Collaboration\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Partner with SIPI, silicon architecture, system/board design, and product teams to drive chip-package-board co-design and resolve system-level challenges\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with OSATs and substrate vendors to ensure design feasibility, manufacturability, and alignment with evolving design rules and technology roadmaps\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support adoption of advanced packaging technologies such as 2.5D, chiplet, CPO/CPC, and heterogeneous integration platforms\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Methodology \u0026amp;amp; Automation\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Develop and scale design methodologies and automation flows to improve efficiency, quality, and repeatability across the organization\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, Materials Science, or related field\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;10+ years of progressive experience in IC package design using tools such as Cadence Allegro APD/SiP\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;5+ years of leadership experience managing teams or technical organizations in IC packaging environments\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong hands-on expertise in end-to-end package design with proven delivery of HVM-ready FCBGA/FCCSP packages using Cadence APD tool\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with high-speed SerDes systems (PCIe Gen5/6/7, CXL, Ethernet 100G/200G/400G+) and advanced nodes (7nm, 5nm, 3nm)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep understanding of substrate technologies, stack-ups, routing constraints, assembly processes, and SI/PI fundamentals\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven experience working with OSATs and substrate vendors through development and production ramp\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience working with OSATs and substrate vendors through development and production ramp\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with advanced packaging architectures such as 2.5D/3D, chiplet, or heterogeneous integration\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Master\u0026#39;s degree in Electrical Engineering or related field\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with advanced packaging architectures such as 2.5D/3D, chiplet, or heterogeneous integration\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience implementing automation, scripting (Python, SKILL, Tcl), or workflow optimization\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Background in early package feasibility, platform evaluation, and technology roadmap development\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with chip floor planning, architecture, and system-level tradeoffs\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Exposure to SIPI modeling and analysis, thermal, and mechanical performance considerations\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;The base salary range is $230,000 USD – $265,000 USD. This position can be hired as a Manager Level or Director Level. Your base salary will be determined based on location, experience, and employees\u0026#39; pay in similar positions.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4586713005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4383619005,"location":{"name":"Multiple Locations"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Human Resources","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4586713005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"1833","title":"Open Application - Join Our Talent Network! ","company_name":"Astera Labs","first_published":"2025-07-15T17:15:27-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;h3\u0026gt;\u0026lt;strong\u0026gt;Why Apply Now?\u0026lt;/strong\u0026gt;\u0026lt;/h3\u0026gt;\n\u0026lt;p\u0026gt;Even if there’s no active posting for your expertise, we’re always on the lookout for exceptional talent to join our future product and team innovations. We are considering resume of all levels.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Early connection: Be on our radar for upcoming openings that match your skills\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Show your passion: Tell us how you can contribute to enterprise‑scale AI connectivity\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Stay informed: Receive priority updates on relevant job opportunities at Astera Labs\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h3\u0026gt;\u0026lt;strong\u0026gt;Who We Want to Meet\u0026lt;/strong\u0026gt;\u0026lt;/h3\u0026gt;\n\u0026lt;p\u0026gt;We welcome professionals across disciplines, including but not limited to:\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Hardware Engineering (ASIC, mixed‑signal, PCB)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Firmware \u0026amp;amp; Embedded Systems (CXL, PCIe, DDR)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Software \u0026amp;amp; Validation (Firmware QA, system validation, diagnostic SW)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Product \u0026amp;amp; Program Management\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Operations \u0026amp;amp; HR\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Sales, Customer Programs, and Field Applications\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs champions diversity in technical expertise and career stages from senior engineers and managers to internship candidates across all functions.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4141519005,"name":"Open Application","child_ids":[],"parent_id":null}],"offices":[{"id":4019546005,"name":"United States","location":null,"child_ids":[4019545005,4050370005,4055745005,4000118005,4017614005,4065362005,4000148005],"parent_id":null}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4645300005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4412063005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"India","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Bangalore","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":"Signal Connectivity Group","value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Optical Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4645300005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2185","title":"Optical / Photonics Validation Engineering, Senior Director","company_name":"Astera Labs","first_published":"2026-07-31T16:21:29-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;div class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-olk-copy-source=\u0026quot;MessageBody\u0026quot;\u0026gt;Job Title: Optical Photonics Validation Leader\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;h2\u0026gt;Overview\u0026lt;/h2\u0026gt;\n\u0026lt;p class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;We are looking for an Optical Validation Engineering, Senior Director to drive the characterization, validation, and qualification of near-packaged optics (NPO) and co-packaged optics (CPO) systems. In this role, you will define and implement the validation approach that ensures the optical, electrical, and thermal performance of advanced photonic interconnects used in next-generation data center and networking platforms.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;You will work at the intersection of silicon photonics, packaging, electrical design, and systems engineering to ensure robust product performance from prototype to production.\u0026lt;/p\u0026gt;\n\u0026lt;h2\u0026gt;Key Responsibilities\u0026lt;/h2\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;Lead a team that owns the optical validation strategy and roadmap for optical connectivity products.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Develop and execute comprehensive validation and test plans covering optical coupling, insertion loss, signal integrity, thermal stability, and reliability metrics.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Define optical test methodologies for complex integrated systems involving photonic, electrical, and mechanical interfaces.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Collaborate with design, packaging, and system architecture teams to translate product specifications into measurable validation criteria.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Establish automated test frameworks for high-throughput optical and electrical validation (instrument control, data analysis, and reporting).\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Analyze measurement data to identify performance trends, failure modes, and root causes.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Lead design-of-experiments (DOE) initiatives to optimize system performance and yield.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Interface with manufacturing, reliability, and quality teams to ensure seamless transition to volume production and long-term reliability.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Mentor junior engineers and promote best practices in optical validation and measurement science.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h2\u0026gt;Qualifications\u0026lt;/h2\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;M.S. or Ph.D. in Optical Engineering, Electrical Engineering, Applied Physics, or equivalent field.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;8+ years of experience in optical module testing, photonic component validation, or high-speed interconnect qualification.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Deep understanding of optical measurements (IL, RL, BER, eye diagrams, mode coupling), optical alignment, and signal characterization.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Hands-on experience with optical instrumentation (optical spectrum analyzers, BERTs, network analyzers, power meters, interferometers).\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Strong background in data analysis, automation scripting (Python, LabVIEW, MATLAB), and statistical validation methods.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Familiarity with packaging-related optical performance dependencies (thermo-mechanical stress, optical coupling efficiency, etc.).\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Excellent collaboration and communication skills, with a proven ability to align across multidisciplinary hardware teams.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h2\u0026gt;Preferred Experience\u0026lt;/h2\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Experience with co-packaged optics, silicon photonics assemblies, and near-packaged optical interfaces.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Knowledge of industry standards and compliance testing (IEEE 802.3, OIF, or custom CPO protocols).\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Understanding of reliability qualification (HTOL, TC, mechanical shock/vibration for optical components).\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Familiarity with system-level validation for networking and hyperscale data center environments.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Base salary range is $260,000 to $295,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;/div\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184399005,"name":"Signal Connectivity Group","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4740323005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4457668005,"location":{"name":"Tel Aviv-Yafo, Tel Aviv District, Israel"},"metadata":[{"id":12122734005,"name":"Country","value":"Israel","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Tel Aviv","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Firmware/Software Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4740323005,"updated_at":"2026-10-05T05:38:38-04:00","requisition_id":null,"title":"PCIe Firmware Expert","company_name":"Astera Labs","first_published":"2026-10-05T05:38:38-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;h2 class=\u0026quot;wnfdntj wnfdnti _1ibi0s35e _1ibi0s36a\u0026quot; data-pm-slice=\u0026quot;1 1 []\u0026quot;\u0026gt;The Role and Its Impact\u0026lt;/h2\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntw _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Our firmware team develops the embedded firmware that brings Astera Labs\u0026#39; compute connectivity silicon to life, from boot and initialization through link management, telemetry, error handling, and diagnostics. This firmware runs on the embedded processors inside our chips and ships in data centers powering AI infrastructure around the world. Beyond the firmware, the team also develops the COSMOS SDK, the software layer customers and internal teams use to configure, monitor, update, and debug our devices in their systems.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntw _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;We are looking for an experienced firmware engineer and PCIe expert who enjoys working close to the hardware, owns features end to end, and has a proven track record of developing and debugging firmware both pre-silicon and post-silicon. You know PCIe in depth, from link training and enumeration to error handling and recovery, and you\u0026#39;re the person others turn to when a PCIe link or device misbehaves. You understand the whole system, not just the chip: how our devices behave inside customer platforms, and how a customer requirement turns into firmware and SDK. You\u0026#39;ll work alongside architects, design and verification engineers, validation teams, and our global firmware teams to take new products from early pre-silicon development through bring-up and into customer deployment.\u0026lt;/p\u0026gt;\n\u0026lt;h2 class=\u0026quot;wnfdntj wnfdnti _1ibi0s35e _1ibi0s36a\u0026quot;\u0026gt;What You\u0026#39;ll Be Doing\u0026lt;/h2\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdntf\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntw _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Having fun! by being part of a very strong and cohesive group.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntw _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Design and develop real-time embedded firmware in C, including low-level drivers and control logic for complex hardware blocks\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntw _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Own PCIe firmware features end to end: link training, enumeration, error handling, and recovery\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntw _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Develop and debug firmware pre-silicon (emulation) and lead post-silicon bring-up and debug in the lab\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntw _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Debug complex PCIe and system-level issues with architecture, design, validation, and customer teams\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntw _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Develop and extend the company SDK in step with firmware features\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntw _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Support customer requests and adjust firmware and SDK development to meet their needs\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h2 class=\u0026quot;wnfdntj wnfdnti _1ibi0s35e _1ibi0s36a\u0026quot;\u0026gt;What We\u0026#39;re Looking For\u0026lt;/h2\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntw _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Required:\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdntf\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntw _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;BSc/MSc in Computer Science, Electrical Engineering, Computer Engineering, or a related field\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntw _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;10+ years of hands-on experience as a firmware engineer\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntw _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Proven experience in embedded and real-time firmware development\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntw _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Strong programming skills in C on resource-constrained, bare-metal, or RTOS-based systems\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntw _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Solid understanding of processor architecture, memory-mapped registers, interrupts, and HW/SW interaction\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntw _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Expert-level knowledge of PCIe: LTSSM and link training, enumeration, configuration space, error handling (AER), and reset and recovery flows\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntw _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Experience with PCIe protocol analyzers and exercisers (e.g., Teledyne LeCroy, Keysight)\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntw _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Proven hands-on experience in both pre-silicon and post-silicon firmware development and debugging, including silicon bring-up of new SoCs\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntw _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Strong debugging skills on real hardware using JTAG debuggers, logs, and register-level analysis\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntw _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Broad system-level understanding of how silicon, firmware, SDK, host software, and platform interact, with the ability to turn customer requirements into technical solutions\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntw _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;A team player with excellent communication skills who works well in a collaborative, cross-site environment\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntw _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Comfort with ambiguity and ownership in a fast-moving, high-growth company\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h2 class=\u0026quot;wnfdntj wnfdnti _1ibi0s35e _1ibi0s36a\u0026quot;\u0026gt;Location\u0026lt;/h2\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntw _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;This position is based in our Tel Aviv, Israel office.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184367005,"name":"Firmware \u0026 Software CCE2","child_ids":[],"parent_id":null}],"offices":[{"id":4052111005,"name":"Haifa","location":"Israel","child_ids":[],"parent_id":4008937005},{"id":4056876005,"name":"Tel Aviv","location":"Israel","child_ids":[],"parent_id":4008937005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4718443005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4446638005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"CTO Organization","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4718443005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":null,"title":"Performance Engineer","company_name":"Astera Labs","first_published":"2026-07-24T14:35:14-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 1\u0026quot;\u0026gt;Senior Performance Engineer\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:322,\u0026amp;quot;335559739\u0026amp;quot;:322}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Location:\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026amp;nbsp;San Jose, CA (On-site)\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:240,\u0026amp;quot;335559739\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 2\u0026quot;\u0026gt;Role Overview\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:299,\u0026amp;quot;335559739\u0026amp;quot;:299}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Astera Labs is a hyper-growth connectivity company enabling the rack-scale AI infrastructure powering the world\u0026#39;s most advanced GPU clusters. Our Scorpio scale-up fabric switches are purpose-built to unlock the performance of next-generation AI workloads, and we\u0026#39;re looking for a Senior Performance Engineer to demonstrate the real-world value of our silicon where it matters most: on real inference and training workloads running on GPUs at scale.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:240,\u0026amp;quot;335559739\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;In this role, you will define how the world measures scale-up fabric performance. You\u0026#39;ll build the roofline models, benchmarks, and end-to-end workload studies that quantify our performance leadership, expose bottlenecks, and drive performance fine-tuning of real AI workloads on our fabric to inform product direction. Your data will directly shape architecture, firmware, and product decisions — and fuel the marketing narrative that positions Astera Labs at the center of AI connectivity.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:240,\u0026amp;quot;335559739\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 2\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:299,\u0026amp;quot;335559739\u0026amp;quot;:299}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:0,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Performance Characterization \u0026amp;amp; Benchmarking\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:1,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Establish theoretical and measured roofline models for Astera Labs\u0026#39; scale-up fabric across key performance metrics, defining the reference for all comparative testing.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:1,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Build and maintain baseline performance benchmarks using industry-standard tools such as NVBandwidth and NCCL across a range of GPU configurations and switch topologies.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:1,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Quantify the impact of differentiated Astera Labs AI fabric features (e.g., Hypercast, In-Network Computing) against baselines using both synthetic benchmarks and real inference workloads.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:0,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Real Workload Analysis \u0026amp;amp; Fabric Scalability\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:1,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Run end-to-end inference model workloads on target hardware to capture real-world performance beyond synthetic benchmarks, supporting architecture decisions and customer-facing demonstrations.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:1,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Evaluate fabric performance as inference cluster size scales from 16 to 32 GPUs and beyond, identifying bottlenecks and building performance scaling models for state-of-the-art AI workloads.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:1,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Design and execute head-to-head performance comparisons against competing fabric switch solutions to produce data-driven differentiation evidence.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:0,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Test Infrastructure \u0026amp;amp; Automation\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:1,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Design, build, and maintain automated lab infrastructure including test execution pipelines, traffic generation tooling, and data collection and reporting systems.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:1,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Enable repeatable, high-quality, and scalable performance measurements across all hardware configurations, reducing manual effort and accelerating the test cycle.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:1,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Share infrastructure and playbooks with the Product Applications team to accelerate customer application development and issue resolution.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:0,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Cross-Functional Impact \u0026amp;amp; Innovation\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:1,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Partner closely with ASIC architecture, firmware, software, Product Definition, Product Applications, and Product Marketing teams to communicate findings, influence design decisions, and resolve performance-impacting issues.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:1,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Serve as a key technical resource in the early evaluation of new fabric architectures, interconnect technologies (UALink, PCIe Gen 6/Gen 7, Ethernet, UEC), and AI/ML communication paradigms.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:1,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Provide performance data, analysis, and live benchmark support for key customer engagements and industry events; produce clear, audience-appropriate performance reports, technical briefs, and marketing collateral, and maintain living documentation in Confluence.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 2\u0026quot;\u0026gt;Basic Qualifications\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:299,\u0026amp;quot;335559739\u0026amp;quot;:299}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;8\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:0,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Computer Engineering, Computer Science, Electrical Engineering, or a related technical field. We welcome both recent graduates with strong, directly relevant project, research, or internship experience and candidates with 2–5 years of industry experience in performance or systems engineering.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;8\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:0,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Hands-on experience running AI/ML workloads on GPU clusters — including benchmarking, performance analysis, and fine-tuning of workloads across clusters of GPUs or accelerators. This can come from industry, research, or substantial academic projects.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;8\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:0,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Demonstrated ability to debug and root-cause system-level performance issues across hardware, firmware, software, and network boundaries.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;8\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:0,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Excellent fundamental knowledge of compute algorithms, parallel algorithms, and AI/ML algorithms and workloads.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;8\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:0,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Strong working knowledge of computer systems, GPU systems, and datacenter networking — including PCIe and Ethernet fundamentals.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;8\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:0,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Working knowledge of GPU and CPU software stacks (e.g., CUDA, MPI, collective communication libraries, drivers, and OS-level performance tooling).\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;8\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:0,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;7\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Proficiency in scripting and automation (e.g., Python) to build test pipelines and analyze large performance datasets.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 2\u0026quot;\u0026gt;Preferred Qualifications\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:299,\u0026amp;quot;335559739\u0026amp;quot;:299}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;9\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:0,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;MS or PhD in Computer Engineering, Computer Science, Electrical Engineering, or a related field.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;9\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:0,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience with scale-up fabrics and next-generation interconnects such as UALink, PCIe Gen 6/Gen 7, Ethernet, or UEC.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;9\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:0,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Deep understanding of modern inference and training workloads (LLMs, MoE, recommender systems) and their communication patterns.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;9\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:0,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience developing roofline models and competitive performance analyses for switching, networking, or accelerator silicon.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;9\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:0,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Excellent written and verbal communication skills, with the ability to translate deep technical findings into concise executive summaries and customer-facing narratives.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Salary range is $135,000 to $170,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:240,\u0026amp;quot;335559739\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184226005,"name":"CTO Office","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4686914005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4431415005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose (HQ)","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Physical Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4686914005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2470","title":"Physical Design Engineering, VP","company_name":"Astera Labs","first_published":"2026-07-27T14:11:38-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Astera Labs is seeking a VP\u0026lt;strong\u0026gt;\u0026amp;nbsp;of Physical Design \u0026lt;/strong\u0026gt;to lead our critical full-chip physical design efforts for next-generation switching products featuring UCIe and UALink technologies. This strategic leadership role will drive the physical implementation of highly complex, multi-die chiplet architectures that are essential to enabling rack-scale AI infrastructure. As VP, you will scale and mentor a growing team of physical design engineers while establishing the methodologies and flows required to deliver multiple high-performance tapeouts in advanced process nodes.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;This role sits at the intersection of\u0026amp;nbsp;cutting-edge\u0026amp;nbsp;connectivity technology and semiconductor execution excellence. You will partner closely with architecture, digital design, packaging, and silicon engineering teams to ensure our switching solutions meet the aggressive performance, power, and area targets demanded by hyperscale AI data centers. Your\u0026amp;nbsp;expertise\u0026amp;nbsp;in interposer design, die-to-die interfaces, advanced packaging, and timing closure will be critical as Astera Labs continues to push the boundaries of AI connectivity with PCIe Gen 6/7 and\u0026amp;nbsp;UALink\u0026amp;nbsp;technologies.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Strategic Physical Design Leadership\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Lead end-to-end physical design execution for complex multi-die switching products with UCIe and\u0026amp;nbsp;UALink\u0026amp;nbsp;connectivity\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Drive chip-level\u0026amp;nbsp;floorplanning, power planning, placement, routing, and timing closure for advanced node designs\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Establish physical design methodologies and best practices for interposer-based\u0026amp;nbsp;chiplet\u0026amp;nbsp;architectures and die-to-die interfaces\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Own physical design quality metrics including timing, power, area, and manufacturability across multiple concurrent projects\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Team Building \u0026amp;amp; Leadership\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Scale and develop a world-class physical design organization to support aggressive product roadmap\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Manage and mentor Directors, Managers, and senior engineers across the physical design team\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Foster a culture of technical excellence, innovation, and collaboration\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Partner with HR and recruiting to attract top physical design talent\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Cross-Functional Collaboration \u0026amp;amp; Execution\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Partner with architecture and digital design teams to influence RTL for physical implementation success\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Collaborate with packaging engineering on advanced 2.5D/3D integration strategies and interposer design\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Work closely with silicon engineering and DFT teams to ensure robust designs through\u0026amp;nbsp;tapeout\u0026amp;nbsp;and bring-up\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Drive resolution of critical timing, power, and signal integrity challenges in high-speed SerDes and switching fabrics\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Basic Qualifications\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, Computer Engineering, or related field\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;15+ years of experience in physical design and implementation of complex SoCs or ASICs\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Proven\u0026amp;nbsp;track record\u0026amp;nbsp;leading physical design teams and delivering multiple successful\u0026amp;nbsp;tapeouts\u0026amp;nbsp;in advanced process nodes (7nm or below)\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Deep\u0026amp;nbsp;expertise\u0026amp;nbsp;in\u0026amp;nbsp;chiplet\u0026amp;nbsp;architectures, interposer design, and die-to-die interface implementation\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Strong understanding of advanced packaging technologies including 2.5D and 3D integration\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Expert-level knowledge of physical design flows, timing closure, power optimization, and signoff methodologies\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience managing and scaling engineering teams of 20+ people\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Preferred Qualifications\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Master\u0026#39;s degree or PhD in Electrical Engineering or related field\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience with UCIe, PCIe Gen 6/7, or other high-speed SerDes physical implementation\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Background in AI/ML infrastructure, networking ASICs, or high-performance switching products\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Deep\u0026amp;nbsp;expertise\u0026amp;nbsp;with Cadence and/or Synopsys physical design tools and flows\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience with advanced DFT integration and design for manufacturability (DFM)\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Track record\u0026amp;nbsp;of innovation in physical design methodologies and automation\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Strong leadership and communication skills with ability to influence across organizations\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Salary range is $250,600 to $375,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4701792005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4438671005,"location":{"name":"Tel Aviv-Yafo, Tel Aviv District, Israel"},"metadata":[{"id":12122734005,"name":"Country","value":"Israel","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Tel Aviv","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":"Compute Connectivity Engineering 2","value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Physical Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Internship","value_type":"single_select"}],"id":4701792005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2607","title":"Physical Design Student","company_name":"Astera Labs","first_published":"2026-06-02T13:34:52-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is establishing a strategic R\u0026amp;amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical \u0026#39;data bottlenecks\u0026#39; enabling the future of AI at scale. As we expand our presence in Israel, we are seeking a motivated\u0026amp;nbsp;\u0026lt;strong data-path-to-node=\u0026quot;8\u0026quot; data-index-in-node=\u0026quot;260\u0026quot;\u0026gt;Physical Design Student\u0026lt;/strong\u0026gt;\u0026amp;nbsp;to join our founding local engineering team.\u0026lt;/p\u0026gt;\n\u0026lt;p data-path-to-node=\u0026quot;9\u0026quot;\u0026gt;This is a unique opportunity to kickstart your career in the semiconductor industry. Working alongside senior industry veterans, you will gain hands-on experience in backend execution and advanced methodologies for cutting-edge chips that power the world\u0026#39;s largest AI clusters. If you are passionate about silicon hardware, eager to learn, and thrive on solving complex engineering challenges, this role offers the perfect bridge between your academic studies and a high-impact career.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p data-path-to-node=\u0026quot;10\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;h4 data-path-to-node=\u0026quot;11\u0026quot;\u0026gt;Guided Implementation \u0026amp;amp; Learning\u0026lt;/h4\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;12,0,0\u0026quot;\u0026gt;Partner with and learn from senior engineers to support the physical implementation journey, including synthesis, floorplanning, Place \u0026amp;amp; Route (P\u0026amp;amp;R), and Clock-Tree Synthesis (CTS)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;12,1,0\u0026quot;\u0026gt;Assist in macro-level implementation and develop hands-on skills in complex layout routing\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;12,2,0\u0026quot;\u0026gt;Participate in deep-submicron process challenges under close professional mentorship\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Signoff \u0026amp;amp; Design Integrity Support\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;14,0,0\u0026quot;\u0026gt;Assist in running engineering checks for design integrity, including Static Timing Analysis (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;14,1,0\u0026quot;\u0026gt;Learn to apply Logic Equivalence Checking (LEC) to help guarantee design correctness\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;14,2,0\u0026quot;\u0026gt;Gain exposure to the rigorous flows required to ensure first-pass silicon success\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Scripting \u0026amp;amp; Cross-Functional Collaboration\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;16,0,0\u0026quot;\u0026gt;Leverage and develop scripting tools to automate repetitive tasks and optimize the engineering environment\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;16,1,0\u0026quot;\u0026gt;Collaborate with Architecture, Design, and DFT teams to understand how different chip design disciplines intersect\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;16,2,0\u0026quot;\u0026gt;Actively participate in team reviews and technical discussions to ramp up backend methodologies\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p data-path-to-node=\u0026quot;18,0,0\u0026quot;\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Pursuing a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;18,1,0\u0026quot;\u0026gt;Strong academic foundation in digital systems, VLSI design, or semiconductor devices.\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;18,1,0\u0026quot;\u0026gt;Familiarity with Python, TCL, Bash, or Perl.\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;18,1,0\u0026quot;\u0026gt;Ability to work at least 2 days per week at our Haifa/Tel Aviv Center\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;18,1,0\u0026quot;\u0026gt;A \u0026quot;can-do\u0026quot; attitude with a passion for solving complex technical challenges\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;18,1,0\u0026quot;\u0026gt;Fluent in Hebrew and English with the ability to work effectively in a team environment\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026amp;nbsp;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p data-path-to-node=\u0026quot;18,2,0\u0026quot;\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Prior experience from a previous VLSI/Hardware student position or a significant academic project in physical design/VLSI\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;20,1,0\u0026quot;\u0026gt;Hands-on university lab experience with industry-standard EDA tools (e.g., Synopsys Fusion Compiler/ICC2, Cadence Innovus)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;20,2,0\u0026quot;\u0026gt;Understanding of basic verification concepts (STA, DRC, LVS)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;20,3,0\u0026quot;\u0026gt;Fast learner with a proactive attitude and a passion for deep-tech hardware infrastructure\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4056876005,"name":"Tel Aviv","location":"Israel","child_ids":[],"parent_id":4008937005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4737682005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4456294005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Quality Assurance Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4737682005,"updated_at":"2026-10-06T12:47:14-04:00","requisition_id":"2026-182","title":"PLM Change Analyst  ","company_name":"Astera Labs","first_published":"2026-10-06T12:20:00-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 1\u0026quot;\u0026gt;Position Summary\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335559738\u0026amp;quot;:480,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Astera Labs is seeking a hands-on PLM Analyst to own the day-to-day administration, configuration, and continuous improvement of Arena Product Lifecycle Management (PLM).\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559739\u0026amp;quot;:100}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;This role will be the internal subject-matter expert for Arena configuration and governance. The PLM Analyst will configure workflows, forms, fields, permissions, lifecycle states, notifications, and reports; manage product and Quality data; and ensure that engineering, manufacturing, Quality, and operations teams can execute controlled processes in one connected system.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559739\u0026amp;quot;:100}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;The ideal candidate combines strong Arena platform expertise with practical knowledge of product data management, engineering change control, document control, CAPA, nonconformance/MRB, audits, and Quality records. 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data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Serve as the primary administrator and functional owner for Arena PLM.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; 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data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;8\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Configure and administer Engineering Change Orders (ECOs), Engineering Change Requests (ECRs), release workflows, effectivity controls, and implementation tracking.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;9\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Support New Product Introduction (NPI) readiness \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;through part setup, BOM validation, document release, configuration checks, and product-data completeness reviews.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;10\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Maintain revision control, lifecycle states, product configurations, approved manufacturer information, and other product data needed for \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;semiconductor\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;, hardware, and optical products.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;11\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Drive PLM data cleanup, migration, standardization, and ongoing data-\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Quality\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt; improvement.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;12\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Ensure product changes are accurately reflected in connected \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Quality\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt; records and downstream ERP processes.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 2\u0026quot;\u0026gt;Business Partnership and Enablement\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335559738\u0026amp;quot;:200,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;13\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Serve as the primary liaison between engineering, manufacturing, \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Quality\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;, operations, supply chain, and IT for Arena requirements and process improvements.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;14\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Lead requirements gathering, process mapping, configuration design, user acceptance testing, and change implementation.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;15\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Develop user guidance, training materials, and role-based training for Arena PLM and \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Q\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;uality\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt; processes.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;16\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Monitor user adoption, process compliance, data \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Quality\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;, and system performance; recommend corrective actions where needed.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;17\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Promote consistent use of controlled product and \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Quality\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt; processes across the organization.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 1\u0026quot;\u0026gt;Required Qualifications\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335559738\u0026amp;quot;:480,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;18\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Bachelor’s degree in engineering, science, \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Quality\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;, information systems, or a related technical field.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;19\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;3–5 years of hands-on experience administering or configuring PLM, \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;QUALITY\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;, or related enterprise systems.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;20\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Demonstrated Arena experience at a configuration and administration level—not only end-user or reporting experience.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;21\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Experience configuring workflows, forms, fields, permissions, lifecycle states, notifications, approvals, and reports in Arena or a comparable platform.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;22\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Experience managing PLM and \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;QUALITY\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt; processes in the same system or across integrated systems.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;23\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Strong working knowledge of BOM management, product structures, revision control, document control, configuration management, ECO/ECN processes, and NPI.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;24\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Practical experience with CAPA, nonconformance/MRB, audit support, \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Quality\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt; records, and controlled documentation.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;25\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Experience with ERP integration or data synchronization, preferably with Oracle ERP or a similar platform.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;26\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Strong analytical, organizational, and problem-solving skills with exceptional attention to detail.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;27\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Ability to translate cross-functional business requirements into clear system configurations and sustainable processes.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;28\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Excellent written and verbal communication skills, with the ability to train users and influence process adoption.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 1\u0026quot;\u0026gt;Preferred Qualifications\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335559738\u0026amp;quot;:480,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;29\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Arena PLM implementation, redesign, migration, or major enhancement experience.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;30\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Experience supporting semiconductor, electronics, optical, or other hardware product-development environments.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;31\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Familiarity with ISO 9001 or comparable \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Quality\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;-management requirements.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;32\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Experience with PLM data governance, system validation, audit trails, and change-impact analysis.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;33\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Experience creating operational dashboards, metrics, and analytics from Arena, PLM, \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;or\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt; ERP data.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;34\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Experience leading cross-functional process-improvement or system-configuration projects.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 1\u0026quot;\u0026gt;Success in This Role\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335559738\u0026amp;quot;:480,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; 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data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;36\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Product data, BOMs, revisions, engineering changes, \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Quality\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt; 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data-aria-posinset=\u0026quot;38\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Users receive timely support and training, with increased adoption and reduced manual workarounds.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;39\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Data-\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Quality\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt; issues, workflow bottlenecks, and cross-system discrepancies are identified and resolved proactively.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 1\u0026quot;\u0026gt;Role Profile\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335559738\u0026amp;quot;:480,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;40\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Primary focus:\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;* Arena configuration and administration across PLM\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;41\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Key differentiator:\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;* Ability to independently configure Arena while owning the operational integrity of both product-lifecycle and \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Quality\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;-management processes\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;42\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Core partners:\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;* Engineering, \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Quality\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;, manufacturing, operations, supply chain, and IT\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p class=\u0026quot;p8i6j01 paragraph\u0026quot;\u0026gt;Salary range is $135,000 to $170,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184390005,"name":"Quality Management","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4723493005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4449204005,"location":{"name":"Tel Aviv-Yafo, Tel Aviv District, Israel"},"metadata":[{"id":12122734005,"name":"Country","value":"Israel","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Tel Aviv","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"System Validation","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4723493005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":null,"title":"Post-Silicon Validation Engineer","company_name":"Astera Labs","first_published":"2026-08-17T04:41:47-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;div class=\u0026quot;x_elementToProof\u0026quot; data-olk-copy-source=\u0026quot;MessageBody\u0026quot;\u0026gt;We are looking for a \u0026lt;strong\u0026gt;Post-Silicon Validation Engineer\u0026lt;/strong\u0026gt;\u0026amp;nbsp;with strong hands-on experience in PCIe link bring-up, physical-layer debug, and silicon validation. Engineer will work closely with Design, Architecture, Firmware, Software, Engineering teams.\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;ul data-spread=\u0026quot;false\u0026quot;\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Perform hands-on\u0026amp;nbsp;\u0026lt;strong\u0026gt;post-silicon validation\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Debug PCIe link issues including\u0026amp;nbsp;\u0026lt;strong\u0026gt;link training, LTSSM, equalization, recovery, resets, and link stability\u0026lt;/strong\u0026gt;.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Analyze PCIe state-machine traces, protocol traces, registers, logs, eye diagrams, and lab measurements.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive complex issues from initial failure through\u0026amp;nbsp;\u0026lt;strong\u0026gt;root-cause analysis and final resolution\u0026lt;/strong\u0026gt;.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work closely with silicon, firmware, software, architecture, and signal-integrity engineers to isolate issues across HW/FW/SW boundaries.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Validate PCIe functionality across different generations, platforms, configurations, and operating conditions.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop and execute PCIe validation plans, stress tests, corner-case scenarios, and interoperability tests.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Develop\u0026amp;nbsp; automation to improve validation coverage, debug efficiency, and regression testing.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;div class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Required Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;ul data-spread=\u0026quot;false\u0026quot;\u0026gt;\n\u0026lt;li\u0026gt;BS/MS in\u0026amp;nbsp;\u0026lt;strong\u0026gt;Electrical Engineering, Computer Engineering, Computer Science\u0026lt;/strong\u0026gt;, or equivalent experience.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;5+ years of engineering experience\u0026lt;/strong\u0026gt;\u0026amp;nbsp;in silicon validation, post-silicon debug, or high-speed interface development.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong hands-on knowledge of\u0026amp;nbsp;\u0026lt;strong\u0026gt;PCIe architecture and protocol\u0026lt;/strong\u0026gt;.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Experience working with PCIe analyzers, state traces, registers, logs, eye diagrams, and/or signal-integrity measurements.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong problem-solving skills and ability to independently drive issues to root cause.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience working across\u0026amp;nbsp;\u0026lt;strong\u0026gt;hardware, firmware, and software\u0026lt;/strong\u0026gt;\u0026amp;nbsp;boundaries.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Good scripting/programming skills, preferably\u0026amp;nbsp;\u0026lt;strong\u0026gt;Python\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Good Linux knowledge and experience with Linux PCIe debug tools.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong communication and collaboration skills.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;div class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;ul data-spread=\u0026quot;false\u0026quot;\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;Experience with\u0026amp;nbsp;\u0026lt;strong\u0026gt;PCIe Gen4/Gen5/Gen6/Gen7\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience with PCIe PHY, SerDes, equalization, lane margining, or signal integrity.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with PCIe compliance and interoperability testing.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience debugging intermittent, marginal, thermal-sensitive, or corner-case PCIe failures.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;Experience with PCIe switches,\u0026amp;nbsp; or networking/accelerator platforms.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Practical experience using AI/ML tools for engineering debug and automation.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184348005,"name":"System Validation CCE2","child_ids":[],"parent_id":null}],"offices":[{"id":4052111005,"name":"Haifa","location":"Israel","child_ids":[],"parent_id":4008937005},{"id":4056876005,"name":"Tel Aviv","location":"Israel","child_ids":[],"parent_id":4008937005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4733678005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4454469005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":null,"value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4733678005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2721","title":"Principal Advanced Packaging Engineer ","company_name":"Astera Labs","first_published":"2026-09-14T14:23:04-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;u\u0026gt;Principal Advanced Packaging Engineer:\u0026lt;/u\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;About the Role\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is seeking a Principal Advanced Packaging Engineer to lead R\u0026amp;amp;D for next-generation packaging technologies for optical chips. This is a senior individual contributor role focused on setting technical direction and driving packaging technology development for NPO and CPO products.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Responsibilities\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Lead R\u0026amp;amp;D for advanced packaging of optical chips, including 2.1D, 2.5D, and 3D integration.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Define and\u0026amp;nbsp;optimize\u0026amp;nbsp;wafer-level, panel-level, or die-level packaging process flows.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Drive EIC-to-PIC integration and broader optical device integration efforts.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Select and\u0026amp;nbsp;qualify\u0026amp;nbsp;packaging materials for advanced packaging.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Partner with OSAT, tool vendors, and material suppliers to drive equipment, process, and materials development.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Characterize and continuously improve yield, reliability, and process capability for NPO and CPO packages.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Develop and\u0026amp;nbsp;maintain\u0026amp;nbsp;packaging\u0026amp;nbsp;PDKs and design rules for NPO and CPO products.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;B.S., M.S., or Ph.D. in Electrical Engineering, Materials Science, Mechanical Engineering, or a related field.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;8+ years of experience in semiconductor or advanced packaging engineering, with\u0026amp;nbsp;demonstrated\u0026amp;nbsp;technical leadership.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Deep\u0026amp;nbsp;expertise\u0026amp;nbsp;in advanced packaging processes, including 2.5D/3D integration, flip-chip, hybrid bonding, Cu pillar, TSV, RDL, and\u0026amp;nbsp;overmold\u0026amp;nbsp;across wafer-, panel-, and die-level flows.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience with silicon\u0026amp;nbsp;photonics\u0026amp;nbsp;chip packaging and EIC/PIC integration.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience with advanced packaging materials, including underfill, molding compounds, dielectrics, adhesives, or optical-grade encapsulants.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Proven track record of equipment and process qualification with OSAT or tool suppliers.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience with PDK development and packaging design rule authoring.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong foundation\u0026amp;nbsp;in yield analysis, reliability characterization, and process capability methodologies such as\u0026amp;nbsp;Cpk\u0026amp;nbsp;and SPC.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience with CPO or NPO product development.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with optical coupling or waveguide alignment for photonic integration.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with DFM and DFT for advanced packaging.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Salary range is $205,000 to $260,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184255005,"name":"Design Engineering CCE1","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4733693005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4454480005,"location":{"name":"Taipei, Taiwan"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":null,"value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4733693005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2722","title":"Principal Advanced Packaging Engineer ","company_name":"Astera Labs","first_published":"2026-09-14T14:22:33-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;u\u0026gt;Principal Advanced Packaging Engineer:\u0026lt;/u\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;About the Role\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is seeking a Principal Advanced Packaging Engineer to lead R\u0026amp;amp;D for next-generation packaging technologies for optical chips. This is a senior individual contributor role focused on setting technical direction and driving packaging technology development for NPO and CPO products.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Responsibilities\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Lead R\u0026amp;amp;D for advanced packaging of optical chips, including 2.1D, 2.5D, and 3D integration.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Define and\u0026amp;nbsp;optimize\u0026amp;nbsp;wafer-level, panel-level, or die-level packaging process flows.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Drive EIC-to-PIC integration and broader optical device integration efforts.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Select and\u0026amp;nbsp;qualify\u0026amp;nbsp;packaging materials for advanced packaging.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Partner with OSAT, tool vendors, and material suppliers to drive equipment, process, and materials development.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Characterize and continuously improve yield, reliability, and process capability for NPO and CPO packages.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Develop and\u0026amp;nbsp;maintain\u0026amp;nbsp;packaging\u0026amp;nbsp;PDKs and design rules for NPO and CPO products.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;B.S., M.S., or Ph.D. in Electrical Engineering, Materials Science, Mechanical Engineering, or a related field.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;8+ years of experience in semiconductor or advanced packaging engineering, with\u0026amp;nbsp;demonstrated\u0026amp;nbsp;technical leadership.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Deep\u0026amp;nbsp;expertise\u0026amp;nbsp;in advanced packaging processes, including 2.5D/3D integration, flip-chip, hybrid bonding, Cu pillar, TSV, RDL, and\u0026amp;nbsp;overmold\u0026amp;nbsp;across wafer-, panel-, and die-level flows.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience with silicon\u0026amp;nbsp;photonics\u0026amp;nbsp;chip packaging and EIC/PIC integration.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience with advanced packaging materials, including underfill, molding compounds, dielectrics, adhesives, or optical-grade encapsulants.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Proven track record of equipment and process qualification with OSAT or tool suppliers.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience with PDK development and packaging design rule authoring.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong foundation\u0026amp;nbsp;in yield analysis, reliability characterization, and process capability methodologies such as\u0026amp;nbsp;Cpk\u0026amp;nbsp;and SPC.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience with CPO or NPO product development.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with optical coupling or waveguide alignment for photonic integration.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with DFM and DFT for advanced packaging.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Salary range will depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4185764005,"name":"Engineering Operations CCE1 (TWN_Engineering Operations CCE1)","child_ids":[],"parent_id":null}],"offices":[{"id":4002874005,"name":"Taiwan","location":"Taipei, Taiwan","child_ids":[4061060005,4009035005],"parent_id":null}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4735377005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4455250005,"location":{"name":"Ho Chi Minh City, Vietnam"},"metadata":[{"id":12122734005,"name":"Country","value":"Vietnam","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Ho Chi Minh","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Analog/AMS Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4735377005,"updated_at":"2026-09-28T10:46:41-04:00","requisition_id":null,"title":"Principal Analog Mixed-Signal Design Engineer","company_name":"Astera Labs","first_published":"2026-09-18T05:14:58-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;About the Role\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;We are seeking an experienced Analog/Mixed-Signal (AMS) Circuit Design Engineer to join our high-performance design team working on next-generation transceiver IPs targeting the FinFET technology node.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;In this role, you will design high-speed analog and mixed-signal circuits used in multi-gigabit transceivers, collaborating with layout, verification, and system teams to ensure robust performance, power efficiency, and successful silicon validation at advanced process nodes.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt; \u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Design critical AMS blocks such as PLLs, CDRs, TX drivers, RX front-ends, CTLEs, DFE, LDOs, bias generators, and ADC/DAC components for wireline transceivers.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Perform transistor-level design, simulation, and optimization for performance, power, and area across process, voltage, and temperature (PVT) corners.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work closely with layout engineers to guide floorplanning, matching-sensitive layout, and parasitic-aware design.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Perform design verification using pre- and post-layout simulations (transient, AC, noise, Monte Carlo, corner sweep).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ensure robust operation under variation, jitter, power supply noise, and crosstalk conditions.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Create and maintain design documentation, design reviews, and specifications.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with system architects, digital design, and firmware teams to define and optimize mixed-signal interface behavior.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support silicon bring-up, lab measurement correlation, and debug of design issues.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Use industry-standard tools (e.g., Virtuoso, Spectre, ADE, MATLAB, Python) for design and analysis.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt; \u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s or Master’s degree in Electrical Engineering, Microelectronics, or related field.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;8+ years of experience in analog/mixed-signal circuit design in deep-submicron or FinFET technologies.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong experience with:\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Transistor-level design and simulation in advanced nodes (≤ 5nm).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Designing analog blocks for high-speed transceivers (e.g., clocking, bias, analog front ends).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;SPICE simulation tools and AMS verification environments.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;Deep understanding of noise, jitter, linearity, bandwidth, gain, impedance matching, and power trade-offs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with layout interaction and parasitic-aware circuit optimization.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Solid debugging, problem-solving, and documentation skills.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt; \u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Benefits\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Competitive salary.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Performance bonus each year.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Long-term Incentive (refreshed each year).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Flexible working time.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Health check each year.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Insurance for engineer and family.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lunch Allowance.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Company trips.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4185002005,"name":"AMS Design (VNM_AMS Design)","child_ids":[],"parent_id":null}],"offices":[{"id":4053944005,"name":"Ho Chi Minh City","location":"Vietnam","child_ids":[],"parent_id":4053943005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4733703005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4454488005,"location":{"name":"Toronto, Ontario, Canada"},"metadata":[{"id":12122734005,"name":"Country","value":"Canada","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Toronto","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Analog/Mixed-Signal","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4733703005,"updated_at":"2026-09-25T13:16:32-04:00","requisition_id":"2026-507","title":"Principal Analog Mixed-Signal Design Engineer","company_name":"Astera Labs","first_published":"2026-09-25T13:16:32-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;h2 class=\u0026quot;wnfdnti _1ibi0s33y _1ibi0s34u\u0026quot;\u0026gt;Role Overview\u0026lt;/h2\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Astera Labs is redefining the connectivity that powers rack-scale AI infrastructure, and analog design is at the heart of it. As a Principal Analog Mixed Signal Design Engineer, you will architect and design the high-performance analog and mixed-signal circuits that anchor our SerDes, PHY, and high-speed I/O — the silicon building blocks that move data at the speed AI demands. Your work directly shapes the performance, power, and reliability of products deployed in the world\u0026#39;s most advanced data centers.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;This is a high-impact, hands-on role at a hyper-growth company purpose-built for AI connectivity. You will own designs from concept through silicon bring-up, set the technical bar for the analog team, and mentor engineers as we scale. If you want your circuits to enable the next generation of AI compute, this is where that happens.\u0026lt;/p\u0026gt;\n\u0026lt;h2 class=\u0026quot;wnfdnti _1ibi0s33y _1ibi0s34u\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/h2\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdntf\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Analog \u0026amp;amp; Mixed-Signal Design\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdntf\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Architect and design high-speed analog and mixed-signal circuits including PLLs, LDOs, references, high-speed SerDes building blocks, ADCs/DACs, and clocking.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Drive circuit design from specification and architecture through schematic, layout supervision, and verification across PVT corners.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Develop robust designs in advanced FinFET process nodes with attention to power, area, and performance trade-offs.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Silicon Execution \u0026amp;amp; Validation\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdntf\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Lead silicon bring-up, characterization, and debug, partnering with validation and product engineering to root-cause and resolve issues.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Define and execute test plans to correlate silicon performance against design targets.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Technical Leadership\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdntf\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Set analog design methodology, review standards, and best practices across the team.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Partner cross-functionally with digital, physical design, systems, and architecture teams to deliver full-chip solutions.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Mentor and guide junior engineers, elevating the technical capability of the analog organization.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h2 class=\u0026quot;wnfdnti _1ibi0s33y _1ibi0s34u\u0026quot;\u0026gt;Basic Qualifications\u0026lt;/h2\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdntf\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;MS or PhD in Electrical Engineering or a related field.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;8+ years of experience in analog and mixed-signal integrated circuit design.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Proven track record designing high-speed analog circuits such as PLLs, SerDes front-ends, data converters, references, or regulators in advanced CMOS/FinFET nodes.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Strong understanding of physical-layer design principles, signal integrity, and high-speed I/O.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Proficiency with industry-standard design and simulation tools (e.g., Cadence Virtuoso, Spectre) and solid layout/parasitic-aware design skills.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h2 class=\u0026quot;wnfdnti _1ibi0s33y _1ibi0s34u\u0026quot;\u0026gt;Preferred Qualifications\u0026lt;/h2\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdntf\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Experience taking multiple analog/mixed-signal designs through full production tape-out and high-volume manufacturing.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Expertise in high-speed serial link design (PCIe, Ethernet, UALink, UCIe) and associated PHY architectures.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Familiarity with silicon debug, ATE test development, and design-for-test techniques.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Experience mentoring engineers and leading technical design reviews.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Excellent communication skills and a collaborative, ownership-driven mindset.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Salary range is $165,000 to $210,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p8i6j01 paragraph\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184482005,"name":"AMS Design (US_AMS Design)","child_ids":[],"parent_id":null}],"offices":[{"id":4000119005,"name":"Toronto","location":"Canada","child_ids":[],"parent_id":4004709005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4719589005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4447235005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Analog/AMS Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4719589005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2026-372","title":"Principal Analog Mixed-Signal Design Engineer","company_name":"Astera Labs","first_published":"2026-09-11T13:12:17-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;h2 class=\u0026quot;wnfdnti _1ibi0s33y _1ibi0s34u\u0026quot;\u0026gt;Role Overview\u0026lt;/h2\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Astera Labs is redefining the connectivity that powers rack-scale AI infrastructure, and analog design is at the heart of it. As a Principal Analog Design Engineer, you will architect and design the high-performance analog and mixed-signal circuits that anchor our SerDes, PHY, and high-speed I/O — the silicon building blocks that move data at the speed AI demands. Your work directly shapes the performance, power, and reliability of products deployed in the world\u0026#39;s most advanced data centers.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;This is a high-impact, hands-on role at a hyper-growth company purpose-built for AI connectivity. You will own designs from concept through silicon bring-up, set the technical bar for the analog team, and mentor engineers as we scale. If you want your circuits to enable the next generation of AI compute, this is where that happens.\u0026lt;/p\u0026gt;\n\u0026lt;h2 class=\u0026quot;wnfdnti _1ibi0s33y _1ibi0s34u\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/h2\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdntf\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Analog \u0026amp;amp; Mixed-Signal Design\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdntf\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Architect and design high-speed analog and mixed-signal circuits including PLLs, LDOs, references, high-speed SerDes building blocks, ADCs/DACs, and clocking.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Drive circuit design from specification and architecture through schematic, layout supervision, and verification across PVT corners.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Develop robust designs in advanced FinFET process nodes with attention to power, area, and performance trade-offs.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Silicon Execution \u0026amp;amp; Validation\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdntf\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Lead silicon bring-up, characterization, and debug, partnering with validation and product engineering to root-cause and resolve issues.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Define and execute test plans to correlate silicon performance against design targets.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Technical Leadership\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdntf\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Set analog design methodology, review standards, and best practices across the team.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Partner cross-functionally with digital, physical design, systems, and architecture teams to deliver full-chip solutions.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Mentor and guide junior engineers, elevating the technical capability of the analog organization.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h2 class=\u0026quot;wnfdnti _1ibi0s33y _1ibi0s34u\u0026quot;\u0026gt;Basic Qualifications\u0026lt;/h2\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdntf\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;MS or PhD in Electrical Engineering or a related field.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;8+ years of experience in analog and mixed-signal integrated circuit design.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Proven track record designing high-speed analog circuits such as PLLs, SerDes front-ends, data converters, references, or regulators in advanced CMOS/FinFET nodes.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Strong understanding of physical-layer design principles, signal integrity, and high-speed I/O.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Proficiency with industry-standard design and simulation tools (e.g., Cadence Virtuoso, Spectre) and solid layout/parasitic-aware design skills.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h2 class=\u0026quot;wnfdnti _1ibi0s33y _1ibi0s34u\u0026quot;\u0026gt;Preferred Qualifications\u0026lt;/h2\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdntf\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Experience taking multiple analog/mixed-signal designs through full production tape-out and high-volume manufacturing.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Expertise in high-speed serial link design (PCIe, Ethernet, UALink, UCIe) and associated PHY architectures.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Familiarity with silicon debug, ATE test development, and design-for-test techniques.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Experience mentoring engineers and leading technical design reviews.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Excellent communication skills and a collaborative, ownership-driven mindset.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Salary range is $207,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p8i6j01 paragraph\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184198005,"name":"AMS Design","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4699636005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4437757005,"location":{"name":"Tel Aviv-Yafo, Tel Aviv District, Israel"},"metadata":[{"id":12122734005,"name":"Country","value":"Israel","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Haifa","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":"Architecture CCE2","value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Architecture","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4699636005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2592","title":"Principal Architect ","company_name":"Astera Labs","first_published":"2026-06-09T09:14:39-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;div\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;p\u0026gt;We are seeking an experienced \u0026lt;strong\u0026gt;Principal\u0026amp;nbsp;Architect\u0026lt;/strong\u0026gt; to lead the architecture of high-performance connectivity solutions, with a strong focus on PCIe, high-speed networking, and Ethernet-based systems.\u0026lt;br\u0026gt;This role will define next-generation architectures for AI infrastructure, working at the intersection of \u0026lt;strong\u0026gt;silicon, system, and protocol design\u0026lt;/strong\u0026gt;. You will play a key role in shaping innovative solutions that enable hyperscale customers to build scalable, high-bandwidth, and low-latency systems.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This is a unique opportunity to join a \u0026lt;strong\u0026gt;new and growing Israel site\u0026lt;/strong\u0026gt;, influence technical direction, and take ownership of critical architectural decisions impacting industry-leading products.\u0026lt;/p\u0026gt;\n\u0026lt;p data-path-to-node=\u0026quot;4\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Define and drive \u0026lt;strong\u0026gt;system and chip-level architecture\u0026lt;/strong\u0026gt; for high-speed connectivity products\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead architecture for \u0026lt;strong\u0026gt;PCIe-based interconnects\u0026lt;/strong\u0026gt;, networking protocols, and Ethernet subsystems\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Analyze system requirements and translate them into scalable and efficient hardware architectures\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive tradeoff analysis across performance, power, latency, area, and cost\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with cross-functional teams including \u0026lt;strong\u0026gt;RTL, Physical Design, Firmware, Validation, and Product Engineering\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Define and review \u0026lt;strong\u0026gt;micro-architecture specifications\u0026lt;/strong\u0026gt; and ensure alignment across teams\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Contribute to \u0026lt;strong\u0026gt;standard-based and custom protocols\u0026lt;/strong\u0026gt; for next-generation AI infrastructure\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support performance modeling, simulation, and architectural validation\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work closely with customers and partners to understand emerging use cases and requirements\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Mentor engineers and help build strong technical leadership within the Israel R\u0026amp;amp;D center\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;br\u0026gt;\u0026lt;/span\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;10+ years of experience\u0026lt;/strong\u0026gt; in semiconductor architecture, ASIC design, or system engineering\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong expertise in \u0026lt;strong\u0026gt;PCIe architecture (Gen4/5/6+)\u0026lt;/strong\u0026gt; and its ecosystem\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep understanding of \u0026lt;strong\u0026gt;Networking and Ethernet (e.g., 25G/50G/100G/400G and beyond)\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience designing \u0026lt;strong\u0026gt;high-speed, low-latency data paths\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Solid understanding of \u0026lt;strong\u0026gt;SoC architecture and integration challenges\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience working across full chip development lifecycle\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong analytical and problem-solving skills with ability to evaluate complex tradeoffs\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ability to influence and collaborate across multiple engineering domains\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Preferred Experience\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience with \u0026lt;strong\u0026gt;CXL, NVLink, UALink, or other advanced interconnect protocols\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Background in \u0026lt;strong\u0026gt;AI/ML infrastructure, data center systems, or hyperscaler environments\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with \u0026lt;strong\u0026gt;SerDes-based systems and high-speed PHY integration\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with \u0026lt;strong\u0026gt;networking stacks, switching, or RDMA technologies\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with \u0026lt;strong\u0026gt;performance modeling tools and architectural simulators\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of \u0026lt;strong\u0026gt;power/performance optimization techniques at system level\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Track record of driving architecture from concept to silicon\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184217005,"name":"Architecture CCE2","child_ids":[],"parent_id":null}],"offices":[{"id":4052111005,"name":"Haifa","location":"Israel","child_ids":[],"parent_id":4008937005},{"id":4056876005,"name":"Tel Aviv","location":"Israel","child_ids":[],"parent_id":4008937005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4637712005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4408383005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Engineering Operations","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4637712005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2156","title":"Principal ATE Test Engineer","company_name":"Astera Labs","first_published":"2025-12-19T14:25:25-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p data-renderer-start-pos=\u0026quot;26\u0026quot;\u0026gt;\u0026lt;strong data-renderer-mark=\u0026quot;true\u0026quot;\u0026gt;Job Description\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;43\u0026quot;\u0026gt;We are looking for \u0026lt;strong\u0026gt;Principal ATE Test Engineers\u0026amp;nbsp;\u0026lt;/strong\u0026gt;with proven experience in developing and supporting complex mixed-signal silicon SoC products to lead ATE Test solutions. The ideal candidate will develop and oversee SoC test strategy, interact with manufacturing partners, define, and implement ATE programs and own the product from design, initial samples all the way through high volume production ramp. The candidate should have working knowledge of communication/interface protocols such as PCI-Express (Gen-4/5/6), Ethernet, Infiniband, DDR, NVMe, USB, etc.\u0026lt;/p\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;574\u0026quot;\u0026gt;\u0026lt;strong data-renderer-mark=\u0026quot;true\u0026quot;\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;598\u0026quot;\u0026gt;Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, and a Master’s is preferred.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;742\u0026quot;\u0026gt;≥8-year experience releasing complex SoC/silicon products to high volume manufacturing.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;833\u0026quot;\u0026gt;Working knowledge of high-speed protocols like PCIe, Ethernet, Infiniband, DDR, NVMe, USB, etc.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;932\u0026quot;\u0026gt;Professional attitude with ability to execute on multiple tasks with minimal supervision.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;1025\u0026quot;\u0026gt;Strong team player with good communication skills to work alongside a team of high caliber engineers.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;1130\u0026quot;\u0026gt;Entrepreneurial, open-mind behavior and can-do attitude.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong data-renderer-mark=\u0026quot;true\u0026quot;\u0026gt;Required Experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;1213\u0026quot;\u0026gt;Hands-on experience with high-speed mixed signal SoC test program/hardware development on multiple high-speed test platforms.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;1342\u0026quot;\u0026gt;Collaboration with design team to define test strategy, create and own test plan.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;1427\u0026quot;\u0026gt;Tester platform selection, design, and development of ATE hardware for wafer sort and final test.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;1528\u0026quot;\u0026gt;Familiar with high-speed load board design techniques.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;1586\u0026quot;\u0026gt;Proven track record of implementing ATE patterns to optimize tester resources and minimize ATE test time while maintaining product quality.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;1729\u0026quot;\u0026gt;Strong knowledge and development of DFT techniques implemented in silicon that provide maximum defect and parametric device coverage – SCAN, MEMBIST, SerDes and other functional tests.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;1917\u0026quot;\u0026gt;Skilled in control interfaces – I2C, I3C, SPI, MDIO, JTAG etc.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;1983\u0026quot;\u0026gt;Expertise in production test of high speed SerDes operating at 16Gbps and higher.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;2068\u0026quot;\u0026gt;Skilled in ATE programming, silicon/ATE bring-up, bench-ATE correlation and debug.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;2154\u0026quot;\u0026gt;Experience with lab equipment including protocol analyzers and oscilloscopes.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;2235\u0026quot;\u0026gt;Experience with using Teradyne or Advantest 93k ATE platform.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;2290\u0026quot;\u0026gt;Proficiency in, at least, one modern programming language such as C/C++, Python.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong data-renderer-mark=\u0026quot;true\u0026quot;\u0026gt;Preferred Experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;2398\u0026quot;\u0026gt;Fluent in data processing using high level programming languages.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;2398\u0026quot;\u0026gt;Experience in running External loopback at wafer sort.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;2467\u0026quot;\u0026gt;Familiarity with modern databases\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;2467\u0026quot;\u0026gt;Basic knowledge of RF Testing on ATE Platform.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;p\u0026gt;The base salary range is $209,000.00 USD – $240,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.\u0026amp;nbsp;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4728417005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4451706005,"location":{"name":"Bengaluru, Karnataka, India"},"metadata":[{"id":12122734005,"name":"Country","value":"India","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Bengaluru","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Design Verification","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4728417005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":null,"title":"Principal Design Verification Engineer","company_name":"Astera Labs","first_published":"2026-08-27T15:35:07-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;We are seeking talented Design Verification Professionals with proven expertise in industry-standard protocols such as PCIe and CXL. You will play a key role in the functional verification of designs, from developing block-level and system-level verification plans to writing test sequences, executing tests, and collecting and closing coverage.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Responsibilities:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Develop and execute block-level and system-level verification plans.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Write and execute test sequences and collect and close coverage.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with RTL designers to debug failures and refine verification processes.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Utilize coding and protocol expertise to contribute to functional verification.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop user-controlled random constraints in transaction-based verification methodologies.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Write assertions, cover properties, and analyze coverage data.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Create VIP abstraction layers for sequences to simplify and scale verification deployments.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Minimum of 12 years’ experience in supporting or developing complex SoC/silicon products for server, storage, and/or networking applications.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong academic and technical background in Electrical Engineering or Computer Engineering (bachelor’s degree required, master’s preferred).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Professional attitude with the ability to prioritize tasks, prepare for customer meetings, and work independently with minimal guidance.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of industry-standard simulators, revision control systems, and regression systems.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Entrepreneurial, open-minded behavior and a can-do attitude, with a focus on customer satisfaction.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Experience:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Interpreting PCIe/CXL standard protocol specifications to develop and execute verification plans in simulation environments.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience using Verification IPs from third-party vendors for PCIe/CXL, focusing on Gen3 or above.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ability to independently develop test plans and sequences in UVM to generate stimuli.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience writing assertions, cover properties, and analyzing coverage data.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Developing VIP abstraction layers for sequences to simplify and scale verification deployments.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Experience:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Expertise in verifying Physical Layer, Link Layer, and Transaction Layer of PCIe/CXL protocols, including compliance on PCIe/CXL EP/RC.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with buffering and queuing with QoS on complex NOC-based SoCs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Analyzing performance at the system level on switching fabrics.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184260005,"name":"Design Verification CCE2","child_ids":[],"parent_id":null}],"offices":[{"id":4049113005,"name":"Bengaluru","location":"India","child_ids":[],"parent_id":4052109005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4729354005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4447236005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Analog/AMS Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4729354005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2026-373","title":"Principal Design Verification Engineer- SerDes/PHY IP","company_name":"Astera Labs","first_published":"2026-08-31T17:43:41-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;h2 class=\u0026quot;wnfdnth _1ibi0s33y _1ibi0s34u\u0026quot; data-pm-slice=\u0026quot;1 1 []\u0026quot;\u0026gt;Role Overview\u0026lt;/h2\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Astera Labs is hiring a Principal Design Verification Engineer to own functional verification of our high-speed SerDes/PHY IP — the connectivity engine powering rack-scale AI infrastructure. You will architect verification environments, drive coverage closure, and ensure first-pass silicon success on the analog/digital boundary that defines next-generation AI systems.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;This is a high-impact, hands-on role at the heart of Astera Labs\u0026#39; hyper-growth story. You\u0026#39;ll partner directly with PHY analog/mixed-signal designers, digital architects, and SoC integration teams to verify multi-Gbps SerDes blocks that ship into the world\u0026#39;s most advanced AI platforms, including UALink, UCIe, PCIe Gen 6/Gen 7, and Ethernet-based connectivity products.\u0026lt;/p\u0026gt;\n\u0026lt;h2 class=\u0026quot;wnfdnth _1ibi0s33y _1ibi0s34u\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/h2\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdnte\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Verification Architecture \u0026amp;amp; Strategy\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Architect UVM-based verification environments for SerDes/PHY IP, including PMA, PCS, and PHY-MAC interface layers\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Define verification plans, coverage models, and sign-off criteria for high-speed serial link blocks\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Drive methodology decisions across analog/mixed-signal co-simulation, gate-level simulation, and emulation flows\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdnte\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Execution \u0026amp;amp; Coverage Closure\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Develop SystemVerilog/UVM testbenches, sequences, scoreboards, and reference models for multi-Gbps SerDes lanes\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Execute functional, performance, and corner-case verification across equalization, CDR, training, and link bring-up scenarios\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Lead coverage analysis and closure, debug failures with designers, and drive regressions to clean tape-out\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdnte\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Physical Layer \u0026amp;amp; Protocol Verification\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Verify PHY behavior against industry specifications including PCIe Gen 6/Gen 7, UALink, UCIe, and Ethernet PHY standards\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Model and validate channel behavior, link training state machines, and analog handoff scenarios\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Partner with analog/AMS designers on Real Number Modeling (RNM) and behavioral models for SerDes blocks\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdnte\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional Leadership\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Mentor junior DV engineers and set technical direction across the verification team\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Collaborate with SoC integration, firmware, post-silicon validation, and customer engineering teams\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Contribute to verification IP reuse strategy and tooling improvements across product lines\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h2 class=\u0026quot;wnfdnth _1ibi0s33y _1ibi0s34u\u0026quot;\u0026gt;Basic Qualifications\u0026lt;/h2\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, Computer Engineering, or related field\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;8+ years of design verification experience on high-speed SerDes, PHY, or mixed-signal IP\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Strong understanding of the physical layer, including equalization (CTLE, DFE, FFE), CDR, training sequences, and link bring-up\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Expert-level proficiency in SystemVerilog and UVM\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Hands-on experience with analog/mixed-signal co-simulation and Real Number Modeling (RNM)\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Working knowledge of one or more high-speed serial protocols: PCIe, UALink, UCIe, Ethernet, or CXL\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h2 class=\u0026quot;wnfdnth _1ibi0s33y _1ibi0s34u\u0026quot;\u0026gt;Preferred Qualifications\u0026lt;/h2\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;MS or PhD in Electrical Engineering or Computer Engineering\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Experience verifying PCIe Gen 6/Gen 7, UALink, or UCIe SerDes/PHY IP\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Familiarity with emulation platforms (Palladium, Veloce, or ZeBu) and gate-level simulation flows\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Scripting proficiency in Python or Perl for verification automation and regression management\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Experience supporting post-silicon bring-up and correlating pre-silicon coverage with silicon results\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Proven ability to lead technically across a multi-disciplinary team in a fast-paced environment\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Salary range is $207,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184198005,"name":"AMS Design","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4703793005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4439628005,"location":{"name":"Tel Aviv-Yafo, Tel Aviv District, Israel"},"metadata":[{"id":12122734005,"name":"Country","value":"Israel","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Haifa","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Physical Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4703793005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2628","title":"Principal DFT Engineer","company_name":"Astera Labs","first_published":"2026-06-08T03:07:32-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is establishing a strategic R\u0026amp;amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical \u0026#39;data bottlenecks\u0026#39; enabling the future of AI at scale. As we expand our presence in Israel, we\u0026#39;re seeking a visionary\u0026lt;strong\u0026gt; Principal DFT Engineer \u0026lt;/strong\u0026gt;to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world\u0026#39;s largest AI clusters.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;div data-olk-copy-source=\u0026quot;MessageBody\u0026quot;\u0026gt;As a Principal DFT Engineer, you will provide technical leadership across the full DFT lifecycle—from architecture and specification through implementation, verification, and silicon bring-up. You will define and drive DFT strategy, establish robust methodologies, and lead execution to ensure high test quality and manufacturability. This role requires deep expertise, cross-functional influence, and the ability to drive DFT excellence across projects and teams.\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;This is a critical leadership position with high impact on first-pass silicon success and production quality for next-generation AI connectivity solutions.\u0026lt;/div\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;strong data-olk-copy-source=\u0026quot;MessageBody\u0026quot;\u0026gt;DFT Architecture \u0026amp;amp; Technical Leadership\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Define and own DFT architecture for complex SoCs, including Scan, MBIST, LBIST, JTAG/iJTAG, and ATPG strategies\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead DFT planning, specification, and quality tracking across the project lifecycle\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Provide technical leadership and drive DFT sign-off readiness to ensure successful tapeout\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;strong\u0026gt;Execution Across the Full Lifecycle\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Lead DFT implementation, integration, and verification at block, full-chip and chiplet levels\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Own end-to-end DFT activities from specification through silicon bring-up and production support\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ensure high test coverage, robust pattern generation, and alignment with manufacturing requirements\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;strong\u0026gt;Methodology \u0026amp;amp; Cross-Functional Impact\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Develop and drive scalable DFT methodologies, flows, and automation frameworks\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate closely with RTL, Physical Design, STA, and Test Engineering teams to ensure design-for-test readiness\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Optimize DFT integration across front-end and backend flows to improve quality, PPA, and turnaround time\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-olk-copy-source=\u0026quot;MessageBody\u0026quot;\u0026gt;Bachelor’s degree in Electrical Engineering or related technical field (Master’s preferred)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;12+ years of experience in DFT design, implementation, and verification for complex ASIC/SoC designs\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven experience in leading DFT activities across full chip development cycles\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep expertise in DFT techniques including Scan, MBIST, LBIST, JTAG/iJTAG, and ATPG\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of DFT and Physical Design flows, including timing implications and integration challenges\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with industry-standard DFT tools (Siemens Tessent, Synopsys TestMAX or equivalent)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Solid experience with DFT verification methodologies and coverage analysis\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong scripting skills (Tcl, Python, or Perl) for automation and flow development\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-olk-copy-source=\u0026quot;MessageBody\u0026quot;\u0026gt;Experience with advanced process nodes (7nm and below)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Background in high-speed connectivity designs (PCIe, Ethernet, CXL, or similar)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with hierarchical DFT methodologies and large multi-die or chiplet-based systems\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of silicon bring-up, production test flows, and yield optimization\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with STA, low-power design, and CDC as it relates to DFT integration\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong leadership and communication skills, with ability to influence cross-functional teams globally\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4052111005,"name":"Haifa","location":"Israel","child_ids":[],"parent_id":4008937005},{"id":4056876005,"name":"Tel Aviv","location":"Israel","child_ids":[],"parent_id":4008937005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4732863005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4454058005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Digital Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4732863005,"updated_at":"2026-10-07T15:25:22-04:00","requisition_id":"2026-171","title":"Principal Digital Design Engineer","company_name":"Astera Labs","first_published":"2026-09-14T13:00:37-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Job Description\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;We are looking for \u0026lt;strong\u0026gt;Principal Digital Design Engineers \u0026lt;/strong\u0026gt;with experience developing micro-architecture and implementation of the front-end circuit design, including RTL, synthesis, IP integration, and block-level verification for high performance network controllers. The candidate must have good knowledge of communication/interface protocols such as PCI-Express (Gen-3 and above), Ualink, Esun, Ethernet etc.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE is required, and a Master’s degree is preferred.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;+8 years’ experience supporting or developing complex SoC/silicon products for Switch ASIC, Networking applications and/or Server, Storage.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Authorized to work in the US and start immediately.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Experience:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Hands-on, thorough knowledge of high-speed protocols like PCIe, Ualink, Esun, Ethernet, etc.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven front end design expertise – architecture, RTL, simulations, synthesis, timing closure, GLS, DFT etc.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Full chip or block level ownership from architecture to GDS, driving multiple complex designs to production\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with Synopsys and/or Cadence digital design tools/flows\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Good knowledge of design for test (DFT), stuck-at and transition scan test insertion\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with UVM based design verification\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Silicon bring-up and debug expertise\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Small-geometry CMOS (≤28nm) design\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Experience:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Firmware development with C-language, scripting with Python or other equivalent programming languages.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Development/support for PCIe or Ethernet Switch products.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;The base salary range is $185,000.00 USD – $230,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184255005,"name":"Design Engineering CCE1","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4738050005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4456508005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Digital Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4738050005,"updated_at":"2026-10-08T07:10:33-04:00","requisition_id":"2026-454","title":"Principal Digital Design Engineer","company_name":"Astera Labs","first_published":"2026-10-05T12:28:52-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Job Description\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;We are looking for \u0026lt;strong\u0026gt;Principal Digital Design Engineers \u0026lt;/strong\u0026gt;with experience developing micro-architecture and implementation of the front-end circuit design, including RTL, synthesis, IP integration, and block-level verification for high performance network controllers. The candidate must have good knowledge of communication/interface protocols such as PCI-Express (Gen-3 and above), Ualink, Esun, Ethernet etc.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE is required, and a Master’s degree is preferred.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;+8 years’ experience supporting or developing complex SoC/silicon products for Switch ASIC, Networking applications and/or Server, Storage.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Authorized to work in the US and start immediately.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Experience:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Hands-on, thorough knowledge of high-speed protocols like PCIe, Ualink, Esun, Ethernet, etc.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven front end design expertise – architecture, RTL, simulations, synthesis, timing closure, GLS, DFT etc.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Full chip or block level ownership from architecture to GDS, driving multiple complex designs to production\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with Synopsys and/or Cadence digital design tools/flows\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Good knowledge of design for test (DFT), stuck-at and transition scan test insertion\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with UVM based design verification\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Silicon bring-up and debug expertise\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Small-geometry CMOS (≤28nm) design\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Experience:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Firmware development with C-language, scripting with Python or other equivalent programming languages.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Development/support for PCIe or Ethernet Switch products.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;The base salary range is $185,000.00 USD – $240,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184256005,"name":"Design Engineering CCE2","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4733735005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4454508005,"location":{"name":"Taipei, Taiwan"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":null,"value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4733735005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2723","title":"Principal Digital Design Engineer ","company_name":"Astera Labs","first_published":"2026-09-14T18:04:31-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;u\u0026gt;Principal Digital Design Engineer:\u0026lt;/u\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Join our team as\u0026amp;nbsp;\u0026lt;strong\u0026gt;Principal Digital Design Engineer\u0026amp;nbsp;\u0026lt;/strong\u0026gt;to architect and implement next-generation digital designs for high-performance connectivity solutions. You\u0026#39;ll own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, PD and DFT teams to deliver high-performance products in a fast-paced, collaborative environment.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Develop and implement complex digital blocks and subsystems by defining micro-architecture and driving digital design.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with verification teams to develop test plans, achieve coverage closure, and debug complex issues.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead efforts to achieve timing closure and implement Design-for-Test (DFT) features for optimal design performance.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work closely with post-silicon teams to facilitate silicon bring-up and debug.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Mentor junior engineers to develop their technical skills and expertise.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Actively contribute to the development and improvement of silicon development processes.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive designs to production, ensuring accountability for quality, schedule, and overall design success.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Qualifications:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Education \u0026amp;amp; Experience:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s degree in electrical engineering or equivalent.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;8+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Digital Design Expertise:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Architecture definition and micro-architecture development\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;RTL coding, functional simulation, and synthesis\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Timing closure and gate-level simulation (GLS)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Design for test (DFT) implementation\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Production experience with advanced CMOS nodes (≤7nm)\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Protocols \u0026amp;amp; Integration:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Deep expertise in at least one high-speed protocol—PCIe, Ethernet, InfiniBand, DDR, or similar\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Third-party IP integration and verification.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Block-level design ownership from architecture through GDS\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Tools \u0026amp;amp; Methodologies:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Proficiency with Cadence and/or Synopsys digital design flows\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with UVM-based verification methodologies.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Silicon bring-up, debug, and failure analysis expertise\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Professional Attributes:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong work ethic with the ability to balance multiple priorities in a dynamic environment\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent communication and collaboration skills; comfortable working cross-functionally with global teams\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Self-directed learner who thrives with minimal supervision and adapts quickly to changing requirements\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Customer-focused mindset with ability to translate business needs into technical excellence\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Track record of delivering multiple high-performance designs to production in data-center environments\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on collaboration with embedded firmware teams; deep understanding of firmware development challenges and constraints\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with standard embedded processor subsystems (RISC-V, Arm, etc.)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven contributions to design methodology, CAD automation, or design infrastructure to improve productivity or design quality\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;The base salary will be determined based on your location, experience, and the pay of employees in similar positions.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184269005,"name":"Digital Design","child_ids":[],"parent_id":null}],"offices":[{"id":4002874005,"name":"Taiwan","location":"Taipei, Taiwan","child_ids":[4061060005,4009035005],"parent_id":null}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4733759005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4454526005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":null,"value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4733759005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2724","title":"Principal Digital Design Engineer ","company_name":"Astera Labs","first_published":"2026-09-14T18:05:04-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;u\u0026gt;Principal Digital Design Engineer:\u0026lt;/u\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Join our team as\u0026amp;nbsp;\u0026lt;strong\u0026gt;Principal Digital Design Engineer\u0026amp;nbsp;\u0026lt;/strong\u0026gt;to architect and implement next-generation digital designs for high-performance connectivity solutions. You\u0026#39;ll own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, PD and DFT teams to deliver high-performance products in a fast-paced, collaborative environment.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Develop and implement complex digital blocks and subsystems by defining micro-architecture and driving digital design.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with verification teams to develop test plans, achieve coverage closure, and debug complex issues.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead efforts to achieve timing closure and implement Design-for-Test (DFT) features for optimal design performance.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work closely with post-silicon teams to facilitate silicon bring-up and debug.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Mentor junior engineers to develop their technical skills and expertise.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Actively contribute to the development and improvement of silicon development processes.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive designs to production, ensuring accountability for quality, schedule, and overall design success.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Qualifications:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Education \u0026amp;amp; Experience:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s degree in electrical engineering or equivalent.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;8+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Digital Design Expertise:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Architecture definition and micro-architecture development\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;RTL coding, functional simulation, and synthesis\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Timing closure and gate-level simulation (GLS)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Design for test (DFT) implementation\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Production experience with advanced CMOS nodes (≤7nm)\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Protocols \u0026amp;amp; Integration:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Deep expertise in at least one high-speed protocol—PCIe, Ethernet, InfiniBand, DDR, or similar\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Third-party IP integration and verification.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Block-level design ownership from architecture through GDS\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Tools \u0026amp;amp; Methodologies:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Proficiency with Cadence and/or Synopsys digital design flows\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with UVM-based verification methodologies.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Silicon bring-up, debug, and failure analysis expertise\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Professional Attributes:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong work ethic with the ability to balance multiple priorities in a dynamic environment\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent communication and collaboration skills; comfortable working cross-functionally with global teams\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Self-directed learner who thrives with minimal supervision and adapts quickly to changing requirements\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Customer-focused mindset with ability to translate business needs into technical excellence\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Track record of delivering multiple high-performance designs to production in data-center environments\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on collaboration with embedded firmware teams; deep understanding of firmware development challenges and constraints\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with standard embedded processor subsystems (RISC-V, Arm, etc.)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven contributions to design methodology, CAD automation, or design infrastructure to improve productivity or design quality\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;The base salary range is $185,000.00 USD – $230,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184472005,"name":"Design Engineering CCE1 (US_SE_Design Engineering CCE1)","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4672627005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4424481005,"location":{"name":"San Jose, CA"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":"Design Engineering CCE1","value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Digital Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4672627005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2362","title":"Principal Digital Design Engineer ","company_name":"Astera Labs","first_published":"2026-03-12T15:00:01-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Join Astera Labs as a \u0026lt;strong\u0026gt;Principal Digital Design Engineer\u0026lt;/strong\u0026gt; to architect and implement next-generation digital designs for high-performance AI connectivity solutions. You\u0026#39;ll own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, physical design, and DFT teams to deliver production-quality silicon supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This role offers the opportunity to work on cutting-edge technology at the forefront of AI infrastructure, taking ownership of critical design challenges in a fast-paced, collaborative environment where your contributions directly impact products deployed by the world\u0026#39;s leading hyperscalers.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Design Ownership \u0026amp;amp; Execution\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Develop and implement complex digital blocks and subsystems by defining micro-architecture and driving RTL implementation with an exceptional power, performance and area trade-off using silicon technologies better than 7nm.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead efforts to achieve timing closure and implement Design-for-Test (DFT) features for optimal design performance\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive designs to production, ensuring accountability for quality, schedule, and overall design success\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Verification \u0026amp;amp; Integration\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with verification teams to develop test plans, achieve coverage closure, and debug complex issues\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Own third-party IP integration and block-level verification through sign-off\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work closely with post-silicon teams to facilitate silicon bring-up and debug\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Technical Leadership\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Mentor junior engineers to develop their technical skills and expertise\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Actively contribute to the development and improvement of silicon development processes\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive design methodology improvements and CAD automation initiatives\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering or equivalent\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;10+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Expertise in architecture definition, micro-architecture development, RTL coding, functional simulation, and synthesis\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of timing closure, gate-level simulation (GLS), and DFT implementation\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep expertise in at least one high-speed protocol: PCIe, CXL, Ethernet, DDR, or similar\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Production experience with advanced CMOS nodes (≤7nm)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency with Cadence and/or Synopsys digital design flows\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Master\u0026#39;s degree in Electrical Engineering or related field\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Track record of delivering multiple high-performance designs to production in data-center environments\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on collaboration with embedded firmware teams; understanding of firmware development challenges\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with standard embedded processor subsystems (RISC-V, Arm, etc.)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven contributions to design methodology, CAD automation, or design infrastructure\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Salary range is $185,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184255005,"name":"Design Engineering CCE1","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4645005005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4411914005,"location":{"name":"San Jose, CA"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":"Design Engineering CCE1","value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Digital Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4645005005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2181","title":"Principal Digital Design Engineer (AI Fabric)","company_name":"Astera Labs","first_published":"2025-12-30T17:30:53-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Join our team as \u0026lt;strong\u0026gt;Principal Digital Design Engineer\u0026amp;nbsp;\u0026lt;/strong\u0026gt;to architect and implement next-generation digital designs for high-performance connectivity solutions. You\u0026#39;ll own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, PD and DFT teams to deliver high performance products in a fast-paced, collaborative environment.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Develop and implement complex digital blocks and subsystems by defining micro-architecture and driving digital design.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with verification teams to develop test plans, achieve coverage closure, and debug complex issues.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead efforts to achieve timing closure and implement Design-for-Test (DFT) features for optimal design performance.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work closely with post-silicon teams to facilitate silicon bring-up and debug.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Mentor junior engineers to develop their technical skills and expertise.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Actively contribute to the development and improvement of silicon development processes.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive designs to production, ensuring accountability for quality, schedule, and overall design success.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Qualifications:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Education \u0026amp;amp; Experience:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s degree in electrical engineering or equivalent.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;8+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Digital Design Expertise:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Architecture definition and micro-architecture development\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;RTL coding, functional simulation, and synthesis\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Timing closure and gate-level simulation (GLS)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Design for test (DFT) implementation\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Production experience with advanced CMOS nodes (≤7nm)\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Protocols \u0026amp;amp; Integration:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Deep expertise in at least one high-speed protocol—PCIe , Ethernet, Infiniband, DDR, or similar\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Third-party IP integration and verification.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Block-level design ownership from architecture through GDS\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Tools \u0026amp;amp; Methodologies:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Proficiency with Cadence and/or Synopsys digital design flows\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with UVM-based verification methodologies.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Silicon bring-up, debug, and failure analysis expertise\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Professional Attributes:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong work ethic with the ability to balance multiple priorities in a dynamic environment\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent communication and collaboration skills; comfortable working cross-functionally with global teams\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Self-directed learner who thrives with minimal supervision and adapts quickly to changing requirements\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Customer-focused mindset with ability to translate business needs into technical excellence\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Track record of delivering multiple high-performance designs to production in data-center environments\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on collaboration with embedded firmware teams; deep understanding of firmware development challenges and constraints\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with standard embedded processor subsystems (RISC-V, Arm, etc.)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven contributions to design methodology, CAD automation, or design infrastructure to improve productivity or design quality\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;p\u0026gt;The base salary range is $185,000.00 USD – $230,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184255005,"name":"Design Engineering CCE1","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4741719005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4458388005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"G\u0026A Management","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4741719005,"updated_at":"2026-10-07T22:17:03-04:00","requisition_id":null,"title":"Principal Ecosystem Partner Manager","company_name":"Astera Labs","first_published":"2026-10-07T21:55:48-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Learn more at \u0026lt;a href=\u0026quot;http://www.asteralabs.com/\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Are you passionate about building ecosystem partnerships that bring the next generation of AI infrastructure to market?\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;We are seeking a highly technical and experienced Principal Ecosystem Partner Manager to drive joint business growth, product adoption, and ecosystem innovation with leading CPU platform providers (x86 and Arm), ODMs, OEMs, and system integrators. This role owns strategic partner engagement end to end, from roadmap alignment and interoperability through agreements and co-marketing, and leads solutions and partner marketing for Astera Labs\u0026#39; rack-scale solutions. It works closely with Astera Labs sales, field applications engineering (FAE), product management, engineering, and corporate marketing teams.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This is a high-visibility role with regular interaction with executive leadership at Astera Labs and at our partners, and requires a strong blend of technical depth, market insight, and leadership. The ideal candidate has deep experience in server, AI, and cloud infrastructure, excels at cross-functional collaboration, and can translate complex technologies into compelling rack-scale solutions built on Astera Labs\u0026#39; Intelligent Connectivity Platform.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This position is based at Astera Labs\u0026#39; headquarters in San Jose, California, and requires in-person presence five days a week, with regular travel to partner sites, customer meetings, and industry events.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities \u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Own strategic relationships with key CPU platform partners (x86 and Arm, including emerging Arm-based platform providers), ODMs, OEMs, and system integrators, including monthly executive syncs, quarterly roadmap exchanges, and joint business planning\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive technology roadmap alignment to place Astera Labs products in partner reference designs and emerging server and AI platforms\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Coordinate interoperability and joint validation programs with partners and Astera Labs engineering, from early silicon through production\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with partners on joint reference architectures and rack-scale solutions built on Astera Labs\u0026#39; Intelligent Connectivity Platform, including emerging AI workloads such as agentic inference\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead solutions and partner marketing for rack-scale solution kits with ODM and OEM partners, including solution briefs, joint go-to-market plans, launch content, and partner programs\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Negotiate and close partner agreements, such as supplier, qualified vendor, and co-marketing agreements, with legal, sales, and business teams\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Plan and execute co-marketing programs with partners, including joint announcements, demos, events, case studies, and partner content\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Own the customer-facing presentations, including the company and portfolio overview decks, solution and partner decks, and event-specific decks, and keep them current across product groups\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Act as the Voice of the Partner, gathering partner and customer insights and competitive intelligence to influence product direction, platform strategy, and go-to-market execution\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop sales enablement on partner platforms and run regular training sessions with customer-facing teams\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Serve as an ecosystem evangelist internally and externally, representing Astera Labs at industry events, partner forums, conferences, and press/analyst engagements\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Track partner engagement and ecosystem-influenced design wins, and report progress to leadership\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Qualifications \u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor\u0026#39;s degree in Engineering or a related field; MBA preferred\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;7+ years of experience in product-focused, customer- or partner-facing roles within the semiconductor or data center infrastructure industry\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Understanding of PCIe, CXL, Ethernet, and/or UALink technologies and server/CPU platform architectures in AI and cloud infrastructure\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Established network across CPU, server platform, ODM, OEM, and system integrator ecosystems\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Previous experience in Ecosystem Partnerships, Solutions or Partner Marketing, Business Development, Product Marketing, Product Management, or similar roles\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience running multi-workstream partner programs, including joint interoperability, reference designs, and executive syncs\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong strategic thinking and analytical skills, with the ability to translate market insights into actionable partner and account strategies\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent communication and presentation skills, including building executive and customer-facing presentations that explain complex technical concepts clearly\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven ability to collaborate effectively with cross-functional teams and drive consensus in a fast-paced, dynamic environment\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Results-oriented mindset with a focus on driving measurable impact and achieving business objectives\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience negotiating and executing partner agreements\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Willingness to travel up to approximately 25% for partner/customer meetings, company training, industry events, and conferences\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p8i6j01 paragraph\u0026quot;\u0026gt;Salary range is $160,000 to $200,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184244005,"name":"Corporate Marketing","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4727465005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4451196005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":null,"value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4727465005,"updated_at":"2026-09-29T16:37:28-04:00","requisition_id":"2710","title":"Principal Electrical Engineer – Smart Cable Modules","company_name":"Astera Labs","first_published":"2026-08-27T17:04:17-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;table width=\u0026quot;648\u0026quot;\u0026gt;\n\u0026lt;tbody\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td width=\u0026quot;648\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;JOB DESCRIPTION\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Principal Electrical Engineer – Smart Cable Modules\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Active Copper Cable \u0026amp;amp; Pluggable Module Design\u0026amp;nbsp; |\u0026amp;nbsp; Hardware Engineering\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;/tbody\u0026gt;\n\u0026lt;/table\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;About the Role\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;We are looking for a Principal Electrical Engineer to take strategic ownership of our Smart Cable Module (SCM) hardware platform. This is a senior individual-contributor role that combines deep technical leadership with cross-organizational influence - you will define the electrical architecture of our next-generation active copper cable assemblies and pluggable modules in OSFP, QSFP-DD, and emerging form-factor enclosures targeting 400G, 800G, and beyond.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As a Principal Engineer you will set design direction, establish engineering standards, and serve as the primary technical authority on module hardware across the full product lifecycle - from concept and architecture through production release and sustaining engineering. You will partner with cross functional team, contract manufacturers, firmware teams, and hyperscale customers to deliver differentiated, high-reliability products for data center AI/ML fabric and high-performance computing applications.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Architecture \u0026amp;amp; Technical Leadership\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Define and own the end-to-end electrical architecture for smart cable modules, including SerDes channel topology, power delivery strategy, and thermal budgeting for muti-Gig (112G PAM4 and 56G NRZ ) designs\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Establish and maintain internal electrical design standards, PCB layout rules, and SI/PI guidelines that the broader hardware team\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead technical reviews (architecture, schematic, layout, DVT) and provide authoritative sign-off on high-speed digital designs\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Contribute to the module hardware roadmap in alignment with host ASIC platform generations, MSA form-factor evolution, and customer requirements\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Evaluate and select components; engage directly with supplier engineering teams on reference design adaptation and silicon bring-up support. \u0026lt;strong\u0026gt;\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Electrical Design Ownership\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Drive schematic capture and PCB design for complex multi-layer modules housing muti-Gig SerDes retimer or DSP ASICs in thermally and spatially constrained OSFP/QSFP-DD enclosures\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Own power delivery design including multi-rail regulation, hot-plug sequencing, brownout protection, and inrush management within MSA-defined power envelopes.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Review and recommendation on PCB stack-up, impedance targets, via structures, and differential-pair routing rules; review and approve layout execution with sufficient SI understanding to ensure first-pass compliance\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Define module management hardware architecture: I2C topology, register map implementation, microcontroller selection, and diagnostic monitoring interface circuitry\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Perform analog and mixed-signal sub-circuit design including clock distribution, oscillator selection, ESD protection, and supervisory logic\u0026amp;nbsp;\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Validation \u0026amp;amp; Bring-Up Leadership\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Author/co-author hardware bring-up strategies, debug plans, and acceptance test procedures for new module designs; lead or directly execute board bring-up.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Oversee firmware integration testing, control-interface validation, and module diagnostic monitoring verification\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead root-cause analysis on complex hardware failures; review failure analysis reports and implement changes.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Define and champion DFT/DFM strategies with CM and PCB fabrication partners to improve yield and reduce manufacturing cost\u0026amp;nbsp;\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional \u0026amp;amp; Organizational Impact\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with firmware and software teams to define initialization sequences, power management schemes, and real-time diagnostic algorithms\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Represent the organization in relevant MSA, and IEEE standards working groups; influence specification development in support of company product strategy\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Mentor and technically develop senior and mid-level engineers; elevate the hardware team\u0026#39;s collective capabilities in high-speed design\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Contribute to strategic hiring, technical onboarding, and department-level engineering process improvement\u0026amp;nbsp;\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s or Master’s degree in electrical engineering or closely related field;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;10-12+ years of progressive electrical engineering experience, with at least 5 years focused on high-speed SerDes-based interconnect, active copper cable, or optical/pluggable module products\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Demonstrated track record of architecting and delivering production hardware with 56G / 112G and faster SerDes interfaces (Ethernet, PCIe, or InfiniBand)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Expert-level understanding of signal integrity principles - impedance control, differential pair management, eye mask budgeting, channel loss allocation - sufficient to author design rules and review layout without performing full SI simulation\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency with EDA tools: industry-standard schematic capture (Cadence Allegro / OrCAD) and PCB layout review\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep familiarity with OSFP, QSFP-DD800, and SFP-DD MSA mechanical, electrical, and management specifications\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience with CMIS 5.x / SFF-8636 module management and I2C/MDIO interface design\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven ability to lead hardware bring-up and debug complex mixed-signal failures using high-bandwidth oscilloscopes and protocol analyzers\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong PDN design fundamentals: multi-rail sequencing, transient response, decoupling strategy, and thermal-electrical co-analysis\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience interfacing with silicon vendors/teams on customizing reference design, silicon errata management, and platform bring-up\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience at the architecture or lead engineer level on 800G or beyond module programs\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with co-packaged optics (CPO) or linear drive (LPO) module electrical architecture\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Working knowledge of host-side switching ASIC electrical interfaces and SerDes equalization schemes\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Participation in OIF, IEEE 802.3, or QSFP/OSFP MSA standards bodies\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with PCIe Gen 5/6 retimer module designs\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Scripting fluency in Python for lab automation, measurement data reduction, or hardware characterization workflows\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Base salary range is $185,000 to $240,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025526005,"name":"Hardware Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4730620005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4452837005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Design Verification","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4730620005,"updated_at":"2026-10-08T03:53:33-04:00","requisition_id":"2026-244","title":"Principal Emulation Engineer","company_name":"Astera Labs","first_published":"2026-09-09T14:01:55-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 1\u0026quot;\u0026gt;Principal Emulation Engineer — San Jose, CA\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335559738\u0026amp;quot;:360,\u0026amp;quot;335559739\u0026amp;quot;:80}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 2\u0026quot;\u0026gt;Role Overview\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335559738\u0026amp;quot;:160,\u0026amp;quot;335559739\u0026amp;quot;:80}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot; data-ccp-parastyle-defn=\u0026quot;{\u0026amp;quot;ObjectId\u0026amp;quot;:\u0026amp;quot;276295ed-5df2-5456-988c-5fdbab071054|1\u0026amp;quot;,\u0026amp;quot;ClassId\u0026amp;quot;:1073872969,\u0026amp;quot;Properties\u0026amp;quot;:[201342446,\u0026amp;quot;1\u0026amp;quot;,201342447,\u0026amp;quot;5\u0026amp;quot;,201342448,\u0026amp;quot;1\u0026amp;quot;,201342449,\u0026amp;quot;1\u0026amp;quot;,469777841,\u0026amp;quot;Aptos\u0026amp;quot;,469777842,\u0026amp;quot;Arial\u0026amp;quot;,469777843,\u0026amp;quot;Aptos\u0026amp;quot;,469777844,\u0026amp;quot;Aptos\u0026amp;quot;,201341986,\u0026amp;quot;1\u0026amp;quot;,469769226,\u0026amp;quot;Aptos,Arial\u0026amp;quot;,268442635,\u0026amp;quot;24\u0026amp;quot;,335559739,\u0026amp;quot;180\u0026amp;quot;,335559738,\u0026amp;quot;180\u0026amp;quot;,469775450,\u0026amp;quot;First Paragraph\u0026amp;quot;,201340122,\u0026amp;quot;2\u0026amp;quot;,134234082,\u0026amp;quot;true\u0026amp;quot;,134233614,\u0026amp;quot;true\u0026amp;quot;,469778129,\u0026amp;quot;FirstParagraph\u0026amp;quot;,335572020,\u0026amp;quot;1\u0026amp;quot;,469775498,\u0026amp;quot;Body Text\u0026amp;quot;,469778324,\u0026amp;quot;Body Text\u0026amp;quot;]}\u0026quot;\u0026gt;As a Principal Emulation Engineer, you will build and\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot;\u0026gt;operate\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot;\u0026gt;\u0026amp;nbsp;emulation environments that let verification teams stress-test complex ASICs before silicon.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot;\u0026gt;You’ll\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot;\u0026gt;\u0026amp;nbsp;partner closely with design, verification, firmware, and systems engineers to model hardware-software interactions, exercise high-speed protocols, and isolate issues across RTL, transactors, test environments, and code. Your hands-on leadership will turn difficult debug problems into actionable fixes and improve confidence in each product milestone.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:180,\u0026amp;quot;335559739\u0026amp;quot;:180}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Body Text\u0026quot;\u0026gt;Astera Labs is accelerating the infrastructure behind AI by delivering purpose-built connectivity solutions for rack-scale systems. In this role,\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Body Text\u0026quot;\u0026gt;you’ll\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Body Text\u0026quot;\u0026gt;\u0026amp;nbsp;help\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Body Text\u0026quot;\u0026gt;validate\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Body Text\u0026quot;\u0026gt;\u0026amp;nbsp;the switching, PCIe, Ethernet, memory, and storage interfaces that\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Body Text\u0026quot;\u0026gt;connect\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Body Text\u0026quot;\u0026gt;\u0026amp;nbsp;the\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Body Text\u0026quot;\u0026gt;compute\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Body Text\u0026quot;\u0026gt;\u0026amp;nbsp;fabric—enabling faster bring-up, stronger interoperability, and more reliable platforms as the company scales.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:180,\u0026amp;quot;335559739\u0026amp;quot;:180}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 2\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335559738\u0026amp;quot;:160,\u0026amp;quot;335559739\u0026amp;quot;:80}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;0\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Emulation and Prototyping\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;0\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot; data-ccp-parastyle-defn=\u0026quot;{\u0026amp;quot;ObjectId\u0026amp;quot;:\u0026amp;quot;eafb41c0-47a4-52dc-ac6b-3b5a7536b560|1\u0026amp;quot;,\u0026amp;quot;ClassId\u0026amp;quot;:1073872969,\u0026amp;quot;Properties\u0026amp;quot;:[201342446,\u0026amp;quot;1\u0026amp;quot;,201342447,\u0026amp;quot;5\u0026amp;quot;,201342448,\u0026amp;quot;1\u0026amp;quot;,201342449,\u0026amp;quot;1\u0026amp;quot;,469777841,\u0026amp;quot;Aptos\u0026amp;quot;,469777842,\u0026amp;quot;Arial\u0026amp;quot;,469777843,\u0026amp;quot;Aptos\u0026amp;quot;,469777844,\u0026amp;quot;Aptos\u0026amp;quot;,201341986,\u0026amp;quot;1\u0026amp;quot;,469769226,\u0026amp;quot;Aptos,Arial\u0026amp;quot;,268442635,\u0026amp;quot;24\u0026amp;quot;,335559739,\u0026amp;quot;36\u0026amp;quot;,335559738,\u0026amp;quot;36\u0026amp;quot;,469775450,\u0026amp;quot;Compact\u0026amp;quot;,201340122,\u0026amp;quot;2\u0026amp;quot;,134234082,\u0026amp;quot;true\u0026amp;quot;,134233614,\u0026amp;quot;true\u0026amp;quot;,469778129,\u0026amp;quot;Compact\u0026amp;quot;,335572020,\u0026amp;quot;1\u0026amp;quot;,469778324,\u0026amp;quot;Body Text\u0026amp;quot;]}\u0026quot;\u0026gt;Architect, build, and\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;maintain\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;\u0026amp;nbsp;emulation environments for complex ASICs and SoCs.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Integrate RTL, transactors, protocol models, software, and test infrastructure to enable meaningful\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;hardware-software\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;\u0026amp;nbsp;co-simulation.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Enable verification teams to stress-test designs with scalable, repeatable emulation workflows.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Develop reusable models, utilities, and debug methodologies that accelerate pre-silicon validation.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Protocol and SoC Verification\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;0\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Verify\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;hardware-software\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;\u0026amp;nbsp;interfaces and system behaviors in partnership with logic designers, firmware engineers, and verification teams.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Exercise and debug PCI Express Gen 3 and above, Ethernet, DDR,\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;NVMe\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;, SPI, I2C/I3C, and similar interfaces.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Analyze protocol behavior, functional coverage, performance, and corner cases across complex\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;server\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;, storage, and networking systems.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Translate system requirements into practical emulation scenarios, tests, checkers, and measurable verification goals.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Debug and Technical Leadership\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;0\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Debug design, environment, transactor, software, and test-code issues across the emulation stack.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Identify\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;\u0026amp;nbsp;software and hardware co-simulation limitations and apply effective isolation and debug techniques.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Partner with cross-functional teams to prioritize a dynamic workload, resolve issues quickly, and drive risks to closure.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Provide technical leadership, communicate clearly, and\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;operate\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;\u0026amp;nbsp;effectively with minimal guidance and supervision.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 2\u0026quot;\u0026gt;Basic Qualifications\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335559738\u0026amp;quot;:160,\u0026amp;quot;335559739\u0026amp;quot;:80}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Bachelor’s degree in Electrical Engineering\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;, Computer Engineering, Computer Science, or\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;a related\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;\u0026amp;nbsp;technical field.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;8–12 years of experience supporting or developing complex SoC or silicon products for server, storage, or networking applications.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Experience working with logic designers to architect, specify, and verify hardware-software interfaces on complex SoCs.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Working knowledge of PCI Express Gen 3 or later, CXL,\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;UALink\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;, Ethernet, DDR,\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;NVMe\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;, SPI, I2C/I3C, or similar communication protocols.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;7\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;High\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;proficiency\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;\u0026amp;nbsp;in\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;SystemVerilog\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;\u0026amp;nbsp;and hardware verification environments.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;8\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Experience understanding software and hardware co-simulation limitations and applying effective debug methods.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;9\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Programming and scripting experience in Python, Perl, C, or similar languages.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;10\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Professional\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;, entrepreneurial, and open-minded approach with a can-do attitude, strong prioritization skills, and a customer-focused mindset.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;11\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Authorized to work in the United States and available to start\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;immediately\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 2\u0026quot;\u0026gt;Preferred Qualifications\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335559738\u0026amp;quot;:160,\u0026amp;quot;335559739\u0026amp;quot;:80}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;12\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Master’s degree in Electrical Engineering\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;, Computer Engineering, Computer Science, or\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;a related\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;\u0026amp;nbsp;technical field.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;13\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Hands-on experience with Palladium, Zebu, Veloce, HAPS, FPGA prototyping, or similar emulation and prototyping technologies.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;14\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Experience developing models for emulation and prototyping and working in non-UVM verification environments.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;15\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Experience building protocol transactors, behavioral models, software drivers, or system-level validation infrastructure.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;16\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Based in the San Jose area or open to relocation; comfortable working fully in person.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot;\u0026gt;Salary range is $207,000 to $230,000 depending on experience, level, and business\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot;\u0026gt;need\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot;\u0026gt;. This role may be eligible for discretionary\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot;\u0026gt;bonus\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot;\u0026gt;,\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot;\u0026gt;incentives\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot;\u0026gt;\u0026amp;nbsp;and benefits.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:180,\u0026amp;quot;335559739\u0026amp;quot;:180}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184209005,"name":"Advanced DV \u0026 Emulation CCE1","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4600077005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4390181005,"location":{"name":"San Jose, CA"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Design Verification","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4600077005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"1906","title":"Principal Emulation Engineer","company_name":"Astera Labs","first_published":"2025-09-09T19:59:51-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;We are looking for a Principal Emulation Engineer with hands-on experience verifying protocols on complex ASICs and experience with or interest in emulation. \u0026amp;nbsp;The ideal candidate would be at ease creating environments to enable verification teams to stress test ASICs, as well as debugging design, environment, transactor, and code issues. \u0026amp;nbsp;The candidate must have good knowledge of communication protocols such as PCI-Express (Gen-3 and above), DDR, Ethernet, NVMe, or similar interfaces.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Basic qualifications:\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong academic and technical background in computer/electrical engineering. At a minimum, a Bachelor’s in EE or Computer Science is required, and a Master’s is preferred.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;≥8 years’ experience supporting or developing complex SoC/silicon products for Server, Storage or Networking applications.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience working with logic designers to architect, specify, and verify hardware-software interfaces on complex SoCs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Professional attitude with the ability to prioritize a dynamic list of multiple tasks and to work with minimal guidance and supervision.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Authorized to work in the US and start immediately.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Required experience:\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Working knowledge of PCIe, Ethernet, DDR, SPI, I2C/I3C or similar protocols.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;High level of proficiency in System Verilog and verification environments.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience understanding software and hardware co-simulation limitations and debug methods.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience in programming and scripting languages (like perl/python/C).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Currently based locally or open to relocation.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Preferred experience:\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience in emulation and prototyping technologies like Palladium/Zebu/Veloce or HAPS and FPGA prototyping.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience in modeling for emulation and prototyping, and/or non-UVM environments\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;p\u0026gt;The base salary range is $209,000.00 USD – $230,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.\u0026amp;nbsp;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4715784005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4445303005,"location":{"name":"Tel Aviv-Yafo, Tel Aviv District, Israel"},"metadata":[{"id":12122734005,"name":"Country","value":"Israel","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Haifa","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Design Verification","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4715784005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":null,"title":"Principal Emulation Engineer","company_name":"Astera Labs","first_published":"2026-07-16T07:02:06-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is establishing a strategic R\u0026amp;amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical \u0026#39;data bottlenecks\u0026#39; enabling the future of AI at scale. As we expand our presence in Israel, we\u0026#39;re seeking a talented \u0026lt;strong\u0026gt;Principal Emulation Engineer\u0026lt;/strong\u0026gt; to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, implementing the emulation strategy for chips that power the world\u0026#39;s largest AI clusters.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As an\u0026amp;nbsp;\u0026lt;strong\u0026gt;Principal \u0026lt;/strong\u0026gt;\u0026lt;strong\u0026gt;Emulation Engineer\u0026lt;/strong\u0026gt;, you will be a core technical driver of our Israel R\u0026amp;amp;D center, working at the intersection of hardware and software to ensure our silicon meets extreme quality and performance targets. You will execute end-to-end emulation flows, bridge the gap between RTL and functional validation, and partner with cross-functional teams to enable seamless hardware-software integration. If you thrive on solving complex technical challenges and want to play a key role in validating cutting-edge AI infrastructure connectivity solutions, this is your opportunity.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Emulation Flow Execution \u0026amp;amp; Implementation\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Execute end-to-end emulation flow from high-level model generation and RTL synthesis to complex system-level testing and silicon-accurate debugging\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Work directly with next-generation emulation platforms (Zebu, Palladium, or Veloce) to implement cutting-edge methodologies\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Maintain and evolve emulation flows to reduce compile times and increase execution speed, directly impacting time-to-market\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;System-Level Debug \u0026amp;amp; Validation\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Drive initial model bring-up process in high-stakes environment, identifying and resolving complex bugs\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Ensure rapid cycles from RTL to functional stability through systematic debug approaches\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Own technical blocks and drive them to completion independently\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional Collaboration\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Partner with Firmware, Software, and Validation teams to debug complex system-level scenarios\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Ensure seamless hardware-software integration for AI infrastructure connectivity\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Collaborate with Design and Verification teams to optimize emulation strategies\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, Computer Engineering, or related technical field\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;10+ years of hands-on experience in Emulation at semiconductor companies\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Deep expertise in emulation flows for large-scale chips using industry-standard emulators (Zebu, Palladium, or Veloce)\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Strong background in SystemVerilog for developing, testing, and debugging complex SoC designs\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience developing and maintaining execution flows for building, running, and debugging emulation models\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\u0026quot;Can-do\u0026quot; approach with ability to own technical blocks and drive them to completion independently\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Master\u0026#39;s degree in Electrical Engineering, Computer Engineering, or related field\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Familiarity with EDA tools for Lint, Clock Domain Crossing (CDC), simulation, and synthesis\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Proficiency in scripting languages such as Python or TCL for automation and flow enhancement\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience with standard debug environments (e.g., Verdi)\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Knowledge of high-speed interface protocols (PCIe, Ethernet, CXL, UALink)\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Background in hardware-software co-verification methodologies\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184260005,"name":"Design Verification CCE2","child_ids":[],"parent_id":null}],"offices":[{"id":4052111005,"name":"Haifa","location":"Israel","child_ids":[],"parent_id":4008937005},{"id":4056876005,"name":"Tel Aviv","location":"Israel","child_ids":[],"parent_id":4008937005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4728939005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4447237005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Program Management","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4728939005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2026-374","title":"Principal Engineering Program Manager (EPM)","company_name":"Astera Labs","first_published":"2026-08-28T18:19:19-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;h1 class=\u0026quot;wnfdnti _1ibi0s33y _1ibi0s34u\u0026quot; data-pm-slice=\u0026quot;1 1 []\u0026quot;\u0026gt;Principal Engineering Program Manager, (EPM)\u0026lt;/h1\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Location:\u0026lt;/strong\u0026gt; San Jose, CA (Onsite)\u0026lt;/p\u0026gt;\n\u0026lt;h2 class=\u0026quot;wnfdnti _1ibi0s33y _1ibi0s34u\u0026quot;\u0026gt;Role Overview\u0026lt;/h2\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;As a Principal Engineering Program Manager on our Analog/Mixed-Signal (AMS) team, you will drive the execution of the complex silicon programs that power Astera Labs\u0026#39; purpose-built connectivity solutions. You\u0026#39;ll orchestrate multi-disciplinary teams — spanning circuit design, layout, verification, and silicon validation — to deliver high-performance AMS IP on schedule, on budget, and to spec.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;This is a high-impact leadership role at a hyper-growth company defining the connectivity backbone of the AI era. You\u0026#39;ll own program plans from concept through tape-out and silicon bring-up, surface and resolve cross-functional risks, and bring the operational rigor that turns ambitious engineering into products shipping at rack scale. Your ability to align stakeholders and keep fast-moving programs on track will be central to Astera\u0026#39;s continued momentum.\u0026lt;/p\u0026gt;\n\u0026lt;h2 class=\u0026quot;wnfdnti _1ibi0s33y _1ibi0s34u\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/h2\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdntf\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Program Planning \u0026amp;amp; Execution\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdntf\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Define, drive, and maintain end-to-end program schedules for AMS IP development, from specification through tape-out and validation\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Manage critical path, milestones, and dependencies across circuit design, layout, verification, and silicon bring-up\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Establish and track program metrics, budgets, and deliverables to ensure predictable, high-quality outcomes\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional Leadership\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdntf\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Partner with AMS design, digital, systems, product, and operations teams to align priorities and resolve blockers\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Lead program reviews, drive decision-making, and communicate status, risks, and trade-offs to leadership and stakeholders\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Coordinate with external partners, foundries, and vendors on tape-out readiness and schedule commitments\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Risk Management \u0026amp;amp; Process Excellence\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdntf\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Proactively identify, quantify, and mitigate technical and schedule risks across concurrent programs\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Drive continuous improvement of program management processes, tools, and best practices for AMS execution\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Champion clear documentation, accountability, and operational discipline across the program lifecycle\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h2 class=\u0026quot;wnfdnti _1ibi0s33y _1ibi0s34u\u0026quot;\u0026gt;Basic Qualifications\u0026lt;/h2\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdntf\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, Computer Engineering, or a related technical field\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;8+ years of experience in program or project management within semiconductor, IC, or hardware development\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Proven track record managing complex silicon or AMS/IP programs through tape-out and silicon validation\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Strong understanding of the ASIC/IC development lifecycle, including design, verification, layout, and bring-up\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Excellent stakeholder management, communication, and cross-functional leadership skills\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Proficiency with program management and collaboration tools (e.g., Microsoft Project, Microsoft 365)\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h2 class=\u0026quot;wnfdnti _1ibi0s33y _1ibi0s34u\u0026quot;\u0026gt;Preferred Qualifications\u0026lt;/h2\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdntf\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;MS in Electrical Engineering, Computer Engineering, or a related field\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Direct experience with analog/mixed-signal or high-speed connectivity programs\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;PMP certification or equivalent program management credential\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Familiarity with foundry engagement, tape-out flows, and vendor/IP coordination\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Ability to thrive and lead through ambiguity in a fast-paced, hyper-growth environment\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Salary range is $160,000 to $200,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p8i6j01 paragraph\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184387005,"name":"Program Management AMS","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4736478005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4455630005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Validation Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4736478005,"updated_at":"2026-09-30T13:41:21-04:00","requisition_id":"2026-336","title":"Principal Engineer - Validation Engineering","company_name":"Astera Labs","first_published":"2026-09-30T13:41:21-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;h3\u0026gt;Role Overview\u0026lt;/h3\u0026gt;\n\u0026lt;p\u0026gt;As a \u0026lt;strong\u0026gt;Principal Engineer in Hardware Engineering\u0026#39;s Validation Engineering\u0026lt;/strong\u0026gt; organization, you will define and lead validation strategies for Astera Labs\u0026#39; next-generation connectivity products. You will turn complex silicon, board, and system requirements into rigorous plans, scalable automation, and clear release decisions—ensuring products perform reliably in the demanding environments of modern AI infrastructure.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This role combines deep hands-on technical leadership with broad cross-functional influence. You will partner with design, firmware, software, product, applications, and customer teams to bring up platforms, isolate issues, and accelerate qualification. Your work will directly support Astera Labs\u0026#39; hyper-growth mission to enable purpose-built, rack-scale AI connectivity and help customers deploy high-performance systems with confidence.\u0026lt;/p\u0026gt;\n\u0026lt;h3\u0026gt;Key Responsibilities\u0026lt;/h3\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Validation Strategy and Planning\u0026lt;/strong\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Define validation methodologies, coverage goals, schedules, dependencies, and exit criteria for complex hardware and connectivity products.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Translate product requirements and architecture specifications into comprehensive validation plans, test cases, and measurable quality objectives.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Identify technical risks early, prioritize validation investments, and communicate readiness, gaps, and tradeoffs to cross-functional stakeholders.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Lab, Automation, and Execution\u0026lt;/strong\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Lead silicon, board, and system bring-up, including test environment definition, instrumentation selection, configuration, and execution.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Architect scalable lab infrastructure and automated test frameworks that improve coverage, repeatability, debug efficiency, and time to qualification.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop, review, and maintain Python-based automation and data analysis tools in Linux-based validation environments.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Debug, Qualification, and Technical Leadership\u0026lt;/strong\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Drive root-cause analysis of functional, performance, interoperability, reliability, and system-level issues across hardware, firmware, and software boundaries.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Partner with design, firmware, software, product, applications, and customer teams to resolve issues and deliver high-quality releases.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Mentor engineers, establish validation best practices, and represent validation status and technical recommendations in design and launch reviews.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h3\u0026gt;Basic Qualifications\u0026lt;/h3\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, Computer Engineering, or a related technical field.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;8-12 years of experience in hardware, silicon, system, or product validation engineering.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven experience leading validation for semiconductor, networking, connectivity, or data center products.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience creating validation plans, test cases, automation, coverage metrics, and release criteria.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong debugging skills across hardware, firmware, software, and laboratory instrumentation.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent written and verbal communication skills, with the ability to influence technical decisions across functions.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h3\u0026gt;Preferred Qualifications\u0026lt;/h3\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Master\u0026#39;s or PhD degree in Electrical Engineering, Computer Engineering, or a related field.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience validating high-speed connectivity interfaces such as PCIe, CXL, Ethernet, or comparable technologies.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Understanding of physical-layer fundamentals, signal integrity, protocol analysis, compliance, and interoperability testing.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency with Python, Linux, laboratory equipment, data analysis, and Microsoft Azure DevOps or comparable validation infrastructure.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience scaling validation labs, working with hyperscalers or ODMs, and mentoring engineers in a fast-paced, high-growth environment.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Salary range is $185,000 to $240,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184210005,"name":"Advanced Hardware Engineering","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4696806005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_optional","internal_job_id":4425617005,"location":{"name":"Taipei, Taiwan"},"metadata":[{"id":12122734005,"name":"Country","value":"Taiwan","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Taipei","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Field Applications Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4696806005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2387","title":"Principal Field Applications Engineer","company_name":"Astera Labs","first_published":"2026-05-19T00:30:28-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;As an Astera Labs Principal Field Applications Engineer, you will support the world’s leading cloud service providers, server and network OEMs by working with them to design solutions that use Astera Labs’ portfolio of connectivity products. In this role, you will need to identify and understand customer requirements, propose Astera Labs solutions that provide clear value to the customer and provide hands-on design-in support. You will drive innovation by listening to the customer requirements, working with our engineering teams to implement into the product roadmap and delivering the results back to the customer.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026amp;nbsp;Basic qualifications:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;BS in electrical engineering. Master’s degree in engineering is preferred.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Minimum of 8 years’ experience working with Cloud service providers and server OEM customers to design in complex SoC/silicon products for Server, Storage, and/or Networking applications.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Customer-oriented, Goal-driven, Self-motivated, be able to work independently and be able to travel frequently to customer sites\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Fluent in Mandarin and English\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Entrepreneurial, open-mind behavior and can-do attitude. Think and act with the customer in mind!\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required experience:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Hands-on, thorough knowledge of high-speed protocols like PCIe \u0026amp;amp; Ethernet\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Silicon/System bring-up and debug experience in customer systems.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with lab equipment including protocol analyzers and oscilloscopes.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;A strong background in high-speed board design techniques, and understanding of Data Center systems like Servers, JBOGs/JBODs, Networking switches/routers etc.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Intermediate level of proficiency in Python for automating system validation and link optimization.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Able to step through embedded firmware at the SerDes (SoC) or MCU level for debugging.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Firsthand experience with lab equipment including traffic generators, analyzers, and high-speed oscilloscopes.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Business travel to Asia and the North America region may be required as needed.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred experience:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong working knowledge of a high speed interface at a physical layer level, associated standards, and debug. Most recent experience with 12G NRZ signaling at a minimum, some experience with 25G NRZ/56G PAM4 preferred.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Development, support, and experience with PCIe ICs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience in embedded SW debug or development with firmware, drivers, and BIOS using PCIe technology.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4134751005,"name":"Field Applications","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4009035005,"name":"Taipei","location":"Taiwan","child_ids":[],"parent_id":4002874005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4737460005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4456180005,"location":{"name":"Shanghai Shi, China"},"metadata":[{"id":12122734005,"name":"Country","value":"China","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Shanghai","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Field Applications Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4737460005,"updated_at":"2026-09-23T23:53:50-04:00","requisition_id":null,"title":"Principal Field Applications Engineer","company_name":"Astera Labs","first_published":"2026-09-23T23:53:50-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;h4\u0026gt;Job Description\u0026lt;/h4\u0026gt;\n\u0026lt;p\u0026gt;As an Astera Labs Senior FAE, you will establish yourself as trusted technical advisor to the world’s leading cloud service providers, server and network OEMs by working with them to design solutions that use Astera Labs’ portfolio of connectivity products. In this role, you will need to identify and understand customer requirements, propose Astera Labs solutions that provide clear value to the customer and provide hands-on design-in support. You will drive innovation by gathering customer requirements, defining new products and working with some of the brightest engineers in the industry.\u0026lt;/p\u0026gt;\n\u0026lt;h4\u0026gt;Basic qualifications\u0026lt;/h4\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;BS in electrical engineering. Master’s degree in engineering is preferred.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Minimum of 8 years’ experience working with Cloud service providers and server OEM customers to design in complex SoC/silicon products for Server, Storage, and/or Networking applications.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong organization skills and ability to provide clear and condensed notes and actions.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Customer-oriented, Goal-driven, Self-motivated, be able to work independently and be able to travel frequently to customer sites\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Fluent in Mandarin and English\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Entrepreneurial, open-mind behavior and can-do attitude. Think and act with the customer in mind!\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h4\u0026gt;Required experience\u0026lt;/h4\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Hands-on, thorough knowledge of high-speed protocols like PCIe, Ethernet, Infiniband, DDR, NVMe, USB, etc.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Silicon/System bring-up and debug experience in customer systems.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with lab equipment including protocol analyzers and oscilloscopes.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;A strong background in high-speed board design techniques, and understanding of Data Center systems like Servers, JBOGs/JBODs, Networking switches/routers etc.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Intermediate level of proficiency in Python for automating system validation and link optimization.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Able to step through embedded firmware at the SerDes (SoC) or MCU level for debugging.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h4\u0026gt;Preferred experience\u0026lt;/h4\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong working knowledge of a high speed interface at a physical layer level, associated standards, and debug. Most recent experience with 12G NRZ signaling at a minimum, some experience with 25G NRZ/56G PAM4 preferred.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Development, support, and experience with PCIe ICs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience in embedded SW debug or development with firmware, drivers, and BIOS using PCIe technology\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Working knowledge of software/firmware build environments, gcc/Make and GitHub.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of simulation/modeling, schematic capture, and PCB layout tools from Cadence, Altium and others etc.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of simulation tools such as Keysight ADS, Mathworks QCD, etc. for IBIS-AMI analysis.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4134751005,"name":"Field Applications","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4002875005,"name":"China","location":"China","child_ids":[4002876005,4061056005,4002878005,4009038005,4002877005],"parent_id":null}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4739524005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4457262005,"location":{"name":"Toronto, Ontario, Canada"},"metadata":[{"id":12122734005,"name":"Country","value":"Canada","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Toronto","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Firmware/Software Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4739524005,"updated_at":"2026-10-07T14:31:51-04:00","requisition_id":"2026-003","title":"Principal FW/SW Engineer","company_name":"Astera Labs","first_published":"2026-10-05T13:58:01-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 1\u0026quot;\u0026gt;Principal Engineer – Embedded Firmware \u0026amp;amp; Software\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335559738\u0026amp;quot;:360,\u0026amp;quot;335559739\u0026amp;quot;:80}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot; data-ccp-parastyle-defn=\u0026quot;{\u0026amp;quot;ObjectId\u0026amp;quot;:\u0026amp;quot;276295ed-5df2-5456-988c-5fdbab071054|1\u0026amp;quot;,\u0026amp;quot;ClassId\u0026amp;quot;:1073872969,\u0026amp;quot;Properties\u0026amp;quot;:[201342446,\u0026amp;quot;1\u0026amp;quot;,201342447,\u0026amp;quot;5\u0026amp;quot;,201342448,\u0026amp;quot;1\u0026amp;quot;,201342449,\u0026amp;quot;1\u0026amp;quot;,469777841,\u0026amp;quot;Aptos\u0026amp;quot;,469777842,\u0026amp;quot;Arial\u0026amp;quot;,469777843,\u0026amp;quot;Aptos\u0026amp;quot;,469777844,\u0026amp;quot;Aptos\u0026amp;quot;,201341986,\u0026amp;quot;1\u0026amp;quot;,469769226,\u0026amp;quot;Aptos,Arial\u0026amp;quot;,268442635,\u0026amp;quot;24\u0026amp;quot;,335559739,\u0026amp;quot;180\u0026amp;quot;,335559738,\u0026amp;quot;180\u0026amp;quot;,469775450,\u0026amp;quot;First Paragraph\u0026amp;quot;,201340122,\u0026amp;quot;2\u0026amp;quot;,134234082,\u0026amp;quot;true\u0026amp;quot;,134233614,\u0026amp;quot;true\u0026amp;quot;,469778129,\u0026amp;quot;FirstParagraph\u0026amp;quot;,335572020,\u0026amp;quot;1\u0026amp;quot;,469775498,\u0026amp;quot;Body Text\u0026amp;quot;,469778324,\u0026amp;quot;Body Text\u0026amp;quot;]}\u0026quot;\u0026gt;Location: Toronto or Ottawa, Ontario (Remote)\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026amp;nbsp;\u0026lt;br\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot;\u0026gt;Travel: Occasional travel to Astera Labs’ San Jose headquarters, \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot;\u0026gt;approximately twice\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot;\u0026gt; per year, for chip bring-up and project coordination\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026amp;nbsp;\u0026lt;br\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot;\u0026gt;Employment: Full-time\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:180,\u0026amp;quot;335559739\u0026amp;quot;:180}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Body Text\u0026quot;\u0026gt;Role Overview\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:180,\u0026amp;quot;335559739\u0026amp;quot;:180}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Body Text\u0026quot;\u0026gt;Join Astera Labs’ Signal Connectivity Engineering team as a Principal \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Body Text\u0026quot;\u0026gt;Engineer\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Body Text\u0026quot;\u0026gt; shaping the firmware and software that makes advanced connectivity products adaptive, reliable, and \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Body Text\u0026quot;\u0026gt;production-ready\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Body Text\u0026quot;\u0026gt;. You will own embedded software across analog connectivity and Ethernet \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Body Text\u0026quot;\u0026gt;retimer\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Body Text\u0026quot;\u0026gt; platforms, from low-level hardware abstraction and calibration through link management, diagnostics, validation, and customer deployment.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:180,\u0026amp;quot;335559739\u0026amp;quot;:180}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Body Text\u0026quot;\u0026gt;This is a high-impact role at the intersection of embedded systems, mixed-signal hardware, and Ethernet physical-layer behavior. You will work across architecture, lab debug, automation, and customer integration while partnering with silicon, analog, systems, validation, and applications teams. Your work will help deliver purpose-built connectivity for rack-scale AI infrastructure as Astera Labs continues to scale.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:180,\u0026amp;quot;335559739\u0026amp;quot;:180}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Body Text\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:180,\u0026amp;quot;335559739\u0026amp;quot;:180}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Firmware Architecture \u0026amp;amp; Product Ownership\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;0\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot; data-ccp-parastyle-defn=\u0026quot;{\u0026amp;quot;ObjectId\u0026amp;quot;:\u0026amp;quot;eafb41c0-47a4-52dc-ac6b-3b5a7536b560|1\u0026amp;quot;,\u0026amp;quot;ClassId\u0026amp;quot;:1073872969,\u0026amp;quot;Properties\u0026amp;quot;:[201342446,\u0026amp;quot;1\u0026amp;quot;,201342447,\u0026amp;quot;5\u0026amp;quot;,201342448,\u0026amp;quot;1\u0026amp;quot;,201342449,\u0026amp;quot;1\u0026amp;quot;,469777841,\u0026amp;quot;Aptos\u0026amp;quot;,469777842,\u0026amp;quot;Arial\u0026amp;quot;,469777843,\u0026amp;quot;Aptos\u0026amp;quot;,469777844,\u0026amp;quot;Aptos\u0026amp;quot;,201341986,\u0026amp;quot;1\u0026amp;quot;,469769226,\u0026amp;quot;Aptos,Arial\u0026amp;quot;,268442635,\u0026amp;quot;24\u0026amp;quot;,335559739,\u0026amp;quot;36\u0026amp;quot;,335559738,\u0026amp;quot;36\u0026amp;quot;,469775450,\u0026amp;quot;Compact\u0026amp;quot;,201340122,\u0026amp;quot;2\u0026amp;quot;,134234082,\u0026amp;quot;true\u0026amp;quot;,134233614,\u0026amp;quot;true\u0026amp;quot;,469778129,\u0026amp;quot;Compact\u0026amp;quot;,335572020,\u0026amp;quot;1\u0026amp;quot;,469778324,\u0026amp;quot;Body Text\u0026amp;quot;]}\u0026quot;\u0026gt;Own the embedded firmware stack from hardware abstraction and device drivers through management interfaces, diagnostics, and customer-facing APIs.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Design firmware for adaptive equalization, gain control, calibration, link training, PLL/CDR feedback, thermal management, and device telemetry.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Architect control algorithms, state machines, and tuning flows that manage analog and high-speed interfaces across process, voltage, and temperature variation.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Define software quality gates, validation criteria, and release practices from pre-silicon planning through production deployment.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Ethernet, Lab Debug \u0026amp;amp; System Integration\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;0\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Debug firmware behavior across Ethernet configurations, link states, and failure modes by tracing interactions among Layer 1 PHY, SERDES, FEC/PCS, MAC, \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;retimer\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;, and gearbox components.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Investigate register accesses, embedded SDK behavior, link state machines, PHY telemetry, logs, and real-hardware measurements to \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;identify\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; root causes and deliver targeted fixes.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Partner with system validation to develop test plans, automate characterization flows, and verify firmware across corner cases and product configurations.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Support \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;customer\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; bring-up, field issue triage, and deployment readiness in collaboration with applications, \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;platform\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;, and silicon teams.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Technical Leadership \u0026amp;amp; Collaboration\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;0\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Set technical direction, lead architecture and tradeoff discussions, and balance performance, code size, maintainability, and time to market.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Serve as a technical authority for mixed-signal firmware, analog control behavior, Ethernet physical-layer debug, and hardware/software integration.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Lead design reviews, implementation, code reviews, and difficult debug efforts across firmware, analog, silicon, systems, validation, and applications teams.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Mentor engineers and help build the team through recruiting, onboarding, and technical development; \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;people\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; management or a senior technical-lead path may be available as the organization grows.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot;\u0026gt;Basic Qualifications\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:180,\u0026amp;quot;335559739\u0026amp;quot;:180}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Bachelor’s degree in Computer Science\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;, Electrical Engineering, Computer Engineering, or \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;a related\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; field.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;8–12 years of experience developing embedded firmware or software for resource-constrained systems, with ownership from architecture through production.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; 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data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Hands-on experience with Ethernet or high-speed connectivity devices, including Layer 1 PHYs, SERDES, \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;retimers\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;, gearboxes, NICs, switches, or related systems.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; 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drivers, CTLE/DFE equalization, CDR/PLL circuits, or thermal control.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; 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data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;15\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Experience using oscilloscopes, BERTs, logic analyzers, and other lab equipment; familiarity with FPGA emulation, pre-silicon validation, RTOS, device drivers, coroutines, mentoring, or recruiting.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot;\u0026gt;Salary range is CAD $184,500 to CAD $205,000 depending on experience, level, and business \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot;\u0026gt;need\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot;\u0026gt;. This role may be eligible for discretionary \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot;\u0026gt;bonus\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot;\u0026gt;, \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot;\u0026gt;incentives\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot;\u0026gt; and benefits.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:180,\u0026amp;quot;335559739\u0026amp;quot;:180}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184368005,"name":"Firmware \u0026 Software SCE","child_ids":[],"parent_id":null}],"offices":[{"id":4000119005,"name":"Toronto","location":"Canada","child_ids":[],"parent_id":4004709005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4736480005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4455632005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Program Management","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4736480005,"updated_at":"2026-10-05T16:58:00-04:00","requisition_id":"2026-548","title":"Principal Hardware NPI Program Manager","company_name":"Astera Labs","first_published":"2026-10-05T16:58:00-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;h2\u0026gt;Role Overview\u0026lt;/h2\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is seeking a Principal Engineering, Hardware NPI Program Manager to lead complex hardware programs from design release through productization, validation, customer readiness, and launch. This highly visible role combines technical NPI expertise with cross-functional program leadership to deliver purpose-built connectivity solutions for rack-scale AI infrastructure.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;You will bring structure to programs spanning product, hardware, systems, manufacturing, operations, supply chain, quality, finance, and customer-facing teams. You will own integrated plans, dependencies, risks, decisions, and outcomes while driving accountability across a fast-moving, globally distributed organization. Your work will turn engineering intent into predictable, customer-ready hardware and help Astera scale new connectivity platforms with speed, quality, and confidence.\u0026lt;/p\u0026gt;\n\u0026lt;h2\u0026gt;Key Responsibilities\u0026lt;/h2\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;NPI Program Planning and Execution\u0026lt;/strong\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Define PCBA program schedules, build quantities, milestones, budgets, dependencies, and readiness criteria from concept through launch.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead prototype and new-product builds through PCB and PCBA fabrication, assembly, bring-up, validation, shipment readiness, and launch.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Establish readiness reviews, decision forums, dashboards, and escalation paths that keep teams aligned.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop recovery recommendations when material shortages, engineering changes, supplier constraints, or other risks threaten delivery.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional Product Execution\u0026lt;/strong\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Align product, hardware, systems, validation, manufacturing, quality, supply chain, finance, operations, and customer-facing teams around shared outcomes.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Identify blockers early, assign accountable owners, drive decisions to closure, and escalate issues with clear recommendations.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Communicate concise, decision-oriented updates to technical teams, senior leaders, executives, customers, contract manufacturers, and external partners.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Manufacturing Readiness and Supplier Leadership\u0026lt;/strong\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Confirm that bill of materials, part numbers, fabrication and assembly data, suppliers, work instructions, deviations, engineering changes, and approvals are complete before each build.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Highlight and resolve manufacturing issues involving component sourcing, design for manufacturability, programming, assembly, rework, traceability, and hardware logistics.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Serve as a primary program and technical contact for contract manufacturers, rework providers, and other external partners while maintaining accountability for commitments.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Operational Excellence and Team Enablement\u0026lt;/strong\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Improve program-management processes, documentation, repositories, reporting, and performance metrics so execution becomes more predictable, measurable, and searchable.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Identify repetitive or error-prone work that can be standardized or automated, and partner with data, software, and applied-AI teams to improve dashboards, milestone tracking, document workflows, and program knowledge.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Coach team members on readiness, documentation, supplier communication, decision-making, and escalation practices.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h2\u0026gt;Basic Qualifications\u0026lt;/h2\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s degree in engineering, computer science, operations, or a related field; equivalent practical experience may be considered.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;8–12 years of experience in hardware NPI, technical program management, manufacturing engineering, product operations, or a related field.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience guiding hardware products or builds through development, validation, manufacturing, or launch.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Working knowledge of hardware development, PCB/PCBA manufacturing, bills of materials, engineering changes, supplier coordination, and manufacturing release.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Demonstrated ability to manage integrated schedules, milestones, risks, action items, budgets, and cross-functional dependencies.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong written and verbal communication skills, with the ability to influence teams without direct authority and operate effectively in a fast-paced environment with changing priorities.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Willingness and ability to travel internationally as needed.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h2\u0026gt;Preferred Qualifications\u0026lt;/h2\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience with high-speed networking, PCIe Gen 6 or Gen 7, UALink, optical or cable connectivity, retimers, ASICs, compute platforms, data centers, or AI infrastructure hardware.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Understanding of physical-layer considerations for high-speed interconnects, including signal integrity, board-level debug, prototype rework, BGA processing, X-ray review, or failure analysis.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with customer programs, product launches, strategic initiatives, cost and operational improvement programs, product lifecycle activities, quality, RMA, or EOL execution.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency with Microsoft Excel, PowerPoint, Project, SharePoint, Power BI, and Teams for planning, reporting, documentation, collaboration, and executive communication.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience building dashboards, data pipelines, workflow automation, or AI-assisted engineering tools, as well as managing prototype budgets, purchase requests, purchase orders, supplier quotes, or forecasts.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience mentoring engineers, interns, or cross-functional teams and strengthening execution practices across a growing organization.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184321005,"name":"New Product Introduction Engineering","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4713208005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4444093005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":"Board Validation","value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Validation Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4713208005,"updated_at":"2026-10-05T14:25:26-04:00","requisition_id":"2026-133","title":"Principal Hardware Validation Engineer","company_name":"Astera Labs","first_published":"2026-08-04T01:25:17-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p style=\u0026quot;color: rgb(34, 34, 34); font-family: Arial, Helvetica, sans-serif; font-style: normal; font-weight: 400; letter-spacing: normal; white-space: normal; word-spacing: 0px; text-align: left;\u0026quot;\u0026gt;\u0026lt;span style=\u0026quot;font-family: helvetica, arial, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);\u0026quot;\u0026gt;As a Principal Hardware Validation Engineer\u0026lt;strong\u0026gt;\u0026amp;nbsp;\u0026lt;/strong\u0026gt;you will join the Hardware Electrical Validation team at Astera Labs, linking between the Hardware Electrical Design teams and Post-Silicon Electrical Validation teams, among others.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;color: rgb(34, 34, 34); font-family: Arial, Helvetica, sans-serif; font-style: normal; font-weight: 400; letter-spacing: normal; white-space: normal; word-spacing: 0px; text-align: left;\u0026quot;\u0026gt;\u0026lt;span style=\u0026quot;font-family: helvetica, arial, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);\u0026quot;\u0026gt;Note: This role is not post-silicon electrical validation; it is electrical validation of PCBAs and related\u0026amp;nbsp;hardware products.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;color: rgb(34, 34, 34); font-family: Arial, Helvetica, sans-serif; font-style: normal; font-weight: 400; letter-spacing: normal; white-space: normal; word-spacing: 0px; text-align: left;\u0026quot;\u0026gt;\u0026lt;span style=\u0026quot;font-family: helvetica, arial, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul style=\u0026quot;color: rgb(34, 34, 34); font-family: Arial, Helvetica, sans-serif; font-style: normal; font-weight: 400; letter-spacing: normal; white-space: normal; word-spacing: 0px; text-align: left;\u0026quot;\u0026gt;\n\u0026lt;li style=\u0026quot;margin-left: 15px; font-family: helvetica, arial, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);\u0026quot;\u0026gt;\u0026lt;span style=\u0026quot;font-family: helvetica, arial, sans-serif; font-size: 12pt;\u0026quot;\u0026gt;Support the Hardware Electrical Design teams with de-risking circuits and modules from project kick-off to gerber out.\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li style=\u0026quot;margin-left: 15px; font-family: helvetica, arial, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);\u0026quot;\u0026gt;\u0026lt;span style=\u0026quot;font-family: helvetica, arial, sans-serif; font-size: 12pt;\u0026quot;\u0026gt;Develop comprehensive hardware electrical validation plans using correct test methods and processes.\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li style=\u0026quot;margin-left: 15px; font-family: helvetica, arial, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);\u0026quot;\u0026gt;\u0026lt;span style=\u0026quot;font-family: helvetica, arial, sans-serif; font-size: 12pt;\u0026quot;\u0026gt;Bring up the PCBAs upon arrival in the lab, and execute the electrical validation plans to validate all circuits on the board.\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li style=\u0026quot;margin-left: 15px; font-family: helvetica, arial, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);\u0026quot;\u0026gt;\u0026lt;span style=\u0026quot;font-family: helvetica, arial, sans-serif; font-size: 12pt;\u0026quot;\u0026gt;Debug complex multi-point failures in hardware - power regulators, DPMs, clock synthesizers, digital control paths, I2C, SPI, etc.\u0026amp;nbsp; \u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li style=\u0026quot;margin-left: 15px; font-family: helvetica, arial, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);\u0026quot;\u0026gt;\u0026lt;span style=\u0026quot;font-family: helvetica, arial, sans-serif; font-size: 12pt;\u0026quot;\u0026gt;Rework components on the PCBAs to unblock debugging activities.\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li style=\u0026quot;margin-left: 15px; font-family: helvetica, arial, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);\u0026quot;\u0026gt;\u0026lt;span style=\u0026quot;font-family: helvetica, arial, sans-serif; font-size: 12pt;\u0026quot;\u0026gt;Pre-empt and de-risk system validation architectures - collaborate with the System Validation teams.\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li style=\u0026quot;margin-left: 15px; font-family: helvetica, arial, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);\u0026quot;\u0026gt;\u0026lt;span style=\u0026quot;font-family: helvetica, arial, sans-serif; font-size: 12pt;\u0026quot;\u0026gt;Support hardware activities in auxiliary teams - Post-Silicon Electrical Validation, Product Apps, System Validation, FAEs, etc.\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li style=\u0026quot;margin-left: 15px; font-family: helvetica, arial, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);\u0026quot;\u0026gt;\u0026lt;span style=\u0026quot;font-family: helvetica, arial, sans-serif; font-size: 12pt;\u0026quot;\u0026gt;Support the new designs using knowledge of existing products to de-risk new features and requirements.\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li style=\u0026quot;margin-left: 15px; font-family: helvetica, arial, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);\u0026quot;\u0026gt;\u0026lt;span style=\u0026quot;font-family: helvetica, arial, sans-serif; font-size: 12pt;\u0026quot;\u0026gt;Self-informed of new industry test standards and equipment to introduce modern testing methodologies.\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li style=\u0026quot;margin-left: 15px; font-family: helvetica, arial, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);\u0026quot;\u0026gt;\u0026lt;span style=\u0026quot;font-family: helvetica, arial, sans-serif; font-size: 12pt;\u0026quot;\u0026gt;Specify test equipment, develop test fixtures, help improve hardware lab functions.\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p style=\u0026quot;color: rgb(34, 34, 34); font-family: Arial, Helvetica, sans-serif; font-style: normal; font-weight: 400; letter-spacing: normal; white-space: normal; word-spacing: 0px; text-align: left;\u0026quot;\u0026gt;\u0026lt;span style=\u0026quot;font-family: helvetica, arial, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Required Skills\u0026lt;/strong\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul style=\u0026quot;color: rgb(34, 34, 34); font-family: Arial, Helvetica, sans-serif; font-style: normal; font-weight: 400; letter-spacing: normal; white-space: normal; word-spacing: 0px; text-align: left;\u0026quot;\u0026gt;\n\u0026lt;li style=\u0026quot;margin-left: 15px; font-family: helvetica, arial, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);\u0026quot;\u0026gt;\u0026lt;span style=\u0026quot;font-family: helvetica, arial, sans-serif; font-size: 12pt;\u0026quot;\u0026gt;Demonstrated strong skills in electronic circuit analysis, comprehensive testing and debug\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li style=\u0026quot;margin-left: 15px; font-family: helvetica, arial, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);\u0026quot;\u0026gt;\u0026lt;span style=\u0026quot;font-family: helvetica, arial, sans-serif; font-size: 12pt;\u0026quot;\u0026gt;Bachelor degree in EE with 3+ years of experience in hardware test or design\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li style=\u0026quot;margin-left: 15px; font-family: helvetica, arial, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);\u0026quot;\u0026gt;\u0026lt;span style=\u0026quot;font-family: helvetica, arial, sans-serif; font-size: 12pt;\u0026quot;\u0026gt;Expert understanding of design and test for power regulators, PDNs, Bode, clock generators\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li style=\u0026quot;margin-left: 15px; font-family: helvetica, arial, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);\u0026quot;\u0026gt;\u0026lt;span style=\u0026quot;font-family: helvetica, arial, sans-serif; font-size: 12pt;\u0026quot;\u0026gt;Ability to produce test description from a schematic design, and execute and document results\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li style=\u0026quot;margin-left: 15px; font-family: helvetica, arial, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);\u0026quot;\u0026gt;\u0026lt;span style=\u0026quot;font-family: helvetica, arial, sans-serif; font-size: 12pt;\u0026quot;\u0026gt;Demonstrated knowledge of the full hardware product lifecycle from Project Kick-off to RTM\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li style=\u0026quot;margin-left: 15px; font-family: helvetica, arial, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);\u0026quot;\u0026gt;\u0026lt;span style=\u0026quot;font-family: helvetica, arial, sans-serif; font-size: 12pt;\u0026quot;\u0026gt;Lab equipment for hardware test - oscilloscopes, e-loads, VNA, TDR, environmental chambers, etc.\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li style=\u0026quot;margin-left: 15px; font-family: helvetica, arial, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);\u0026quot;\u0026gt;\u0026lt;span style=\u0026quot;font-family: helvetica, arial, sans-serif; font-size: 12pt;\u0026quot;\u0026gt;Automating lab equipment to optimize test processes, Python preferred\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p style=\u0026quot;color: rgb(34, 34, 34); font-family: Arial, Helvetica, sans-serif; font-style: normal; font-weight: 400; letter-spacing: normal; white-space: normal; word-spacing: 0px; text-align: left;\u0026quot;\u0026gt;\u0026lt;span style=\u0026quot;font-family: helvetica, arial, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Preferred Skills\u0026lt;/strong\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul style=\u0026quot;color: rgb(34, 34, 34); font-family: Arial, Helvetica, sans-serif; font-style: normal; font-weight: 400; letter-spacing: normal; white-space: normal; word-spacing: 0px; text-align: left;\u0026quot;\u0026gt;\n\u0026lt;li style=\u0026quot;margin-left: 15px; font-family: helvetica, arial, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);\u0026quot;\u0026gt;\u0026lt;span style=\u0026quot;font-family: helvetica, arial, sans-serif; font-size: 12pt;\u0026quot;\u0026gt;Measurements of high-speed interfaces - PCIe, DDR, 25/50G/100G SERDES, etc.\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li style=\u0026quot;margin-left: 15px; font-family: helvetica, arial, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);\u0026quot;\u0026gt;\u0026lt;span style=\u0026quot;font-family: helvetica, arial, sans-serif; font-size: 12pt;\u0026quot;\u0026gt;EMI/EMC compliance\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li style=\u0026quot;margin-left: 15px; font-family: helvetica, arial, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);\u0026quot;\u0026gt;\u0026lt;span style=\u0026quot;font-family: helvetica, arial, sans-serif; font-size: 12pt;\u0026quot;\u0026gt;Technical writing skills - ECOs, Bug Reports, Rework WIs, MCOs, etc.\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li style=\u0026quot;margin-left: 15px; font-family: helvetica, arial, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);\u0026quot;\u0026gt;\u0026lt;span style=\u0026quot;font-family: helvetica, arial, sans-serif; font-size: 12pt;\u0026quot;\u0026gt;PLM, Arena or equivalent\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li style=\u0026quot;margin-left: 15px; font-family: helvetica, arial, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);\u0026quot;\u0026gt;\u0026lt;span style=\u0026quot;font-family: helvetica, arial, sans-serif; font-size: 12pt;\u0026quot;\u0026gt;Understanding of the ASIC/silicon product development process\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p class=\u0026quot;p8i6j01 paragraph\u0026quot;\u0026gt;\u0026lt;span style=\u0026quot;font-family: helvetica, arial, sans-serif; font-size: 12pt;\u0026quot;\u0026gt;The base salary range is $185,000 USD - $240,000 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184210005,"name":"Advanced Hardware Engineering","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4690506005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4433033005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":"IP Strategy","value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"CTO Organization","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4690506005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2493","title":"Principal IP Signoff \u0026 Methodology Engineer ","company_name":"Astera Labs","first_published":"2026-04-29T14:48:55-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 3\u0026quot;\u0026gt;Role Overview\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335559738\u0026amp;quot;:281,\u0026amp;quot;335559739\u0026amp;quot;:281}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Astera Labs is looking for\u0026amp;nbsp;a\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Principal\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026amp;nbsp;IP Signoff\u0026amp;nbsp;\u0026amp;amp;\u0026amp;nbsp;Methodology\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Engineer\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;to own the readiness, quality, and signoff of internal and external IP blocks before they are released into SoC and system implementation flows. This role sits at the intersection of IP development, physical design, and\u0026amp;nbsp;tapeout\u0026amp;nbsp;execution, with responsibility for ensuring that IP deliverables from both external vendors and internal engineering teams are complete,\u0026amp;nbsp;validated, and\u0026amp;nbsp;integration-ready.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:240,\u0026amp;quot;335559739\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;You will drive signoff closure and revision management across key IP handoff views and verification checks, including RTL, SDC, LEF/DEF, netlists, timing, physical verification, and package-aware considerations such as die and bump views. You will also drive configuration management of digital IP and ensure adherence to Astera-defined specifications, configurations, and usage profiles. The right candidate combines strong digital and physical design fundamentals with disciplined execution, debug ownership, and the ability to partner closely across digital, analog, package, CAD, and integration teams.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:240,\u0026amp;quot;335559739\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 2\u0026quot;\u0026gt;Key Responsibilities:\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335559738\u0026amp;quot;:299,\u0026amp;quot;335559739\u0026amp;quot;:299}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 3\u0026quot;\u0026gt;IP Release Readiness\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335559738\u0026amp;quot;:281,\u0026amp;quot;335559739\u0026amp;quot;:281}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:0,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Own the completeness, consistency, and configuration management of all internal and external IP deliverables, including supported configurations and usage profiles.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:0,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Own signoff readiness for IP releases, ensuring all required handoff views and collateral are complete, version-controlled,\u0026amp;nbsp;validated, and integration-ready.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:0,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Review and\u0026amp;nbsp;validate\u0026amp;nbsp;key IP deliverables such as RTL, timing constraints (SDC), synthesized netlists, LEF/DEF, floorplan-related data, and supporting documentation.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:0,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Define and\u0026amp;nbsp;maintain\u0026amp;nbsp;IP signoff checklists, release criteria, quality gates, and acceptance requirements for reusable IP.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:0,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Drive alignment between IP providers and SoC or subsystem implementation teams on expected deliverables, quality metrics, and release timelines.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 3\u0026quot;\u0026gt;Digital Signoff\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335559738\u0026amp;quot;:281,\u0026amp;quot;335559739\u0026amp;quot;:281}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:0,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Run, review, and\u0026amp;nbsp;validate\u0026amp;nbsp;digital signoff checks for IP releases, including timing, logical consistency, and implementation quality.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:0,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Verify the completeness and correctness of RTL, timing constraints, synthesized netlists, and other digital collateral\u0026amp;nbsp;required\u0026amp;nbsp;for downstream integration.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:0,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Ensure consistency across RTL, netlist, timing, and physical views prior to IP release.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:0,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Analyze digital signoff issues,\u0026amp;nbsp;identify\u0026amp;nbsp;root causes, and drive closure in partnership with design, physical design, and CAD teams.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 3\u0026quot;\u0026gt;Signoff and Physical Verification\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335559738\u0026amp;quot;:281,\u0026amp;quot;335559739\u0026amp;quot;:281}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:0,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Run, review, and debug physical verification signoff for IP and related assembly views, including DRC, LVS, PERC, and other required physical signoff checks.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:0,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Analyze physical verification results,\u0026amp;nbsp;identify\u0026amp;nbsp;root causes, and drive closure of violations in partnership with design, layout, and CAD teams.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:0,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Verify consistency across abstract, netlist, physical, and package-related views to support clean downstream integration.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:0,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Assess signoff readiness not only at the block level but also in the context of top-level integration, die, and bump/package interactions where applicable.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 3\u0026quot;\u0026gt;Debug, Integration, and Risk Management\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335559738\u0026amp;quot;:281,\u0026amp;quot;335559739\u0026amp;quot;:281}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:0,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Triage digital, physical, analog, and mixed-signal signoff issues and drive structured debug to resolution.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:0,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Partner with IP design, physical design, CAD, packaging, and integration teams to resolve signoff issues and reduce schedule risk.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:0,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Track signoff metrics, closure status, release readiness, and risk items, and communicate progress clearly to project stakeholders.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:0,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Identify\u0026amp;nbsp;recurring failure modes in IP releases and improve\u0026amp;nbsp;methodology, automation, and review practices to increase first-pass success.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 3\u0026quot;\u0026gt;Methodology and Continuous Improvement\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335559738\u0026amp;quot;:281,\u0026amp;quot;335559739\u0026amp;quot;:281}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:0,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Improve digital and physical signoff flows, checklists, and automation used to qualify IP for release.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:0,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Standardize release content, naming conventions, validation procedures, and acceptance criteria across multiple IP types.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:0,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Help define best practices for IP handoff into chip, package, card, and system design environments.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:0,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Contribute to\u0026amp;nbsp;scalable signoff\u0026amp;nbsp;methodology\u0026amp;nbsp;for increasingly complex, high-performance connectivity and AI infrastructure products.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 3\u0026quot;\u0026gt;Basic Qualifications\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335559738\u0026amp;quot;:281,\u0026amp;quot;335559739\u0026amp;quot;:281}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:0,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Strong hands-on experience with signoff views and deliverables such as RTL, SDC, LEF/DEF, synthesized netlists, timing reports, and related physical design artifacts.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:0,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience defining signoff metrics, release dashboards, automation, and\u0026amp;nbsp;methodology\u0026amp;nbsp;improvements across multiple programs.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;The base salary range is\u0026amp;nbsp;\u0026lt;strong\u0026gt;$175,000.00 USD – $230,000.00 USD\u0026lt;/strong\u0026gt;. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184300005,"name":"IP Strategy","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4735008005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4455067005,"location":{"name":"Bengaluru, Karnataka, India"},"metadata":[{"id":12122734005,"name":"Country","value":"India","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Bengaluru","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Digital Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4735008005,"updated_at":"2026-09-30T02:27:58-04:00","requisition_id":null,"title":"Principal Logic Design Engineer","company_name":"Astera Labs","first_published":"2026-09-30T02:27:58-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Principal Logic Design Engineer\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt; - \u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;10+ years\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Job Summary\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;We are seeking a \u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Principal Logic Design Engineer\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; with deep expertise in micro-architecture and RTL design to lead the development of complex IPs/subsystems. The candidate will provide technical ownership across architecture, microarchitecture, RTL implementation, integration, and silicon bring-up.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Lead RTL/microarchitecture development for \u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;complex connectivity IP/subsystems\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Translate specifications and system requirements into robust hardware architecture.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Design high-performance and scalable logic for controllers/subsystems.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Work across connectivity IP / subsystem layers including \u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Transaction, Data Link, and Physical interface integration\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; as applicable to the role.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Develop and review RTL using \u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;SystemVerilog/Verilog\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Develop robust mechanisms for \u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;flow control, ordering, buffering, arbitration, error handling, and reliability\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;7\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Drive performance, latency, area, and power optimization.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;8\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Collaborate with verification teams to develop verification strategies and debug complex failures.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;9\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Work with SoC integration and physical design teams to ensure successful implementation.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;10\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Lead technical reviews and mentor senior engineers.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;11\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Support post-silicon debug and root-cause analysis.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Required Skills\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Extensive experience in \u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;complex connec\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;t\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;i\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;vity\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; IPs such as PCIE, UALink, Ethernet, \u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;CXL, \u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;UCIe\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Strong RTL design experience using \u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;SystemVerilog/Verilog\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Deep knowledge of PCIe architecture and protocol.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Strong understanding of high-speed data paths, FIFOs, arbitration, flow control, and error handling.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience with simulation, lint, CDC, synthesis, and timing considerations.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; 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By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Principal Logic Design Engineer – UALink IP/Subsystem\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;10–15 years\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Job Summary\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;We are looking for a \u0026lt;strong\u0026gt;Principal Logic Design Engineer\u0026lt;/strong\u0026gt; with strong expertise in high-performance interconnect and SoC/IP design to lead RTL and microarchitecture development for \u0026lt;strong\u0026gt;UALink-based IP/subsystems\u0026lt;/strong\u0026gt;.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Lead architecture and RTL development for UALink IP/subsystems.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Translate protocol and system requirements into scalable hardware architecture.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Design high-bandwidth, low-latency data paths and control logic.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop robust mechanisms for \u0026lt;strong\u0026gt;flow control, ordering, buffering, arbitration, error handling, and reliability\u0026lt;/strong\u0026gt;.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Define interfaces between UALink and other SoC/interconnect components.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop and review SystemVerilog RTL.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive design optimization for performance, power, area, and latency.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work closely with verification, physical design, SoC integration, and firmware teams.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Review design specifications and contribute to architectural decisions.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Debug complex simulation and integration issues.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Provide technical leadership and mentorship.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Skills\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong experience in \u0026lt;strong\u0026gt;RTL and microarchitecture development\u0026lt;/strong\u0026gt;.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with high-speed interconnects and/or coherent fabrics.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of computer architecture, networking/interconnect concepts, and data movement.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency in SystemVerilog/Verilog.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of CDC, reset architecture, performance, and hardware design methodology.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Direct \u0026lt;strong\u0026gt;UALink\u0026lt;/strong\u0026gt; experience.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with \u0026lt;strong\u0026gt;PCIe, CXL, CCIX, CHI, Ethernet\u0026lt;/strong\u0026gt;, or similar protocols.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience in AI/accelerator or high-performance compute systems.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184256005,"name":"Design Engineering CCE2","child_ids":[],"parent_id":null}],"offices":[{"id":4049113005,"name":"Bengaluru","location":"India","child_ids":[],"parent_id":4052109005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4742856005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4458822005,"location":{"name":"Shanghai Shi, China"},"metadata":[{"id":12122734005,"name":"Country","value":"China","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Suzhou","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Supply Chain Operations","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4742856005,"updated_at":"2026-10-10T05:58:36-04:00","requisition_id":null,"title":"Principal NPI Planner","company_name":"Astera Labs","first_published":"2026-10-10T05:58:36-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is seeking a principal board NPI planner to drive material and production readiness for new hardware products, from early engineering builds through manufacturing ramp. You will turn complex requirements into executable plans, ensuring PCBA components, assemblies, suppliers, and build schedules are aligned to program milestones.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This role is central to bringing purpose-built connectivity solutions to market quickly and reliably as Astera Labs scales its rack-scale AI infrastructure portfolio. You will work across engineering, operations, procurement, and quality to support order fulfillment, surface risks early, resolve constraints, and improve launch execution in a fast-moving semiconductor environment.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· \u0026lt;span style=\u0026quot;text-decoration: underline;\u0026quot;\u0026gt;Planning \u0026amp;amp; Execution\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;o Own PCBA planning activities through production ramp readiness.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;o Build and maintain detailed build plans covering BOM readiness, material availability, purchase orders, supplier commitments, and production milestones.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;o Track planning-system transactions, inventory, shortages, and material status to keep the builds on schedule.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;o Support order fulfillment against internal and external demand.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;o Support local manufacturing activities and resolve execution issues as they arise.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· \u0026lt;span style=\u0026quot;text-decoration: underline;\u0026quot;\u0026gt;Cross-Functional \u0026amp;amp; Manufacturing Coordination\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;o Partner with hardware engineering, operations, procurement, and the internal contract manufacturing team to align demand, supply, and execution plans.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;o Coordinate PCBA readiness across component suppliers, PCB and assembly partners, and test or manufacturing teams.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;o Support build execution by monitoring work-in-progress, finished goods, configuration changes, and handoffs into sustaining or high-volume manufacturing.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· \u0026lt;span style=\u0026quot;text-decoration: underline;\u0026quot;\u0026gt;Risk Management \u0026amp;amp; Launch Communication\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;o Identify material shortages, supplier constraints, capacity gaps, and schedule risks, then drive mitigation plans to protect launch milestones.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;o Prepare clear status reports, readiness assessments, and escalation materials for program and operations reviews.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;o Analyze supply, delivery, and cost tradeoffs and recommend actions that improve schedule predictability and inventory efficiency.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;text-decoration: underline;\u0026quot;\u0026gt;Basic Qualifications\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Bachelor’s degree in Supply Chain, Engineering, Operations, Business, or a related field.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· 8+ years of experience in NPI planning, supply chain planning, production planning, or manufacturing operations.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Experience in PCBA hardware manufacturing, specifically within electronics assembly and contract manufacturing environments.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Strong working knowledge of material requirements planning, supply-demand planning, inventory management, and supplier coordination.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Experience building and managing detailed schedules across multiple cross-functional stakeholders.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Advanced Microsoft Excel skills and hands-on experience with ERP or MRP systems, with strong analytical and communication skills.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;text-decoration: underline;\u0026quot;\u0026gt;Preferred Qualifications\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Experience supporting new product introductions for data center or AI infrastructure products.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Familiarity with PCBAs, bills of material, approved vendor lists, engineering changes, component lifecycle management, and manufacturing readiness gates.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Experience working with global suppliers, contract manufacturers, and manufacturing partners in Asia.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Experience creating planning dashboards, shortage reports, and data-driven operating metrics using Microsoft tools.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Ability to influence cross-functional teams, manage competing priorities, and drive timely resolution in a high-growth environment.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184298005,"name":"Hardware Supply Chain","child_ids":[],"parent_id":null}],"offices":[{"id":4009038005,"name":"Suzhou-Wuxi","location":"China","child_ids":[],"parent_id":4002875005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4720464005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4447672005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Supply Chain Operations","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4720464005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2026-377","title":"Principal NPI Planner ","company_name":"Astera Labs","first_published":"2026-07-31T17:00:01-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;h1 class=\u0026quot;wnfdnti _1ibi0s33y _1ibi0s34u\u0026quot; data-pm-slice=\u0026quot;1 1 []\u0026quot;\u0026gt;Principal NPI Planner (2026-377)\u0026lt;/h1\u0026gt;\n\u0026lt;h2 class=\u0026quot;wnfdnti _1ibi0s33y _1ibi0s34u\u0026quot;\u0026gt;Role Overview\u0026lt;/h2\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Astera Labs is seeking a Principal NPI Planner to lead supply chain planning and execution for ASIC new product introductions, from early engineering builds through ramp readiness. This role owns cross-functional schedule alignment, material readiness, supply-demand coordination, and launch execution, ensuring new products move from development into manufacturing on time and with minimal supply risk.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;As a hyper-growth company building the connectivity that powers rack-scale AI infrastructure, our ability to bring new silicon to market fast is a competitive advantage. You will partner closely with engineering, operations, business teams, and external manufacturing partners to build executable plans, surface risks early, and drive resolution across the product lifecycle. This is a highly visible role for someone who thrives in a fast-moving semiconductor environment and turns complexity into clear execution.\u0026lt;/p\u0026gt;\n\u0026lt;h2 class=\u0026quot;wnfdnti _1ibi0s33y _1ibi0s34u\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/h2\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdntf\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;NPI Planning \u0026amp;amp; Execution\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdntf\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Own NPI planning activities for ASIC products from engineering builds through RTM and production ramp readiness.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Build and maintain detailed product schedules, including key milestones, material readiness dates, build plans, and customer delivery requirements.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Support ERP and planning-system execution for NPI materials, inventory tracking, purchase orders, and related planning transactions.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional \u0026amp;amp; Supplier Coordination\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdntf\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Partner with engineering, operations, procurement, finance, and external manufacturing partners to align demand, supply, and execution plans.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Track and drive material readiness for wafers, substrates, test hardware, and other critical components required to support builds.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Coordinate with OSATs, suppliers, and contract manufacturers to support build execution, monitor WIP and finished goods status, and resolve schedule or supply constraints.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Risk Management \u0026amp;amp; Business Communication\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdntf\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Identify launch risks, capacity gaps, and execution roadblocks early, then drive cross-functional mitigation plans to protect program timelines.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Analyze supplier quotes and support cost and delivery tradeoff discussions to ensure supply commitments align with program needs.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Prepare clear status updates, risk assessments, and escalation materials for business and operations reviews.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Partner with sustaining or HVM planners to ensure an effective handoff once products transition beyond the NPI phase.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h2 class=\u0026quot;wnfdnti _1ibi0s33y _1ibi0s34u\u0026quot;\u0026gt;Basic Qualifications\u0026lt;/h2\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdntf\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Supply Chain, Engineering, Operations, Business, or a related field.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;8 + years of experience in NPI planning, supply chain planning, production planning, or manufacturing operations.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Experience supporting semiconductor, fabless, OSAT, EMS, or other high-tech manufacturing environments.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Strong working knowledge of supply-demand planning, material planning, inventory management, and supplier or factory coordination.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Experience building and managing detailed schedules across multiple cross-functional stakeholders.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Advanced Excel skills and hands-on experience working in ERP or MRP systems, with strong analytical and communication skills to influence internal teams and external partners.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h2 class=\u0026quot;wnfdnti _1ibi0s33y _1ibi0s34u\u0026quot;\u0026gt;Preferred Qualifications\u0026lt;/h2\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdntf\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Experience supporting ASIC or other semiconductor new product introductions.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Familiarity with wafer, assembly, test, substrate, or hardware readiness planning.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Experience working with global suppliers or manufacturing partners in Asia.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Experience with reporting, dashboards, or data analysis to improve planning visibility and execution.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Salary range is $160,000 to $200,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184341005,"name":"Silicon Supply Chain","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4720847005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4447882005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Packaging Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4720847005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2026-108","title":"Principal Optical Assembly Engineer","company_name":"Astera Labs","first_published":"2026-08-03T17:31:47-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 2\u0026quot;\u0026gt;About the Role\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335559738\u0026amp;quot;:200,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Astera Labs is seeking a \u0026lt;strong\u0026gt;Principal Optical Assembly Engineer\u0026lt;/strong\u0026gt; to drive development of optical assembly processes that support\u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt; next-generation photonics products for scale up and scale out AI infrastructure applications\u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;. This is a high-impact individual contributor role with technical leadership responsibilities, focused on developing robust assembly processes, expanding lab capability, and improving the yield, quality, and reliability of optical assemblies for NPO and CPO products.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 2\u0026quot;\u0026gt;Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335559738\u0026amp;quot;:200,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Drive development and optimization of optical assembly processes, including active and passive fiber alignment, fiber \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;attach\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;, and epoxy cure.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Define and document process flows, work instructions, and quality control plans for optical assembly.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Support the build-out and scaling of the optical assembly laboratory, including equipment layout, tool qualification, and safety protocols.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Partner with equipment suppliers on the development and qualification of\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt; high volume capable\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt; active alignment systems, dispensing tools, and curing tools.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Qualify optical adhesives and encapsulants with material vendors for optical performance, thermal and mechanical requirements, process scalability, and reliability.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Develop yield improvement plans and implement statistical process control (SPC) methods for optical assembly.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 2\u0026quot;\u0026gt;Basic Qualifications\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335559738\u0026amp;quot;:200,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;7\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;B.S., M.S., or Ph.D. in Electrical Engineering, Mechanical Engineering, Materials Science, Optical Engineering, or a related field.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;8\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;8\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;+ years of experience in optical assembly, \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;photonics\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt; packaging, or \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;a related\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt; process development role.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;9\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Hands-on experience developing precision assembly processes for photonic or optoelectronic products.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;10\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Experience leading \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;optical assembly platforms from concept to high volume production\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;11\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Experience\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt; with alignment-intensive assembly methods and process controls used in fiber-coupled or optical device manufacturing.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;12\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Strong understanding of process development, qualification, troubleshooting, and transfer to manufacturing.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;13\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Ability to create clear process documentation and translate development work into repeatable production practices.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;14\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Experience collaborating with external equipment and materials partners to mature assembly solutions.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;15\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Strong foundation\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt; in yield analysis, reliability characterization, and process capability methodologies such as \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Cpk\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt; and SPC.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 2\u0026quot;\u0026gt;Preferred Qualifications\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335559738\u0026amp;quot;:200,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;16\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Hands-on experience with active alignment systems for photonic or optical device assembly.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;17\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Hands-on experience with optical adhesives, encapsulants, and related material \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;qualification\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;18\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Familiarity with optical performance verification, failure analysis, and process optimization.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;19\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Experience \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;building high volume assembly tools\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;, equipment qualification, and safe operating practices for optical assembly environments.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p class=\u0026quot;p8i6j01 paragraph\u0026quot;\u0026gt;Salary range is $185,000 to $240,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184399005,"name":"Signal Connectivity Group","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4731932005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4453553005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Engineering Operations","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4731932005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2720","title":"Principal Package Signal \u0026 Power Integrity ","company_name":"Astera Labs","first_published":"2026-09-09T13:54:32-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Job Description: \u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As a \u0026lt;strong\u0026gt;Principal Package Signal \u0026amp;amp; Power Integrity Engineer\u0026lt;/strong\u0026gt; at Astera Labs, you will serve as a senior technical leader responsible for architecting, optimizing, and signing off package SIPI solutions for next-generation connectivity products. You will drive package electrical architecture across high-performance IC packaging platforms, including FCBGA, coreless substrates, chiplet-based packages, 2.5D/3D integration, silicon interposers, bridge-based interconnect, and heterogeneous multi-die systems.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;In this role, you will lead SIPI strategy and execution for products supporting PCIe, CXL, Ethernet, 200G/400G+ SerDes, and die-to-die interconnect. You will partner closely with silicon architecture, SerDes/IP teams, package design, PCB design, hardware validation, manufacturing, substrate vendors, and OSAT partners to optimize signal integrity, power delivery, substrate/interposer routing, bump planning, and system-level electrical performance while balancing cost, manufacturability, reliability, yield, and schedule.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;You will also drive SIPI methodology, modeling standards, simulation-to-measurement correlation, and chip–package–board co-design frameworks to enable scalable execution across multiple product lines.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Define package SIPI architecture and design strategy for high-performance connectivity products, including PCIe 5.0/6.0/7.0, CXL, Ethernet, 200G/400G+ SerDes, and die-to-die interconnect.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Perform package and system-level SI and PI simulations using industry-standard simulation software such as HFSS, SIwave, and Keysight ADS to develop, optimize, and sign off package electrical models, validate package architecture and designs, and ensure robust signal and power integrity across chip–package–board systems.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead cross-functional execution across silicon team, package design, marketing and APPs, PCB board team, validation team, package manufacturing, and external substrate/OSAT partners, managing technical tradeoffs among SIPI performance, cost, DFM, yield, etc., and deliver packaging solutions on schedule.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive simulation-to-measurement correlation strategy, ensuring strong alignment between EM extraction, system-level models, and lab validation (VNA, TDR, high-speed oscilloscope), continuously improving model accuracy, simulation efficiency, and SIPI signoff criteria.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Own SIPI simulation and signoff for advanced packaging platforms, including chiplet-based packages, 2.5D/3D integration, silicon interposers, and bridge-based interconnect, by leading simulations for D2D interconnect (e.g., UCIe), multi-die PDN, micro-bump modeling, TSV/interposer modeling, and multi-die CPM co-simulation.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Define substrate, interposer, and bridge routing guidelines for high-speed SerDes and D2D interfaces, including impedance targets, differential-pair geometry, via/transition optimization, return-current management, shielding, skew control, and crosstalk isolation.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Establish SIPI modeling standards, design rules, review checklists, automation flows, and signoff methodologies to improve execution efficiency, while mentoring engineers across the organization.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required qualifications:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;10+ years of experience in signal integrity, power integrity, package electrical design, or chip–package–board co-design for high-performance semiconductor products.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep expertise in package SIPI modeling, analysis, optimization, and signoff across the chip–package–board system, for high-speed SerDes, PCIe, CXL, Ethernet, etc.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong experience with PCIe 5.0/6.0, PAM4 SerDes channel design, high-speed S-parameter extraction, package model development, eye-diagram analysis, return/insertion-loss optimization, and crosstalk analysis.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven track record delivering high-performance packages using FCBGA, FCCSP, coreless substrates, advanced organic substrates, chiplet-based packages, 2.5D integration, silicon interposers, or heterogeneous integration platforms.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on expertise with EM extraction and SIPI simulation tools such as ANSYS HFSS, SIwave, Q3D, 3D Layout, Keysight ADS, Cadence Sigrity, or equivalent tools.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Expert-level knowledge of PDN design, including DC IR drop, AC impedance, target impedance, loop inductance, decoupling optimization, transient response, noise coupling, and chip-package-model methodology.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Demonstrated ability to correlate simulation to lab measurement (VNA, TDR, high-speed oscilloscope).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of tradeoffs between SIPI performance, cost, reliability, and manufacturability.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience leading vendor engagements and managing technical execution through production ramps.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;:\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience influencing silicon floor planning, bump map definition, SerDes and power-grid planning, package escape strategy, and PCB breakout from a SIPI perspective.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with automation and scripting for SIPI modeling flow.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Exposure to Allegro Package Designer (APD) for hands-on substrate editing.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge on traditional FCBGA type package and advanced package (chiplet/2.5D/3D) manufacturing and assembly process flows\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with CPO and NPO optical package SIPI design, including high-speed channel modeling between EIC/PIC/optical engine, PDN design, crosstalk/noise analysis, and chip–package–board co-design for optical connectivity applications.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;The base salary range is $203,000 USD – $240,000 USD. Your base salary will be determined based on location, experience, and employees\u0026#39; pay in similar positions.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4720529005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4447707005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Packaging Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4720529005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2026-107","title":"Principal Photonics Package Architect","company_name":"Astera Labs","first_published":"2026-07-31T16:56:36-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Location: San Jose, CA (On-site).\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 2\u0026quot;\u0026gt;About the Role\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335559738\u0026amp;quot;:200,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Astera Labs is seeking a Principal Photonics Package Architect to define and drive package architecture for next-generation photonics products for scale up and scale out AI infrastructure applications. This is a high-impact senior individual contributor role focused on aligning electrical, thermal, and mechanical design requirements across functions, enabling robust package implementation, and guiding package technology decisions for NPO and CPO products.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 2\u0026quot;\u0026gt;Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335559738\u0026amp;quot;:200,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Define\u0026lt;/span\u0026gt; \u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;photonics\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt; package architecture, \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;define\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt; electrical\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt; and optical\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt; interface specifications, and \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;establish\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt; signal integrity\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt; and power integrity\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt; requirements.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Establish and manage Thermal Design Power (TDP) budgets and thermal performance targets.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Drive cross-functional alignment with EIC, PIC, and hardware teams on co-design constraints\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt; and drive system optical link budget\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Partner with validation, test, and reliability teams to define DFT and DFR requirements and acceptance criteria.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Finalize bump map and ball \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;map, and\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt; manage ECOs and revision control of package design databases.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Lead package-level design reviews and own the package design technical roadmap.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 2\u0026quot;\u0026gt;Basic Qualifications\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335559738\u0026amp;quot;:200,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;7\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;B.S., M.S., or Ph.D. in Electrical Engineering, Mechanical Engineering, Materials Science, Physics, or a related field.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;8\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;10+ years of experience in semiconductor \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;or \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;photonics\u0026lt;/span\u0026gt; \u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;package development, package design, or package integration, with \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;demonstrated\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt; technical leadership.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;9\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Strong understanding of package architecture tradeoffs across electrical, \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;optical, \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;thermal, mechanical, and manufacturability considerations.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;10\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Experience working across chip, board, and system-level design \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;electrical and optical \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;interfaces in complex product development environments.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;11\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Experience with package EDA tools and electrical simulation tools, including Cadence APD+ and Ansys HFSS.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;12\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Experience with advanced packaging design, including 2.5D and 3D package architectures.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;13\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Familiarity with package design flows, design database management, and engineering change control practices.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;14\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Ability to drive technical decisions, resolve cross-functional issues, and communicate architecture direction clearly to stakeholders.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;15\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Strong foundation\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt; in design reviews, risk assessment, and design quality from concept through production release.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 2\u0026quot;\u0026gt;Preferred Qualifications\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335559738\u0026amp;quot;:200,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;16\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Experience with industry-standard \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;optical\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt; interfaces and interconnect technologies relevant to package design.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;17\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Experience with advanced\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt; photonics\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt; packaging technologies for \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;data center interconnects\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;18\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Experience supporting package bring-up and correlating design assumptions with validation results.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;19\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Experience supporting cross-functional design closure with silicon, photonics, board, validation, test, and reliability teams.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:360,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;singleLevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;20\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;List Bullet\u0026quot;\u0026gt;Knowledge of package design for NPO or CPO products.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Salary range is $185,000 to $240,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184399005,"name":"Signal Connectivity Group","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4742858005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4458824005,"location":{"name":"Haifa District, Israel"},"metadata":[{"id":12122734005,"name":"Country","value":"Israel","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Tel Aviv","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Physical Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4742858005,"updated_at":"2026-10-11T08:11:38-04:00","requisition_id":null,"title":"Principal Physical Design CAD Engineer","company_name":"Astera Labs","first_published":"2026-10-11T08:11:38-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;EOP SCXW38165641 BCX0\u0026quot; data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:160}\u0026quot;\u0026gt;Astera Labs is establishing a strategic R\u0026amp;amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical \u0026#39;data bottlenecks\u0026#39; enabling the future of AI at scale. As we expand our presence in Israel, We are looking for a\u0026amp;nbsp;\u0026lt;strong\u0026gt;Physical Design CAD Engineer\u0026lt;/strong\u0026gt;\u0026amp;nbsp;with at least\u0026amp;nbsp;\u0026lt;strong\u0026gt;3 years of hands-on experience\u0026lt;/strong\u0026gt;\u0026amp;nbsp;in digital implementation flows. The ideal candidate is highly technical, curious, and eager to drive innovation by combining strong physical design knowledge with modern automation and\u0026amp;nbsp;\u0026lt;strong\u0026gt;GenAI-based methodologies.\u0026lt;/strong\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p data-path-to-node=\u0026quot;4\u0026quot;\u0026gt;This is a unique opportunity to take on meaningful technical ownership in a new site, implementing the parasitic extraction (PEX) methodologies and flows for chips that power the world\u0026#39;s largest AI clusters. As a foundational member of the team, you will be responsible for the accuracy and efficiency of our extraction environment, ensuring that our high-speed designs are modeled with the highest precision from RTL to GDSII.\u0026lt;/p\u0026gt;\n\u0026lt;p data-path-to-node=\u0026quot;4\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;p data-olk-copy-source=\u0026quot;MessageBody\u0026quot;\u0026gt;The Engineer will develop, maintain, and improve CAD flows and methodologies for physical design teams, supporting advanced implementation stages from synthesis through place and route, timing closure, power optimization, and signoff readiness.\u0026lt;/p\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;p\u0026gt;Key responsibilities include:\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Develop and support physical design CAD flows using industry-standard EDA tools\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Build automation infrastructure for implementation, analysis, reporting, and debug\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support design teams in areas such as synthesis, floorplanning, placement, CTS, routing, timing, power, and physical verification\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Create scripts and utilities to improve productivity, quality of results, and flow robustness\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support and enhance flows based on\u0026amp;nbsp;\u0026lt;strong\u0026gt;Synopsys Fusion Compiler\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Explore and integrate\u0026amp;nbsp;\u0026lt;strong\u0026gt;GenAI solutions\u0026lt;/strong\u0026gt; to accelerate debug, automate repetitive tasks, improve reporting, and enhance engineering productivity\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Analyze tool results, logs, QoR metrics, timing reports, congestion, utilization, power, and design-rule issues\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;br\u0026gt;\u0026lt;/span\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-olk-copy-source=\u0026quot;MessageBody\u0026quot;\u0026gt;At least\u0026amp;nbsp;\u0026lt;strong\u0026gt;3 years of experience\u0026lt;/strong\u0026gt; in Physical Design, CAD, or implementation methodology\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of digital physical design concepts, including synthesis, placement, CTS, routing, timing closure, and physical verification\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience with\u0026amp;nbsp;\u0026lt;strong\u0026gt;Synopsys Fusion Compiler\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with scripting languages such as\u0026amp;nbsp;\u0026lt;strong\u0026gt;Tcl, Python\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ability to develop automation around EDA tools and large-scale design flows\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Good understanding of timing, power, congestion, floorplanning, and QoR analysis\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong debugging and problem-solving skills\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ability to work closely with multiple engineering teams and support complex design environments\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;High motivation to learn and apply\u0026amp;nbsp;\u0026lt;strong\u0026gt;GenAI technologies\u0026lt;/strong\u0026gt;\u0026amp;nbsp;in semiconductor design flows.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Preferred Experience\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-olk-copy-source=\u0026quot;MessageBody\u0026quot;\u0026gt;Experience with additional tools such as PrimeTime, StarRC, ICC2, Innovus, Voltus, RedHawk, Calibre, or similar\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of STA, low-power design, UPF, EM/IR, extraction, or signoff flows\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience building dashboards, regression systems, flow checkers, or automated report analyzers\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with LLMs, prompt engineering, AI agents, or GenAI-based coding/debug tools\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with Git, CI/CD, databases, or cloud-based compute environments\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184376005,"name":"Physical Design CCE2","child_ids":[],"parent_id":null}],"offices":[{"id":4052111005,"name":"Haifa","location":"Israel","child_ids":[],"parent_id":4008937005},{"id":4056876005,"name":"Tel Aviv","location":"Israel","child_ids":[],"parent_id":4008937005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4679751005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4428081005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":"Compute Connectivity Engineering 1","value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Physical Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4679751005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2435","title":"Principal Physical Design Engineer","company_name":"Astera Labs","first_published":"2026-03-31T14:28:20-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is redefining the connectivity fabric that powers rack-scale AI infrastructure. As a Principal Physical Design Engineer, you will own the backend implementation of complex, high-performance SoCs that sit at the heart of the world\u0026#39;s largest AI clusters — driving floorplan, timing, power, and signoff decisions that directly determine product PPA and time-to-market.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This is a hands-on technical leadership role. You will architect physical design methodology, mentor senior engineers, and partner closely with RTL, DFT, analog, and package teams to take our next generation of connectivity silicon from RTL to tapeout on leading-edge nodes.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;End-to-End RTL2GDS Ownership\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Own the full RTL2GDS flow on advanced process nodes — synthesis, floorplan, placement, CTS, routing, and signoff — across Astera\u0026#39;s connectivity product portfolio\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive block- and chip-level place \u0026amp;amp; route strategy, congestion resolution, and routing convergence on high-frequency, high-density designs\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Architect clock tree synthesis and clocking topology to meet skew, latency, and power targets\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead tapeout execution: final ECO closure, GDS handoff, and post-tapeout support through fab\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Timing, Power \u0026amp;amp; Signoff\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive multi-mode multi-corner STA closure, low-power implementation (UPF/CPF), and IR/EM analysis to signoff\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Own physical verification (LVS, DRC, antenna, ERC) and reliability signoff through clean closure\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Define methodology for ECO flows, hierarchical timing, and full-chip signoff sign-around\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Technical Leadership \u0026amp;amp; Cross-Functional Partnership\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Partner with RTL, DFT, analog/mixed-signal, package, and CAD teams to converge on floorplan, clocking, and power delivery strategies\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Establish and evolve physical design methodology, scripts, and flows across the team\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Mentor engineers, drive design reviews, and represent Physical Design in program-level technical decisions\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, Computer Engineering, or related field\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;8+ years of physical design experience with multiple tapeouts on advanced process nodes (7nm or below)\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep expertise in synthesis, place \u0026amp;amp; route, CTS, and timing closure using industry-standard tools (Synopsys Fusion Compiler / ICC2, Cadence Innovus, PrimeTime)\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong command of low-power design techniques (multi-Vt, power gating, DVFS, UPF)\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency in Tcl/Python scripting for flow automation\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven track record delivering high-frequency, high-complexity SoC blocks or full-chip implementations to production\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;MS in Electrical Engineering or Computer Engineering\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with high-speed SerDes-heavy designs, PCIe Gen 6/7, or UALink/UCIe-based connectivity SoCs\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience with hierarchical implementation and full-chip integration of large designs (\u0026amp;gt;500M gates)\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with EMIR, thermal, and package co-design considerations\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience mentoring senior engineers and driving methodology adoption across teams\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Salary range is $185,000 to $240,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184232005,"name":"Compute Connectivity Engineering 1","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4693897005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4434829005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Physical Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4693897005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2527","title":"Principal Physical Design Engineer -EMIR \u0026 Power Integrity","company_name":"Astera Labs","first_published":"2026-07-22T15:13:35-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 2\u0026quot;\u0026gt;Role Overview\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:299,\u0026amp;quot;335559739\u0026amp;quot;:299}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Astera Labs is scaling the connectivity fabric behind the world\u0026#39;s largest AI clusters, and reliable power delivery is non-negotiable in the SoCs we ship. As a \u0026lt;strong\u0026gt;Principal Physical Design Engineer\u0026lt;/strong\u0026gt;, you will own IR drop and electromigration (EMIR) analysis and closure across Astera Labs\u0026#39; connectivity ASIC portfolio, driving power integrity from early floorplan through tapeout.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:240,\u0026amp;quot;335559739\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;You will partner closely with power grid, floorplan, package, and implementation teams to ensure stable power delivery, meet foundry sign-off criteria, and prevent long-term reliability issues in production silicon. This role is fully on-site at our San Jose, CA location.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:240,\u0026amp;quot;335559739\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 2\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:299,\u0026amp;quot;335559739\u0026amp;quot;:299}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Power Integrity Analysis \u0026amp;amp; Sign-off\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:240,\u0026amp;quot;335559739\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Own static and dynamic IR drop and electromigration analysis at block and full-chip levels, driving closure to foundry sign-off criteria\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:240,\u0026amp;quot;335559739\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Drive UPF-based power domain planning and power-aware sign-off across multi-voltage designs\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:240,\u0026amp;quot;335559739\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Analyze thermal and current density issues and recommend design modifications to ensure long-term reliability\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:240,\u0026amp;quot;335559739\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Design Convergence \u0026amp;amp; Cross-Functional Partnership\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:240,\u0026amp;quot;335559739\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Collaborate with package, power grid, and floorplan teams to identify and resolve voltage drop hotspots and EM violations early in the design cycle\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:240,\u0026amp;quot;335559739\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Provide actionable feedback to implementation teams on power grid reinforcement, decap strategy, and hard-macro / SerDes integration\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:240,\u0026amp;quot;335559739\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Partner with RTL, STA, verification, IP vendors, and foundry to drive power integrity convergence through tapeout\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:240,\u0026amp;quot;335559739\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Methodology \u0026amp;amp; Automation\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:240,\u0026amp;quot;335559739\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Develop and refine EMIR runsets, stimulus methodologies, and reporting dashboards to improve predictability and reduce iterations\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:240,\u0026amp;quot;335559739\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Build and maintain EMIR analysis flows and automation infrastructure for efficient multi-corner analysis\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:240,\u0026amp;quot;335559739\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Deliver clear, actionable root-cause analysis and mitigation guidance at both block and full-chip levels\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:240,\u0026amp;quot;335559739\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 2\u0026quot;\u0026gt;Basic Qualifications:\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:299,\u0026amp;quot;335559739\u0026amp;quot;:299}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, Computer Engineering, or a related field\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:240,\u0026amp;quot;335559739\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;8+ years of experience in IR drop, electromigration analysis, and power integrity sign-off for complex SoCs at advanced nodes (7nm and below)\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:240,\u0026amp;quot;335559739\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Deep expertise in power grid design, PDN analysis, and EM reliability mitigation, including static and dynamic IR methodologies and foundry sign-off criteria\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:240,\u0026amp;quot;335559739\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Proficiency with Cadence Voltus and/or Synopsys RedHawk-SC / PrimeTime PX\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:240,\u0026amp;quot;335559739\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Strong scripting ability in Tcl, Python, and/or Perl for flow automation and data analysis\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:240,\u0026amp;quot;335559739\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 2\u0026quot;\u0026gt;Preferred Qualifications:\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:299,\u0026amp;quot;335559739\u0026amp;quot;:299}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Master\u0026#39;s degree in Electrical Engineering or a related field\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:240,\u0026amp;quot;335559739\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Power integrity experience on high-speed SerDes, Ethernet PHY, or PCIe designs\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:240,\u0026amp;quot;335559739\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Package-level power delivery analysis / co-simulation, including advanced packaging or multi-die integration exposure\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:240,\u0026amp;quot;335559739\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience building EMIR methodology infrastructure that scales across multiple concurrent tapeout programs\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:240,\u0026amp;quot;335559739\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Base salary range is $185,000 to $240,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:240,\u0026amp;quot;335559739\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4692163005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4433721005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Physical Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4692163005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2503","title":"Principal Physical Design Engineer, Methodology","company_name":"Astera Labs","first_published":"2026-07-22T14:58:19-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Role Overview\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:200,\u0026amp;quot;335559740\u0026amp;quot;:276}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;As a\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Principal Physical Design Engineer\u0026amp;nbsp;-\u0026amp;nbsp;Methodology\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;, you will define, develop, and\u0026amp;nbsp;maintain\u0026amp;nbsp;the reusable physical design flows and automation infrastructure that the entire PD team relies on. You will build the RTL-to-GDSII flow, integrate and qualify tools from multiple vendors (Cadence and Synopsys), and continuously improve PPA and schedule predictability across all programs. You are the force multiplier\u0026amp;nbsp;scaling the team\u0026#39;s capabilities and enabling faster, better\u0026amp;nbsp;tapeouts. This role is fully on-site at our San Jose, CA location.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:200,\u0026amp;quot;335559740\u0026amp;quot;:276}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Key Responsibilities:\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Flow \u0026amp;amp; Methodology Ownership\u0026lt;/strong\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Define, develop, and maintain reusable physical design flows spanning synthesis, place-and-route, extraction, STA, and EMIR\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Own the end-to-end RTL-to-GDSII flow infrastructure across multi-vendor toolchains (Cadence Innovus, Tempus, Voltus, Pegasus; Synopsys Fusion Compiler, ICC2, PrimeTime, StarRC)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Evaluate and qualify new tool features, foundry enablement kits, and flow enhancements to continuously improve PPA and schedule predictability\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Integrate and maintain DRC/LVS/extraction runsets and ensure consistency with foundry requirements\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Automation \u0026amp;amp; Scale\u0026lt;/strong\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Build and enhance automation scripts and infrastructure to manage large-scale multi-corner/multi-mode STA and EMIR runs with efficient partitioning and resource usage\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop QoR optimization frameworks and tracking methodologies to measure and improve design quality across programs\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Partner with IT and compute infrastructure teams to optimize job scheduling, storage, and compute resource utilization\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Standards, Quality \u0026amp;amp; Enablement\u0026lt;/strong\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Establish best practices, runset standards, and quality checks that scale across multiple concurrent tapeout programs\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support physical design engineers with flow issues, tool configurations, and methodology guidance\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive adoption of flow improvements across the team, including training and documentation\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Basic Qualifications:\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, Computer Engineering, or a related field; Masters Preferred.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;8+ years of experience in physical design\u0026amp;nbsp;methodology, CAD, or flow development for complex SoCs at advanced nodes (7nm and below)\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:200,\u0026amp;quot;335559740\u0026amp;quot;:276}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Strong knowledge of synthesis, place-and-route, extraction, STA, and equivalence checking flows\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:200,\u0026amp;quot;335559740\u0026amp;quot;:276}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience with both Cadence (Innovus, Tempus,\u0026amp;nbsp;Voltus, Pegasus) and Synopsys (Fusion Compiler,\u0026amp;nbsp;PrimeTime,\u0026amp;nbsp;StarRC, ICC2)\u0026amp;nbsp;toolchains\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:200,\u0026amp;quot;335559740\u0026amp;quot;:276}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Expert-level scripting ability in Python,\u0026amp;nbsp;Tcl, and/or Perl for flow development and automation\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:200,\u0026amp;quot;335559740\u0026amp;quot;:276}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience building and\u0026amp;nbsp;maintaining\u0026amp;nbsp;multi-corner/multi-mode analysis infrastructure\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:200,\u0026amp;quot;335559740\u0026amp;quot;:276}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Understanding of foundry design rules, technology files, and enablement kit integration\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:200,\u0026amp;quot;335559740\u0026amp;quot;:276}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Ability to work independently with strong prioritization and a results-driven mindset\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:200,\u0026amp;quot;335559740\u0026amp;quot;:276}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Preferred Qualifications:\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Knowledge of agentic AI solutions for EDA automation\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:200,\u0026amp;quot;335559740\u0026amp;quot;:276}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience with CI/CD integration for physical design flows\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:200,\u0026amp;quot;335559740\u0026amp;quot;:276}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Familiarity with compute farm management and job scheduling optimization\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:200,\u0026amp;quot;335559740\u0026amp;quot;:276}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Knowledge of advanced packaging or multi-die integration flows\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:200,\u0026amp;quot;335559740\u0026amp;quot;:276}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;The base salary range is \u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;$185,000 to $240,000\u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026amp;nbsp;depending on experience, level, and business\u0026amp;nbsp;need. This role may be eligible for discretionary\u0026amp;nbsp;bonus, incentives, and benefits.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:200,\u0026amp;quot;335559740\u0026amp;quot;:276}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4691422005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4433382005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Physical Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4691422005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2499","title":"Principal Physical Design Engineer, STA","company_name":"Astera Labs","first_published":"2026-05-20T17:38:52-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Overview\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;br\u0026gt;As an Astera Labs \u0026lt;strong\u0026gt;Principal Physical Design Engineer (STA) \u0026lt;/strong\u0026gt;you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs\u0026#39; portfolio of connectivity ASICs used in the world\u0026#39;s leading cloud service providers, server and network OEMs. This role requires end-to-end STA ownership across design stages, deep technical expertise, and close collaboration with RTL, physical design, and verification teams to ensure robust full-chip timing convergence. This role is fully on-site and in-person.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Drive timing closure from RTL through sign-off, ensuring robust timing across complex SoCs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop and validate SDC constraints, including MMMC setup, to enable accurate and efficient STA analysis.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Define and manage I/O timing budgets across hierarchical designs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Apply advanced sign-off methodologies at TSMC 7nm and below, including OCV/AOCV and PVT effects.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Leverage ETM libraries for hierarchical timing analysis and correlation, balancing runtime and accuracy.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Provide actionable timing feedback at both block and full-chip levels, including root cause analysis and ECO guidance.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Manage large-scale multi-corner/multi-mode STA runs with automation, partitioning, and efficient resource usage.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Generate and validate timing ECOs, partnering with physical design and RTL teams for quick closure.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Partner closely with design, implementation, and verification teams to drive timing convergence, providing sign-off level expertise and guidance.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s in Electrical Engineering or Computer Science required; Master’s preferred.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;≥10 years of experience in timing analysis and sign-off for complex SoCs in Server, Storage, or Networking applications.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Expertise in timing constraints, STA methodology, and timing closure at both block and full-chip level.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows in advanced nodes (7nm or below).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency with Cadence and/or Synopsys physical design/STA toolchains.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong scripting ability (Tcl, Python, Perl).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ability to work independently with strong prioritization and a professional, customer-focused mindset.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with high-speed SerDes or Ethernet PHY timing challenges.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of ECO methodologies, DFT tools, and test coverage analysis.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience working with IP vendors for both RTL and hard-macro integration.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;SystemVerilog/Verilog familiarity.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;The base salary range is USD 209,000.00 USD – USD 250,000.00. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4722151005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4448528005,"location":{"name":"Taipei, Taiwan"},"metadata":[{"id":12122734005,"name":"Country","value":"Taiwan","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Taipei","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Product Applications Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4722151005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2026-351","title":"Principal Product Application Engineer","company_name":"Astera Labs","first_published":"2026-08-10T04:22:34-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Job Description:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As an Astera Labs Principal Product Application Engineer, you will need to provide technical guidance to ODMs to overcome design challenges, generate collateral for existing and new products, and drive innovation by providing insightful feedback to other internal teams to continuously improve products and processes. We need experience supporting the development and designing-in of semiconductor products for PCIe/CXL. There are opportunities to support key ODMs directly, and also to dive deep in the lab to address the challenges associated with leading edge semiconductor products.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, Master’s is preferred.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Minimum of 10 years’ experience designing in complex SoC/silicon products with a high speed (preferably PCIe) interface.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!\u0026lt;strong\u0026gt;\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Experience\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong working knowledge of PCIe LTSSM at a physical layer level, associated standards, and debug. Most recent experience with PCIe 4.0 at a minimum, some experience with 5.0/CXL preferred.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Silicon/System bring-up and debug experience in customer systems.\u0026amp;nbsp;\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Technical ownership of issue resolution: Driving and directing internal teams, and driving communication to customers through FAE and sales teams.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Firsthand experience with lab equipment such as protocol analyzers/exercisers, high-speed oscilloscopes, or BERTs.\u0026amp;nbsp;\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Technical writing skills to generate clear, precise documentation including application notes and similar guides for internal and customer-facing audiences.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Global customer engagement support, with travel as required for on-site activities, reviews, and system bring-up.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred experience\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Triaging complex customer reported issues which require taking into account multiple layers of conditions; for instance, silicon, firmware, hardware board design, and system environment.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Development/support for PCIe or Ethernet Switch or Retimer products.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;PCIe compliance testing methodology and troubleshooting.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Comfort working with software/firmware associated with semiconductor products, such as; Firmware development with C-language, scripting with Python or other equivalent programming languages.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Understanding of Data Center systems like Servers, JBOGs/JBODs, Networking switches/routers/interconnects etc.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184470005,"name":"Copper Product Applications (US_Copper Product Applications)","child_ids":[],"parent_id":null}],"offices":[{"id":4009035005,"name":"Taipei","location":"Taiwan","child_ids":[],"parent_id":4002874005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4697866005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4436935005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose (HQ)","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Product Applications Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4697866005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2570","title":"Principal Product Application Engineer - PCIe","company_name":"Astera Labs","first_published":"2026-05-20T14:23:14-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is seeking a Principal Product Applications Engineer to join our Aries PCIe Retimer team and serve as a critical technical bridge between our customers and engineering organization. As AI infrastructure demands explode, our Aries Smart Retimers are enabling the high-speed, low-latency PCIe connectivity that powers the world\u0026#39;s most advanced data centers—and you\u0026#39;ll be at the center of that growth.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;In this high-impact role, you\u0026#39;ll work directly with hyperscalers, OEMs, and system builders to drive successful adoption of our Aries PCIe products. You\u0026#39;ll combine deep technical expertise with customer-facing skills to solve complex system-level challenges, create compelling technical documentation, and influence product direction based on real-world customer needs. This is an opportunity to shape how next-generation AI and cloud infrastructure connects and scales.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;You\u0026#39;ll collaborate cross-functionally with design engineering, validation, sales, and marketing teams while building strong relationships with customers who are defining the future of computing. If you thrive at the intersection of cutting-edge silicon and customer success, this role offers exceptional visibility and impact.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Customer Technical Engagement\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Serve as the primary technical resource for customers during pre-sales evaluation and post-sales deployment of Aries PCIe retimers\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deliver technical presentations, product training, and demonstrations to customer engineering teams\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Build trusted advisor relationships with key accounts and drive product adoption\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;System-Level Debug \u0026amp;amp; Validation Support\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Lead root cause analysis and debugging of complex PCIe signal integrity and protocol issues in customer systems\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support customer lab bring-up, characterization, and validation activities\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop and execute test plans to reproduce and resolve customer-reported issues\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Technical Documentation \u0026amp;amp; Enablement\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Create application notes, reference designs, and best practices guides for PCIe system implementation\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop collateral that accelerates customer time-to-deployment\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Contribute to product documentation including datasheets and user guides\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional Collaboration\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Partner with product management and engineering to translate customer feedback into product requirements\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support sales teams with technical expertise during customer engagements\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Represent the voice of the customer in internal roadmap and feature discussions\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, Computer Engineering, or related field\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;8+ years of experience in applications engineering, technical support, or system engineering roles\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of PCIe architecture, protocol, and electrical specifications (Gen4/Gen5/Gen6)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience with lab equipment including oscilloscopes, protocol analyzers, and BERT tools\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience debugging high-speed serial interfaces at both the physical and protocol layers\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent written and verbal communication skills with ability to explain complex technical concepts\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop and modify firmware using C to implement features, optimize performance, and resolve technical issues\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Travel to customer sites worldwide to provide on-site technical support, conduct system integration, and drive issue resolution\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience with PCIe retimers, redrivers, or similar connectivity components\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with server, storage, or GPU system architectures\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Background in signal integrity analysis and simulation tools\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Scripting proficiency (Python, TCL) for test automation and data analysis\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Prior experience working directly with hyperscale or enterprise data center customers\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Track record of creating high-quality technical documentation and application notes\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Salary range is $170,500 to $220,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4000702005,"name":"Product Applications","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4736534005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4455681005,"location":{"name":"Shanghai Shi, China"},"metadata":[{"id":12122734005,"name":"Country","value":"China","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Shanghai","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Product Applications Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4736534005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":null,"title":"Principal Product Applications Engineer","company_name":"Astera Labs","first_published":"2026-09-22T02:32:10-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As an Astera Labs Product Applications Engineer, you will be part of a team that supports design-in of Astera Labs’ portfolio of connectivity products by the world’s leading cloud service providers and server and network OEMs. In this role, you will need to provide technical guidance to customers to overcome design challenges, generate collateral for existing and new products, and drive innovation by providing insightful feedback to other internal teams to continuously improve products and processes. You will investigate and duplicate issues reported by customers, and drive critical issues to resolution. There are opportunities to support key customers directly, and also to dive deep in the lab to address the challenges associated with leading edge semiconductor products.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Strong academic and technical background in electrical, electronics, or computer engineering or a closely related field. At a minimum, an engineering bachelor’s degree is required. A master’s degree is preferred.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· A minimum of 10 years’ experience working with cloud service providers or server or network OEM customers to design in complex SoC/silicon products for server, storage, and/or networking applications.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Entrepreneurial spirit, open-minded approach, and can-do attitude. Think and act with the customer in mind!\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Required Experience\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· System HW design and bring-up and debug experience.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Strong knowledge of NRZ/PAM4 SerDes-based protocols like PCIe, Ethernet (25G and above), etc. and/or memory interfaces such as (LP)DDR5/4/3.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Firsthand experience with lab equipment including traffic generators, analyzers, and high-speed oscilloscopes.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· A strong background in high-speed board design and techniques for preserving signal integrity.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Technical writing skills and the ability to generate clear, precise documentation including datasheets, application notes, and similar guides for both internal audiences and customers.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Firmware development and in-system debug with C-language, scripting with Python or other equivalent programming languages.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Development/support for PCIe or Ethernet switch products\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Working with silicon characterization/validation teams to ensure desired device performance is readily achievable in customer systems.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Knowledge of simulation/modeling, schematic capture, and PCB layout tools from Cadence, Altium and others.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Knowledge of simulation tools such as Keysight ADS, SiSoft QCD, and others, for IBIS-AMI analysis.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Understanding of Data Center systems such as servers, compute nodes, JBOGs/JBODs, and networking switches/routers/interconnects, etc.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Solid customer enablement experience\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4185766005,"name":"Fabrics \u0026 Controllers Products (CHN_F\u0026C Prod)","child_ids":[],"parent_id":null}],"offices":[{"id":4002875005,"name":"China","location":"China","child_ids":[4002876005,4061056005,4002878005,4009038005,4002877005],"parent_id":null}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4740715005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4457895005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Product Applications Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4740715005,"updated_at":"2026-10-07T17:04:49-04:00","requisition_id":"2026-497","title":"Principal Product Applications Engineer","company_name":"Astera Labs","first_published":"2026-10-07T17:02:54-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Role Overview\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;As a Principal Engineer on the Scorpio Product Applications team, you will help customers and internal teams deploy high-performance PCIe fabric solutions for rack-scale AI infrastructure. You will translate complex system requirements into practical architectures, lead platform bring-up, and guide the integration of Scorpio switches across demanding CPU, GPU, NIC, storage, and accelerator designs.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;This role connects product strategy, firmware, and real-world system behavior. You will work across hardware, firmware, validation, and customer-facing teams to solve interoperability challenges, accelerate adoption, and shape the next generation of PCIe Gen 6/Gen 7 connectivity. Your work will directly influence how AI systems scale using purpose-built fabrics, UALink, and UCIe.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Product Applications and Customer Enablement\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Lead technical engagements with customers and ecosystem partners to define Scorpio-based PCIe architectures and deployment requirements.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Develop reference designs, application guidance, technical presentations, and system-level collateral that accelerate customer adoption.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Translate customer use cases into clear product requirements, integration plans, and prioritized technical actions.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;PCIe and Firmware Bring-Up\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Drive system bring-up, debug, and interoperability across PCIe hosts, GPUs, NICs, storage devices, and other high-performance endpoints.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Partner with firmware teams to define, implement, and validate device configuration, boot flows, telemetry, recovery mechanisms, and field-debug capabilities.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Analyze link training, enumeration, performance, error handling, and system stability issues using protocol traces, logs, and lab instrumentation.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Build and maintain firmware, validation, and automation workflows that improve debug efficiency and product readiness.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Cross-Functional Product Leadership\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Partner with architecture, design, firmware, validation, and applications teams to resolve complex issues from prototype through production.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Lead root-cause analysis, communicate risks and recommendations, and drive issues to closure with clear ownership and measurable outcomes.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Influence product enhancements and ecosystem interoperability plans for next-generation AI infrastructure connectivity.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Basic Qualifications\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;8–12 years of experience in product applications, systems engineering, firmware, platform validation, or a related semiconductor domain.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Strong understanding of PCIe architecture, including link training, enumeration, configuration space, error handling, performance, and system interoperability.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience with firmware development or debug, including the ability to read code, interpret logs, and collaborate effectively with firmware developers.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Hands-on experience with system bring-up, lab debug, protocol analysis, and root-cause investigation across complex hardware and software stacks.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Strong written and verbal communication skills, with the ability to explain technical issues to both engineering teams and customers.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Preferred Qualifications\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience with PCIe Gen 6 or Gen 7, PCIe fabric switches, retimers, or other high-speed connectivity products.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Familiarity with UALink, UCIe, or emerging scale-up and scale-out interconnect architectures.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience developing validation plans, firmware test strategies, lab automation, or customer-facing technical collateral.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Background supporting AI servers, accelerator platforms, hyperscale infrastructure, or high-performance computing systems.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Demonstrated ability to lead ambiguous, cross-functional technical challenges in a fast-paced, high-growth environment.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Salary range is $207,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184703005,"name":"Fabrics \u0026 Controllers Products (US_F\u0026C Prod)","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4697283005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4436728005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose (HQ)","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Product Applications Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4697283005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2561","title":"Principal Product Applications Engineer - Ethernet","company_name":"Astera Labs","first_published":"2026-05-20T10:00:29-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is seeking a Principal Product Applications Engineer to join our Taurus Ethernet Smart Cable Modules team and drive customer success at the forefront of AI infrastructure connectivity. As data centers scale to meet explosive AI workload demands, our Taurus products are enabling the high-bandwidth, low-latency Ethernet fabric connections that power next-generation GPU clusters and disaggregated computing architectures.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;In this role, you\u0026#39;ll be the technical expert customers rely on to successfully deploy Taurus Ethernet solutions in their most demanding environments. You\u0026#39;ll work hands-on with hyperscalers, OEMs, and AI system builders to debug complex physical layer challenges, deliver technical enablement, and ensure seamless product integration. Your customer insights will directly influence how we evolve our products to meet the market\u0026#39;s most pressing connectivity needs.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This is a unique opportunity to combine deep Ethernet and physical layer expertise with meaningful customer impact at a hyper-growth company defining the future of AI connectivity. You\u0026#39;ll collaborate across engineering, sales, and product teams while building relationships with the world\u0026#39;s most innovative technology companies.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Customer Technical Engagement\u0026lt;/strong\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Serve as the primary technical resource for customers evaluating and deploying Taurus Ethernet Smart Cable Modules\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deliver technical presentations, product training, and hands-on demonstrations to customer engineering teams\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Build trusted relationships with key accounts and drive successful product adoption\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;System-Level Debug \u0026amp;amp; Validation Support\u0026lt;/strong\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Lead root cause analysis and debugging of complex Ethernet physical layer and link issues in customer systems\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support customer lab bring-up, characterization, and system validation activities\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop and execute test plans to reproduce and resolve customer-reported issues\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Technical Documentation \u0026amp;amp; Enablement\u0026lt;/strong\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Create application notes, integration guides, and best practices documentation for Ethernet system implementation\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop technical collateral that accelerates customer time-to-deployment\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Contribute to product documentation including datasheets and user guides\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional Collaboration\u0026lt;/strong\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Partner with product management and engineering to translate customer feedback into product requirements\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support sales teams with technical expertise during pre-sales and post-sales engagements\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Represent voice of the customer in internal roadmap discussions and feature prioritization\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Willingness to travel for work within US and to Asia.\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, Computer Engineering, or related field\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;8+ years of experience in applications engineering, technical support, or system engineering roles\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of Ethernet physical layer specifications (100G/200G/400G/800G)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience with lab equipment including oscilloscopes, protocol analyzers, and BER test tools\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience debugging high-speed serial interfaces and signal integrity challenges\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent written and verbal communication skills with ability to convey complex technical concepts\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience with optical modules, active cables, or similar high-speed connectivity components\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with AI/ML system architectures, GPU clusters, or data center networking\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Background in signal integrity analysis and simulation\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Scripting proficiency (Python, TCL) for test automation and data analysis\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Prior experience working with hyperscale or enterprise data center customers\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of Ethernet consortium specifications and industry standards\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Salary range is $158,400 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4000702005,"name":"Product Applications","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4690430005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4433012005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Product Applications Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4690430005,"updated_at":"2026-10-07T11:01:02-04:00","requisition_id":"2490","title":"Principal Product Applications Engineer – Memory \u0026 CXL","company_name":"Astera Labs","first_published":"2026-04-29T13:45:01-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;h1\u0026gt;Principal Product Applications Engineer – Leo\u0026lt;/h1\u0026gt;\n\u0026lt;h2\u0026gt;About the Role\u0026lt;/h2\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is looking for a \u0026lt;strong\u0026gt;Principal Product Applications Engineer\u0026lt;/strong\u0026gt; to support the deployment of our Leo Smart Memory Controller and Extender solutions in next-generation server, AI, and datacenter platforms.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This role sits at the intersection of \u0026lt;strong\u0026gt;memory architecture, system integration, hardware/software debug, and customer engineering\u0026lt;/strong\u0026gt;. You will work directly with customers and Astera Labs engineering teams to bring up platforms, troubleshoot complex memory and system issues, support product development, and drive solutions from initial integration through production.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;We are looking for an experienced engineer with \u0026lt;strong\u0026gt;strong DDR/DRAM and memory subsystem expertise\u0026lt;/strong\u0026gt; who enjoys solving complex system-level problems and working with customers. Experience with CXL and related high-speed technologies is highly relevant. Firmware or platform software experience is valuable, but not required.\u0026lt;/p\u0026gt;\n\u0026lt;h2\u0026gt;What You Will Do\u0026lt;/h2\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Serve as a technical point of contact for customers integrating Leo products into server, AI, and datacenter platforms.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Support customer platform bring-up, integration, debug, and production deployment.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Troubleshoot complex memory, hardware, system, and software interactions.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Analyze DDR and memory subsystem behavior, including initialization, training, configuration, performance, and error handling.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Work with customers and internal engineering teams to isolate root causes and drive technical issues through resolution.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Collaborate with hardware, firmware, validation, systems, and product engineering teams on customer issues and new product capabilities.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Review system architectures, schematics, logs, debug data, and technical documentation to identify and resolve issues.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Support integration and debug of CXL, PCIe, and other high-speed interfaces.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Translate customer requirements and technical issues into actionable engineering requirements and product feedback.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Create technical documentation, application notes, debug reports, and customer-facing technical material.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Participate in customer technical reviews, platform bring-up activities, and product demonstrations.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Help identify opportunities to improve product functionality and customer deployment experience.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h2\u0026gt;What You Bring\u0026lt;/h2\u0026gt;\n\u0026lt;h3\u0026gt;Required\u0026lt;/h3\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Significant hands-on experience with \u0026lt;strong\u0026gt;DDR/DRAM and memory subsystems\u0026lt;/strong\u0026gt; in server, datacenter, SoC, controller, semiconductor, or related computing environments.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Strong understanding of memory architecture and the interaction between memory, CPUs/SoCs, controllers, and platform components.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Experience with \u0026lt;strong\u0026gt;memory bring-up, debug, validation, integration, or system-level troubleshooting\u0026lt;/strong\u0026gt;.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Ability to analyze complex technical problems and work across multiple engineering disciplines to identify root cause.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Experience working with hardware, systems, validation, product, or customer engineering teams.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Strong technical communication skills, including the ability to explain complex memory and system concepts clearly to customers and engineering teams.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Bachelor\u0026#39;s or Master\u0026#39;s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Typically 8+ years of relevant industry experience.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h3\u0026gt;Preferred\u0026lt;/h3\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Experience with \u0026lt;strong\u0026gt;CXL or CXL memory\u0026lt;/strong\u0026gt;.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Experience with \u0026lt;strong\u0026gt;PCIe or other high-speed interconnects\u0026lt;/strong\u0026gt;.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Hands-on firmware or platform software development/debugging, particularly with \u0026lt;strong\u0026gt;C/C++\u0026lt;/strong\u0026gt;.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Experience with BIOS, UEFI, BMC, OpenBMC, or other platform firmware.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Experience with memory initialization, training, controller configuration, or platform firmware.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Knowledge of memory RAS, ECC, PPR, patrol scrubbing, or related reliability technologies.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Experience with server or hyperscale datacenter platforms.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Experience with silicon or system bring-up.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Experience using protocol analyzers, oscilloscopes, logic analyzers, or other hardware debug equipment.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Experience working with OEMs, ODMs, hyperscalers, or semiconductor customers.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Previous Product Applications, FAE, systems engineering, or other customer-facing technical experience.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Linux, drivers, or system software experience.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h2\u0026gt;Who Will Be Successful\u0026lt;/h2\u0026gt;\n\u0026lt;p\u0026gt;The strongest candidates will bring \u0026lt;strong\u0026gt;deep practical knowledge of DDR/DRAM and memory systems\u0026lt;/strong\u0026gt; combined with the ability to work across hardware, systems, and customer organizations.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;We are open to candidates coming from different technical paths, including \u0026lt;strong\u0026gt;memory engineering, applications engineering, systems engineering, validation, firmware, platform engineering, or semiconductor product development\u0026lt;/strong\u0026gt;.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Direct CXL experience is valuable, but candidates with strong DDR/memory expertise and relevant adjacent experience are encouraged to apply.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This role is well suited for an engineer who enjoys going beyond a narrow technical discipline—working with customers, investigating difficult system problems, collaborating with engineering teams, and helping shape how products are deployed in next-generation AI and datacenter platforms.\u0026lt;/p\u0026gt;\n\u0026lt;h2\u0026gt;Location\u0026lt;/h2\u0026gt;\n\u0026lt;p\u0026gt;Santa Clara, CA / Hybrid\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Compensation\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;The base salary range for this role is \u0026lt;strong\u0026gt;$175,000 – $230,000 USD\u0026lt;/strong\u0026gt;. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;em\u0026gt;Astera Labs is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.\u0026lt;/em\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4000702005,"name":"Product Applications","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4725093005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4449971005,"location":{"name":"Vancouver, British Columbia, Canada"},"metadata":[{"id":12122734005,"name":"Country","value":"Canada","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Vancouver","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Product Applications Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4725093005,"updated_at":"2026-10-06T11:47:23-04:00","requisition_id":null,"title":" Principal Product Applications Engineer -  Scorpio","company_name":"Astera Labs","first_published":"2026-08-17T22:02:58-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is redefining the fabric of AI infrastructure with our Scorpio Smart Fabric Switches — purpose-built silicon that connects GPUs, CPUs, and accelerators at rack scale. As a Principal Product Applications Engineer on the Scorpio team, you will be the technical face of our switching portfolio to the world\u0026#39;s leading hyperscalers, AI system builders, and platform partners, guiding them from first evaluation through production deployment.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This is a high-impact, customer-facing role at the center of one of the fastest-growing categories in semiconductors. You will lead customer system design-in and Scorpio-related debug, develop customer-facing collateral, lead cross-functional Scorpio-related initiatives, and drive and validate new features across PCIe Gen 6 / Gen 7 \u0026amp;amp; UALink platforms — directly influencing the roadmap of a hyper-growth company powering the next generation of AI compute.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Customer Enablement\u0026lt;/strong\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Lead technical engagements with hyperscalers, ODMs, and AI system partners from architecture discussions through design-in and evaluation\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Own on-site and remote bring-up, debug, and performance tuning of Scorpio-based platforms at customer sites\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Translate customer requirements into actionable feedback for product, silicon, and firmware teams\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Post-Silicon Validation \u0026amp;amp; System Integration\u0026lt;/strong\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Influence post-silicon validation plans and execute system-level integration on next-generation switching platforms\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Debug complex multi-domain issues spanning protocol (UALink, UCIe, PCIe Gen 6/7), signal integrity, firmware, and software stacks\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Partner with hardware, firmware, and SI/PI teams to root-cause issues and deliver production-ready solutions\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Technical Leadership \u0026amp;amp; Cross-Functional Influence\u0026lt;/strong\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Serve as the go-to Scorpio applications expert across sales, marketing, product, and engineering\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Mentor junior applications engineers and represent Astera Labs at industry forums, standards bodies, and customer executive reviews\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Author white papers, technical collateral, and training materials that scale the team\u0026#39;s impact\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;8+ years of experience in product applications, systems engineering, or post-silicon validation on high-speed connectivity or networking silicon\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of the physical layer and high-speed serial interfaces (PCIe, Ethernet, UALink, UCIe, or similar)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience with lab bring-up, debug, and system-level integration — including scopes, BERTs, and protocol analyzers\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven track record engaging directly with hyperscaler, cloud, or Tier-1 OEM/ODM customers on complex technical deployments\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent communication skills with the ability to translate deep technical detail into clear customer-facing narratives\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;MS or PhD in Electrical Engineering, Computer Engineering, or a related field\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Direct experience with PCIe Gen 6 / Gen 7, UALink, or UCIe protocols and compliance testing\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with AI/ML rack-scale architectures, GPU fabrics, and accelerator interconnects\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Scripting and automation experience (Python, shell) for validation and diagnostics\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Background contributing to standards bodies (PCI-SIG, UALink Consortium, UCIe) or authoring technical publications\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p class=\u0026quot;p8i6j01 paragraph\u0026quot;\u0026gt;Salary range is $165,000 to $210,000 CAN depending on experience, level, and business need. This role may be eligible for discretionary bonuses, incentives, and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184496005,"name":"Fabrics \u0026 Controllers Product Applications (CAN_F\u0026C Prod Apps)","child_ids":[],"parent_id":null}],"offices":[{"id":4003931005,"name":"Vancouver","location":"Canada","child_ids":[],"parent_id":4004709005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4680695005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4428444005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Product Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4680695005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2444","title":"Principal Product Engineer ","company_name":"Astera Labs","first_published":"2026-04-01T19:40:31-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Job Overview:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;We are seeking an experienced and hands-on \u0026lt;strong\u0026gt;Principal Product Engineer\u0026amp;nbsp;\u0026lt;/strong\u0026gt;to lead and develop next generation high-speed, high performance and low power semiconductor products in advanced process node. The ideal candidate possesses breadth of industry experience in high-speed product development in the field of product and/or test engineering, can apply fundamentals in circuit, ATE, and test program to aid problem solving, and is a self-driven, result focused go-getter in the pursuit of goals and objectives.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Minimum of 8 years of experience in the field of post silicon product development dealing with high-speed I/O (product test or validation)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Have gone through at least one cycle of full product development life cycle\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong academic/technical background in electrical or computer engineering; Bachelor’s is required; MS preferred\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong problem-solving skills that involve system level analysis with test hardware, test program and DUT.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Digital and analog circuit level understanding for DUT\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent team player with great communication skills\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Professional attitude with the ability to prioritize a dynamic list of multiple tasks\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Experience\u0026lt;/strong\u0026gt;:\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Hands on experience with using the Advantest 93k ATE platform with specific skills updating ATE test programs for wafer sort and final test solutions or similar ATE platform\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Detailed mindset monitoring device ATE test yields, ATE test time, device quality and rolling out new ATE test programs using consistent BKMs\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong data analysis skills using tools such as JMP or Spotfire calculating limits and drawing conclusions\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Energetic work mindset meeting the demands of shipping quality parts to Astera Labs’ customers through the manufacturing stage of development\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands on experience in product/package qualification\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Experience:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Hands-on knowledge of NRZ/PAM4 SerDes protocols like PCIe (Gen3 and above), Ethernet (25G and above), etc. and/or memory interfaces such as (LP)DDR5/4\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Working with silicon validation teams to ensure device performance meets production requirements\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Firmware development in C/C++, scripting in Python, or other equivalent programming experience\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;The base salary range is USD 185,00 - USD 240,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/div\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4728996005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4452032005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":null,"value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4728996005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2713","title":"Principal Product Manager, Fiber Connectivity","company_name":"Astera Labs","first_published":"2026-09-02T15:51:44-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Principal Product Manager, Fiber Connectivity\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;San Jose, California, United States\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Job Summary:\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is redefining the connectivity fabric of rack-scale AI infrastructure, with optical connectivity becoming increasingly important to the next generation of scale-up and scale out systems.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As a Principal Product Manager for Fiber Connectivity, you will own the link between AI system architecture and commercial product adoption. You will define a portfolio of passive optical connectivity solutions, set customer-driven product requirements, and drive products from concept through qualification, deployment, and production.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Optical connectivity is becoming a system-level architecture decision in AI infrastructure, not simply a component choice. This role spans optical performance, system integration, manufacturing scale, supply chain, customer qualification, and commercial execution. You will work with hyperscalers, AI infrastructure companies and optical ecosystem partners.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Responsibilities\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026amp;nbsp;Define the product strategy and multi-year roadmap for passive optical connectivity at the fiber-to-chip and system interfaces of high-density AI infrastructure.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026amp;nbsp;Identify target applications, market opportunities, technology transitions, and competitive threats, serving as the voice of the customer for hyperscalers, AI infrastructure companies, system OEMs and ecosystem partners.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026amp;nbsp;Set customer-driven product attribute targets and make clear tradeoffs across optical performance, density, cost, manufacturability, reliability, supply chain, adoption, and time to market.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026amp;nbsp;Develop go-to-market strategy and launch plans, including market assessment, competitive analysis, positioning, technical content, and sales enablement.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026amp;nbsp;Execute product development from concept through requirements, development, qualification, customer deployment, production ramp, and sustaining support.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026amp;nbsp;Lead cross-functional relationships across optical, mechanical, electrical, systems, manufacturing, operations, quality, supply chain, applications, sales, and finance.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026amp;nbsp;Establish manufacturing, supplier, automation, quality, reliability, test, yield, capacity, and cost-reduction strategies for high-volume production.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Partner with sales and applications teams to secure design wins, support customer commitments, and drive adoption.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s degree in engineering, physics, materials science, business, or a related field.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;10+ years of experience in product management, product line management, engineering, applications, business development, or a related function.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026amp;nbsp;Experience developing and commercializing complex hardware products.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026amp;nbsp;Experience in optics, photonics, fiber optics, optical connectivity, optical packaging, or a related technology.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026amp;nbsp;Experience working across engineering, manufacturing, operations, supply chain, sales, and commercial organizations.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent communication, presentation, and cross-functional leadership skills.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026amp;nbsp;Willingness to travel internationally as needed.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;MBA or advanced technical degree.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Market knowledge of AI, cloud, networking, data center, server, and high performance computing infrastructure.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026amp;nbsp;Strong understanding of passive optical connectivity, optical coupling, fiber assemblies, connectors, alignment, and optical and mechanical tolerances.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026amp;nbsp;Experience with co-packaged optics, near-package optics, optical I/O, scale-up optical interconnects, or related emerging architectures.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with high-volume manufacturing, supplier qualification, new product introduction, or production ramp.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven ability to work directly with hyperscalers, major system companies and optical ecosystem partners\u0026lt;strong\u0026gt; \u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Base salary range is $185,000 to $240,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184399005,"name":"Signal Connectivity Group","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4717583005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4446241005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Product Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4717583005,"updated_at":"2026-09-30T12:26:13-04:00","requisition_id":"2026-137","title":"Principal Product Technical Leader — AEC/SCM","company_name":"Astera Labs","first_published":"2026-08-04T01:25:05-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;h2\u0026gt;Role Overview\u0026lt;/h2\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is seeking a hands-on \u0026lt;strong\u0026gt;Principal Product Technical Leader\u0026lt;/strong\u0026gt; to drive product integration for Active Electrical Cables (AECs) and Smart Cable Modules (SCMs) used in rack-scale AI infrastructure. You will serve as a technical owner across high-speed silicon and retimers, firmware, PCB or flex circuitry, cable assemblies, connectors, mechanical and thermal design, signal integrity, validation, manufacturing, and customers.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;You will translate system and customer requirements, engineering data, and field feedback into reliable, production-ready products. This is an individual-contributor role: you will lead complex technical investigations, resolve cross-domain issues, strengthen product readiness, and improve repeatable integration and debug practices. You should bring deep expertise in at least one relevant discipline and working knowledge across adjacent domains.\u0026lt;/p\u0026gt;\n\u0026lt;h2\u0026gt;Key Responsibilities\u0026lt;/h2\u0026gt;\n\u0026lt;h3\u0026gt;Product integration and validation\u0026lt;/h3\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Define product-level interfaces, integration plans, risks, validation checkpoints, and readiness criteria from design through production release.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Influence architecture and design decisions early, finding creative, practical solutions to tradeoffs across signal integrity, retimer and firmware integration, power, thermal performance, mechanical constraints, manufacturability, cost, and schedule.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead product-level electrical compliance and system validation for AEC/SCM products, including channel performance, eye margins, jitter, equalization, link training, BER, interoperability, and resolution of system-level issues.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Direct and review AEC/SCM hardware validation, including board-level probing, circuit verification, functional testing under nominal, corner, mechanical, and environmental conditions, and reliability/failure analysis; ensure results are correlated to design requirements and corrective actions are driven to closure.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive root-cause analysis for issues spanning silicon, firmware, hardware, SI, mechanical, thermal, test, and manufacturing teams.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h3\u0026gt;Production readiness and technical execution\u0026lt;/h3\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Partner with NPI, manufacturing, quality, and operations teams to transition products from development into volume production.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive DFM/DFA/DFT reviews, production-test development, test-coverage improvements, yield analysis, and manufacturability feedback.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Own technical investigations and corrective actions for complex failures, process excursions, production escapes, and field issues.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Establish clear product specifications, issue-tracking practices, technical reports, and readiness reviews.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h3\u0026gt;Customer and cross-functional leadership\u0026lt;/h3\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Provide technical direction during customer bring-up, interoperability testing, platform qualification, and escalations.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with applications and customer engineering teams to resolve design-in challenges and translate field feedback into product improvements.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead cross-functional design and integration reviews across hardware, firmware, SI, mechanical, test, manufacturing, and quality.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Mentor engineers and improve documentation, debug workflows, integration methods, and engineering standards.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p class=\u0026quot;p8i6j01 paragraph\u0026quot;\u0026gt;The base salary range is $160,000 USD - $200,000 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184210005,"name":"Advanced Hardware Engineering","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4733819005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4454560005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":null,"value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4733819005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2728","title":"Principal / Senior Principal Design Verification Engineer- CXL / PCIe / Ethernet  ","company_name":"Astera Labs","first_published":"2026-09-14T18:07:56-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;u\u0026gt;Principal / Senior Principal Design Verification Engineer – CXL / PCIe / Ethernet:\u0026lt;/u\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;We are seeking an experienced\u0026amp;nbsp;\u0026lt;strong\u0026gt;Principal / Senior Principal Design Verification Engineer\u0026lt;/strong\u0026gt;\u0026amp;nbsp;to lead the verification of next-generation connectivity IPs and SoCs powering AI and cloud infrastructure. This is a highly visible technical leadership role where you will define verification strategies, drive methodology improvements, mentor engineering teams, and collaborate across architecture, RTL, firmware, validation, and silicon teams to ensure first-pass silicon success.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;The ideal candidate is passionate about building world-class verification environments, has deep expertise in protocol verification, and enjoys solving complex architectural challenges.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Technical Leadership\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Lead the verification strategy for complex IPs and SoC subsystems from architecture through silicon.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Define verification methodologies, reusable verification frameworks, and best practices across multiple programs.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Drive verification planning, execution, coverage closure, and sign-off.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Identify verification risks early and proactively drive mitigation plans.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Lead technical reviews including architecture, RTL, verification, and tape-out readiness reviews.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Design Verification\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Architect and develop scalable UVM/System Verilog verification environments.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Develop constrained-random, coverage-driven verification methodologies.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Design scoreboards, protocol monitors, checkers, assertions (SVA), and functional coverage models.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Debug complex RTL, protocol, timing, and integration issues.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Drive regression planning, automation, and continuous integration improvements.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Develop reusable VIP and verification infrastructure across multiple product lines.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Protocol Verification\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Lead verification efforts involving one or more of:\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Compute Express Link (CXL 2.x / 3.x)\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;PCI Express (Gen4/Gen5/Gen6)\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Ethernet (10G–800G)\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;AXI, APB, AHB\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;High-speed SerDes interfaces\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Memory interfaces including DDR/LPDDR/HBM (preferred)\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional Collaboration\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Work closely with Architecture teams to influence design for verification.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Partner with RTL designers during implementation and debug.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with Firmware, Emulation, FPGA, Post-Silicon Validation, and System Engineering teams.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Support customer issue analysis and silicon bring-up when required.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Technical Mentorship\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Mentor and coach verification engineers across multiple experience levels.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Establish verification standards and engineering excellence across the organization.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Drive innovation in automation, verification productivity, and quality metrics.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Qualifications\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor\u0026#39;s or Master\u0026#39;s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Minimum10+ years (Principal) or 15+ years (Senior Principal) of experience in Design Verification.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong expertise in System Verilog and UVM.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Extensive experience in verification planning, execution, and sign-off.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Deep understanding of constrained-random verification and coverage-driven methodologies.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong experience with assertions (SVA), functional coverage, and protocol compliance.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Excellent debugging skills involving RTL, simulation, protocol analysis, and waveform debugging.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience with industry-standard simulators such as Synopsys VCS, Cadence Xcelium, or Siemens Questa.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Technical Expertise\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Strong experience in several of the following areas:\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;CXL Cache, Memory, and I/O protocols\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;PCIe Transaction, Data Link, and Physical Layers\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Ethernet MAC/PCS/PMA architecture\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Coherency protocols\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;High-speed interconnects\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;AI accelerator connectivity\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Data center SoC architecture\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Multi-chip and chiplet-based systems\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Performance verification\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Low-power verification\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;CDC/RDC verification\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Formal Verification\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Portable Stimulus (PSS)\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Python, Perl, Tcl, or similar scripting languages\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Emulation and FPGA prototyping\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Leadership Expectations\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Own technical direction for large verification programs.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Influence architecture and product quality through early engagement.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Drive cross-functional execution across geographically distributed teams.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Establish reusable verification IP and methodology.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Mentor engineers and help grow technical capability within the organization.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Champion engineering excellence, quality, and continuous improvement.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience leading verification for large SoCs or complex connectivity IPs.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Proven success delivering multiple first-pass silicon programs.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience with AI infrastructure, cloud networking, or hyperscale data center technologies.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with customer-facing debug and post-silicon issue resolution.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li style=\u0026quot;text-align: left;\u0026quot;\u0026gt;Contributions to verification methodology, reusable frameworks, or industry standards are a strong plus.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Salary range will be is $185,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4185028005,"name":"Design Verification (DNU) (US_DV_CCE1)","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4733808005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4454554005,"location":{"name":"Taipei, Taiwan"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":null,"value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4733808005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2727","title":"Principal / Senior Principal Design Verification Engineer- CXL / PCIe / Ethernet  ","company_name":"Astera Labs","first_published":"2026-09-14T18:07:17-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;u\u0026gt;Principal / Senior Principal Design Verification Engineer – CXL / PCIe / Ethernet:\u0026lt;/u\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;We are seeking an experienced\u0026amp;nbsp;\u0026lt;strong\u0026gt;Principal / Senior Principal Design Verification Engineer\u0026lt;/strong\u0026gt;\u0026amp;nbsp;to lead the verification of next-generation connectivity IPs and SoCs powering AI and cloud infrastructure. This is a highly visible technical leadership role where you will define verification strategies, drive methodology improvements, mentor engineering teams, and collaborate across architecture, RTL, firmware, validation, and silicon teams to ensure first-pass silicon success.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;The ideal candidate is passionate about building world-class verification environments, has deep expertise in protocol verification, and enjoys solving complex architectural challenges.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Technical Leadership\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Lead the verification strategy for complex IPs and SoC subsystems from architecture through silicon.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Define verification methodologies, reusable verification frameworks, and best practices across multiple programs.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Drive verification planning, execution, coverage closure, and sign-off.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Identify verification risks early and proactively drive mitigation plans.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Lead technical reviews including architecture, RTL, verification, and tape-out readiness reviews.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Design Verification\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Architect and develop scalable UVM/System Verilog verification environments.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Develop constrained-random, coverage-driven verification methodologies.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Design scoreboards, protocol monitors, checkers, assertions (SVA), and functional coverage models.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Debug complex RTL, protocol, timing, and integration issues.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Drive regression planning, automation, and continuous integration improvements.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Develop reusable VIP and verification infrastructure across multiple product lines.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Protocol Verification\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Lead verification efforts involving one or more of:\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Compute Express Link (CXL 2.x / 3.x)\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;PCI Express (Gen4/Gen5/Gen6)\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Ethernet (10G–800G)\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;AXI, APB, AHB\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;High-speed SerDes interfaces\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Memory interfaces including DDR/LPDDR/HBM (preferred)\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional Collaboration\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Work closely with Architecture teams to influence design for verification.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Partner with RTL designers during implementation and debug.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with Firmware, Emulation, FPGA, Post-Silicon Validation, and System Engineering teams.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Support customer issue analysis and silicon bring-up when required.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Technical Mentorship\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Mentor and coach verification engineers across multiple experience levels.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Establish verification standards and engineering excellence across the organization.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Drive innovation in automation, verification productivity, and quality metrics.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Qualifications\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor\u0026#39;s or Master\u0026#39;s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Minimum10+ years (Principal) or 15+ years (Senior Principal) of experience in Design Verification.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong expertise in System Verilog and UVM.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Extensive experience in verification planning, execution, and sign-off.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Deep understanding of constrained-random verification and coverage-driven methodologies.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong experience with assertions (SVA), functional coverage, and protocol compliance.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Excellent debugging skills involving RTL, simulation, protocol analysis, and waveform debugging.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience with industry-standard simulators such as Synopsys VCS, Cadence Xcelium, or Siemens Questa.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Technical Expertise\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Strong experience in several of the following areas:\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;CXL Cache, Memory, and I/O protocols\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;PCIe Transaction, Data Link, and Physical Layers\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Ethernet MAC/PCS/PMA architecture\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Coherency protocols\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;High-speed interconnects\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;AI accelerator connectivity\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Data center SoC architecture\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Multi-chip and chiplet-based systems\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Performance verification\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Low-power verification\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;CDC/RDC verification\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Formal Verification\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Portable Stimulus (PSS)\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Python, Perl, Tcl, or similar scripting languages\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Emulation and FPGA prototyping\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Leadership Expectations\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Own technical direction for large verification programs.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Influence architecture and product quality through early engagement.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Drive cross-functional execution across geographically distributed teams.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Establish reusable verification IP and methodology.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Mentor engineers and help grow technical capability within the organization.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Champion engineering excellence, quality, and continuous improvement.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience leading verification for large SoCs or complex connectivity IPs.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Proven success delivering multiple first-pass silicon programs.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience with AI infrastructure, cloud networking, or hyperscale data center technologies.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with customer-facing debug and post-silicon issue resolution.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li style=\u0026quot;text-align: left;\u0026quot;\u0026gt;Contributions to verification methodology, reusable frameworks, or industry standards are a strong plus.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Salary range will depend on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184258005,"name":"Design Verification","child_ids":[],"parent_id":null}],"offices":[{"id":4002874005,"name":"Taiwan","location":"Taipei, Taiwan","child_ids":[4061060005,4009035005],"parent_id":null}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4733814005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4454557005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Analog/AMS Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4733814005,"updated_at":"2026-10-05T13:54:34-04:00","requisition_id":"2026-508","title":"Principal SerDes Bring-up Validation Engineer ","company_name":"Astera Labs","first_published":"2026-10-05T13:54:34-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;h1 class=\u0026quot;wnfdnti _1ibi0s33y _1ibi0s34u\u0026quot; data-pm-slice=\u0026quot;1 1 []\u0026quot;\u0026gt;Principal SerDes Bring-up Validation Engineer\u0026amp;nbsp;\u0026lt;/h1\u0026gt;\n\u0026lt;h2 class=\u0026quot;wnfdnti _1ibi0s33y _1ibi0s34u\u0026quot;\u0026gt;Role Overview\u0026lt;/h2\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Astera Labs is seeking a Principal SerDes Bring-up Validation Engineer to join a cutting-edge mixed-signal design team and lead end-to-end post-silicon bring-up, validation, and characterization. You will own bring-up and characterization strategies from the ground up, translating design and product requirements into measurable test objectives, pass/fail criteria, and schedules, and driving hands-on lab work to verify silicon against specification and performance targets.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;As a hyper-growth company building the purpose-built connectivity that powers rack-scale AI infrastructure, the speed and rigor of our silicon validation directly shape what we can ship. You will partner closely with AMS design, firmware, and system teams to build automated test frameworks, debug complex analog and digital interactions at the physical layer, and deliver clear, data-driven recommendations that influence product direction. This is a high-impact role for a deep technical expert who thrives on hands-on problem solving and mentoring across disciplines.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Design, develop, and execute bring-up plans.\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; Own end\u0026lt;/span\u0026gt;‑\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;to\u0026lt;/span\u0026gt;‑\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;end post\u0026lt;/span\u0026gt;‑\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;silicon bring up and characterization strategies, translating design/product requirements into measurable test objectives, pass/fail criteria, and schedules.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Drive design reviews and specification alignment.\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; Participate in architecture and design\u0026lt;/span\u0026gt;‑\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;spec reviews to ensure testability, trace requirements to verification plans, and influence design tradeoffs to meet performance and reliability targets.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Lead hands\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;‑\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;on test execution and bring\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;‑\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;up.\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; Perform silicon block level bring\u0026lt;/span\u0026gt;‑\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;up, functional and parametric testing, interop checks, and performance benchmarking; rapidly iterate on test flows to accelerate time\u0026lt;/span\u0026gt;‑\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;to\u0026lt;/span\u0026gt;‑\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;data.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Build and maintain automation frameworks.\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; Develop scalable test automation, data capture, and analysis pipelines to increase throughput, reproducibility, and coverage across mixed\u0026lt;/span\u0026gt;‑\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;signal test benches.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Debug and optimize system performance.\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; Diagnose complex failures and performance bottlenecks across analog, digital, firmware, and protocol layers; propose and validate corrective actions to improve stability, yield, and power/performance tradeoffs.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Root\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;‑\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;cause cross\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;‑\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;domain failures.\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; Trace issues to circuit, package, firmware, or protocol interactions using lab measurements, waveform analysis, and system\u0026lt;/span\u0026gt;‑\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;level tests; coordinate with design, package, and firmware teams to implement fixes.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;7\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Collaborate with cross\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;‑\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;functional teams.\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; Work closely with mixed\u0026lt;/span\u0026gt;‑\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;signal design, firmware, system engineering, and manufacturing to deliver detailed results, root\u0026lt;/span\u0026gt;‑\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;cause analyses, optimization recommendations, and formal validation/compliance reports.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;8\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Document findings and improve methodologies.\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; Produce clear debug reports, formal characterization summaries, and recommendations for design/process/test improvements; contribute to failure analysis (FA) best practices and knowledge base.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;9\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Develop test software and platform integrations.\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; Write robust Python test scripts and control interfaces to configure, monitor, and collect status from multiple DSP and hardware platforms, improving firmware stability and automating regression suites.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;10\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Measure and communicate impact.\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; Define key validation metrics, track coverage and defect trends, and present data\u0026lt;/span\u0026gt;‑\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;driven conclusions to stakeholders to influence product direction and release decisions.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;br\u0026gt;\u0026lt;br\u0026gt;\u0026lt;/span\u0026gt;\n\u0026lt;h2 class=\u0026quot;wnfdnti _1ibi0s33y _1ibi0s34u\u0026quot; data-pm-slice=\u0026quot;1 1 []\u0026quot;\u0026gt;Basic Qualifications\u0026lt;/h2\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdntf\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, Computer Engineering, or a related field.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;8-12 years of hands-on experience in mixed-signal, high-speed lab environments executing characterization and validation with industry instruments such as protocol analyzers, BERTs, real-time oscilloscopes, sampling scopes, TDRs, and VNAs.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Proven track record in post-silicon validation and bring-up of high-speed PHYs or retimers, with a strong understanding of the physical layer and experience developing characterization flows and validating silicon against specifications.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Deep understanding of NRZ and PAM4 architectures and high-speed building blocks (PLLs, CTLE, DFE, FFE, transmitter equalization), with the ability to investigate jitter sources, CDR/PLL behavior, crosstalk, and power integrity issues.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Practical experience bringing up and debugging retimers, including equalization tuning, pass-through operation, clocking strategies, and reset and link sequencing.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Strong programming ability in Python and C/C++ for test automation, data analysis, and firmware interaction, paired with exceptional troubleshooting skills and excellent written and verbal communication.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h2 class=\u0026quot;wnfdnti _1ibi0s33y _1ibi0s34u\u0026quot;\u0026gt;Preferred Qualifications\u0026lt;/h2\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdntf\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;MS or PhD in Electrical Engineering or a related field to demonstrate advanced technical depth and specialization.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Hands-on proficiency with signal integrity test equipment and methodologies (BERTs, VNAs, oscilloscopes, sampling scopes, TDRs, advanced probing) and experience designing and debugging lab characterization and demo boards.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Working knowledge of IEEE 802.3 Ethernet standards and experience validating Ethernet PHYs, link training, auto-negotiation, and compliance across speeds and media types.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Practical understanding of serial interfaces such as I2C, I3C, SPI, and UART for device bring-up, firmware interaction, and system integration.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Proven ability to translate SI/PI simulation results into testable lab plans and document findings that drive design or process improvements.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Salary range is $185,000 to $240,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184482005,"name":"AMS Design (US_AMS Design)","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4613831005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4397108005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":"Advanced Hardware Engineering","value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"System Validation","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4613831005,"updated_at":"2026-09-28T14:19:30-04:00","requisition_id":"2047-6","title":"Principal Silicon Validation Engineer","company_name":"Astera Labs","first_published":"2025-12-23T13:03:15-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p data-start=\u0026quot;145\u0026quot; data-end=\u0026quot;476\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Overview:\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p data-start=\u0026quot;145\u0026quot; data-end=\u0026quot;476\u0026quot;\u0026gt;The mission of this role is to develop and execute electrical validation tests that quantify parametric device performance and operating margins across all system conditions. The validation team upholds customer requirements to the highest standard and serves as the final authority in certifying a product’s parametric compliance.\u0026lt;/p\u0026gt;\n\u0026lt;p data-start=\u0026quot;478\u0026quot; data-end=\u0026quot;1077\u0026quot;\u0026gt;Astera Labs is seeking motivated \u0026lt;strong data-start=\u0026quot;511\u0026quot; data-end=\u0026quot;568\u0026quot;\u0026gt;Principal / Senior Principal Post-Silicon Validation Engineers\u0026lt;/strong\u0026gt; to support our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role, you will define comprehensive post-silicon validation plans, automate IC- and board-level testing, and design experiments to identify and root-cause unexpected behavior. You will analyze and report validation results against specifications, collaborate closely with key internal stakeholders, quantify performance margins, and ensure robust, production-ready designs.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026amp;nbsp;Strong academic and technical background in Electrical or Computer Engineering. At minimum, a Bachelor’s is required, and a Master’s is preferred.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026amp;nbsp;≥10 years experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026amp;nbsp;Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for internal meetings in advance, and to work with minimal guidance and supervision.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven track record solving problems independently, preferably as a tech lead\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Required experience\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience working on debug and bring-up of complicated SoC’s with high-speed interfaces such as PCIe/802.3 Ethernet\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong problem-solving skills, ability to solve problems independently\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Basic knowledge of key, high-speed design blocks such as PLL’s, CTLE, DFE, Tx EQ, PAM4 signaling\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong python scripting and coding ability: knowledge of object-oriented programming and basic dev ops using git for source control and collaboration\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency using high-speed lab equipment such as BERT, Oscilloscope, and VNA\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Experience:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026amp;nbsp;Experience in system testing, characterization, margin analysis and optimization of high-speed, multi-gigabit data links over long and short channels\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026amp;nbsp;Familiarity with PCIe or Ethernet especially Electrical Compliance sections\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026amp;nbsp;Hands-on experience with signal integrity, especially as it relates to PCIe/Ethernet testing and CEM/NVMe interfaces\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026amp;nbsp;Working knowledge of C or C++ for embedded FW\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026amp;nbsp;Familiarity with IEEE 802.3x Ethernet standards and both NRZ and PAM-4 signaling\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026amp;nbsp;Working knowledge of common serial data specifications such as I2C, SPI, etc\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026amp;nbsp;Knowledge of schematic capture and PCB layout tools from Cadence, Altium, etc.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026amp;nbsp;Knowledge of simulation tools such as MATLAB, Keysight ADS, or PLTS for data analysis and modeling of electrical channel and signal integrity issues\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;The base salary range is USD $205,000 - USD $260,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184210005,"name":"Advanced Hardware Engineering","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4733794005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4454545005,"location":{"name":"Taipei, Taiwan"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":null,"value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4733794005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2726","title":"Principal/ Sr Principal Digital Design Engineer ","company_name":"Astera Labs","first_published":"2026-09-14T18:06:23-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Principal Digital Design Engineer:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Role Overview\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Join Astera Labs as a\u0026amp;nbsp;Principal Digital Design Engineer\u0026amp;nbsp;to architect and implement next-generation digital designs for high-performance AI connectivity solutions. You\u0026#39;ll own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, physical design, and DFT teams to deliver production-quality silicon supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This role offers the opportunity to work on cutting-edge technology at the forefront of AI infrastructure, taking ownership of critical design challenges in a fast-paced, collaborative environment where your contributions directly impact products deployed by the world\u0026#39;s leading hyperscalers.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Key Responsibilities\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Design Ownership \u0026amp;amp; Execution\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Develop and implement complex digital blocks and subsystems by defining micro-architecture and driving RTL implementation with an exceptional power, performance and area trade-off using silicon technologies better than 7nm.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead efforts to achieve timing closure and implement Design-for-Test (DFT) features for optimal design performance\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive designs to production, ensuring accountability for quality, schedule, and overall design success\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;Verification \u0026amp;amp; Integration\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with verification teams to develop test plans, achieve coverage closure, and debug complex issues\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Own third-party IP integration and block-level verification through sign-off\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work closely with post-silicon teams to facilitate silicon bring-up and debug\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;Technical Leadership\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Mentor junior engineers to develop their technical skills and expertise\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Actively contribute to the development and improvement of silicon development processes\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive design methodology improvements and CAD automation initiatives\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Basic Qualifications\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering or equivalent\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;10+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Expertise in architecture definition, micro-architecture development, RTL coding, functional simulation, and synthesis\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of timing closure, gate-level simulation (GLS), and DFT implementation\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep expertise in at least one high-speed protocol: PCIe, CXL, Ethernet, DDR, or similar\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Production experience with advanced CMOS nodes (≤7nm)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency with Cadence and/or Synopsys digital design flows\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Preferred Qualifications\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Master\u0026#39;s degree in Electrical Engineering or related field\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Track record of delivering multiple high-performance designs to production in data-center environments\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on collaboration with embedded firmware teams; understanding of firmware development challenges\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with standard embedded processor subsystems (RISC-V, Arm, etc.)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven contributions to design methodology, CAD automation, or design infrastructure\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Salary range will depend on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184255005,"name":"Design Engineering CCE1","child_ids":[],"parent_id":null}],"offices":[{"id":4002874005,"name":"Taiwan","location":"Taipei, Taiwan","child_ids":[4061060005,4009035005],"parent_id":null}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4733773005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4454532005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":null,"value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4733773005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2725","title":"Principal/ Sr.Principal Digital Design Engineer ","company_name":"Astera Labs","first_published":"2026-09-14T18:05:39-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Principal Digital Design Engineer:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Role Overview\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Join Astera Labs as a\u0026amp;nbsp;Principal Digital Design Engineer\u0026amp;nbsp;to architect and implement next-generation digital designs for high-performance AI connectivity solutions. You\u0026#39;ll own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, physical design, and DFT teams to deliver production-quality silicon supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This role offers the opportunity to work on cutting-edge technology at the forefront of AI infrastructure, taking ownership of critical design challenges in a fast-paced, collaborative environment where your contributions directly impact products deployed by the world\u0026#39;s leading hyperscalers.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Key Responsibilities\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Design Ownership \u0026amp;amp; Execution\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Develop and implement complex digital blocks and subsystems by defining micro-architecture and driving RTL implementation with an exceptional power, performance and area trade-off using silicon technologies better than 7nm.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead efforts to achieve timing closure and implement Design-for-Test (DFT) features for optimal design performance\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive designs to production, ensuring accountability for quality, schedule, and overall design success\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;Verification \u0026amp;amp; Integration\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with verification teams to develop test plans, achieve coverage closure, and debug complex issues\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Own third-party IP integration and block-level verification through sign-off\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work closely with post-silicon teams to facilitate silicon bring-up and debug\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;Technical Leadership\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Mentor junior engineers to develop their technical skills and expertise\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Actively contribute to the development and improvement of silicon development processes\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive design methodology improvements and CAD automation initiatives\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Basic Qualifications\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering or equivalent\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;10+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Expertise in architecture definition, micro-architecture development, RTL coding, functional simulation, and synthesis\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of timing closure, gate-level simulation (GLS), and DFT implementation\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep expertise in at least one high-speed protocol: PCIe, CXL, Ethernet, DDR, or similar\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Production experience with advanced CMOS nodes (≤7nm)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency with Cadence and/or Synopsys digital design flows\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Preferred Qualifications\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Master\u0026#39;s degree in Electrical Engineering or related field\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Track record of delivering multiple high-performance designs to production in data-center environments\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on collaboration with embedded firmware teams; understanding of firmware development challenges\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with standard embedded processor subsystems (RISC-V, Arm, etc.)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven contributions to design methodology, CAD automation, or design infrastructure\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Salary range is $185,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184472005,"name":"Design Engineering CCE1 (US_SE_Design Engineering CCE1)","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4721053005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4447994005,"location":{"name":"Suzhou Qu, Gansu, China"},"metadata":[{"id":12122734005,"name":"Country","value":"China","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Suzhou","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Quality Assurance Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4721053005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":null,"title":"Principal Supplier Quality Engineer /China","company_name":"Astera Labs","first_published":"2026-08-07T05:44:13-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Job Description:\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;We are seeking an experienced leader to drive Supplier / Manufacturing Quality Engineering to anchor our global supplier quality efforts across both Astera Lab’s semiconductor, board-level products, optical products\u0026amp;nbsp;and\u0026amp;nbsp;rack-scale\u0026amp;nbsp;system\u0026amp;nbsp;products. In this role,\u0026amp;nbsp;you\u0026amp;nbsp;will drive leading supplier quality across key manufacturing partners including IC fabs, OSAT’s,\u0026amp;nbsp;optical product suppliers, rack-scale\u0026amp;nbsp;system product suppliers,\u0026amp;nbsp;and PCB/PCBA vendors.  You will\u0026amp;nbsp;also\u0026amp;nbsp;work closely with the customers to understand their quality needs and resolve issues related to product quality.\u0026amp;nbsp;Moreover, you will lead cross-functional teams to drive various quality initiatives to ensure that the products meet customer expectations and quality standards.\u0026amp;nbsp;\u0026amp;nbsp;A strong foundation in supplier quality engineering\u0026amp;nbsp;and customer quality engineering, uniquely paired with experience in advanced data analytics for predictive quality, risk assessments, and product quality analytics will be highly valuable to this role.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Responsibilities:\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Supplier Quality Management\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Drive supplier quality engineering activities at manufacturing partners, including failure analysis, root-cause identification, corrective actions, and verification of sustained closure.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Lead containment, escalation, and recovery actions for supplier-driven quality excursions.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Conduct regular focus line audits at key suppliers to verify process discipline, control plan adherence, corrective actions, and execution against quality expectations.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Nurture winning partnerships across all our strategic manufacturing suppliers: semiconductor wafer fabs, advanced packaging \u0026amp;amp; test (OSAT), boards \u0026amp;amp; assemblies (PCB / PCBA / SMT), substrates / interposers,\u0026amp;nbsp;rack-scale\u0026amp;nbsp;system products,\u0026amp;nbsp;optical products,\u0026amp;nbsp;probe cards, and passive components.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Develop robust supplier selection and onboarding processes in collaboration with Design, Procurement, Business \u0026amp;amp; Engineering Operations teams.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Define, build, and manage the systems to collect the data (KPI’s) needed to track supplier performance and drive continuous improvement.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;7\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Audit to assess the effectiveness of supplier process controls, manufacturing capabilities, and overall quality management system.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;8\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Coach suppliers by sharing your deep manufacturing experience and knowledge. \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;9\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;International travel\u0026amp;nbsp;as\u0026amp;nbsp;needed, potentially on short notice. There is no minimum amount but prepare to accommodate up to\u0026amp;nbsp;50%.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Customer Quality Management\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;10\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Work directly with regional customers to investigate and resolve supplier-related and other related quality issues, provide status updates, and coordinate cross-functional closure.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;11\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Handle customer quality issues using tools such as 8D, 5-why, and FMEA.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;12\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Manage customer messaging and provide timely status updates to customers.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;13\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Work on customer questionnaires on environmental compliance such as FMD, REACH and RoHS.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;14\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Handle RMA requests and other technical requests from the customers.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;15\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Build and maintain strong relationships with key customers.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Advanced Data Analytics\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Create data collection methods to enable\u0026amp;nbsp;product\u0026amp;nbsp;and supplier advanced data analytics needed for monolithic, chiplet, and board products.  Data sources will include manufacturing inline controls, production test (including data collection from advanced embedded agents), and failure analysis activities.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Leverage data into quality models \u0026amp;amp; methods to predict product quality issues and supply chain risks.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience with AI/ML tools is a \u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;plus\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;; ability to work with technical partners on model development is key.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Cross-functional Collaboration\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Interface with R\u0026amp;amp;D, NPI, product engineering, ops and other engineering teams to provide supplier\u0026amp;nbsp;and customer\u0026amp;nbsp;input into product design and DFX.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Support early supplier involvement and ensure quality requirements needed for manufacturability \u0026amp;amp; testability are achieved, and learnings are propagated appropriately to other products in production \u0026amp;amp; development.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Represent supplier quality\u0026amp;nbsp;and customer quality\u0026amp;nbsp;as needed in line failure reviews, excursion management, material reviews (MRB), and CAPA processes.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Partner with engineering and manufacturing teams to conduct quarterly engineering reviews, evaluate supplier changes (PCN), and assess supplier risks.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;With engineering engagement, lead quality audits, and corrective action activities using tools such as 8D, 5-why, and FMEA.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Education \u0026amp;amp; Experience\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Bachelor’s or\u0026amp;nbsp;Master’s degree in Engineering\u0026amp;nbsp;or equivalent experience.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;8+ years of career progression in supplier quality engineering in the semiconductor, rack-scale\u0026amp;nbsp;system, optics,\u0026amp;nbsp;and/or board-level electronics industry.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;3+\u0026amp;nbsp;years\u0026amp;nbsp;direct experience working embedded within a\u0026amp;nbsp;high volume\u0026amp;nbsp;advanced manufacturing operation in an engineering role.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience with supplier development in Asia with global manufacturing supply chains.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience interfacing with customers to handle customer quality issues, customer audits, RMA requests and other technical requests.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience serving as a direct interface with the customer with strong expertise to analyze and resolve product quality issues effectively and efficiently\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;7\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Six Sigma or ASQ certification a plus\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Technical Skills\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;8\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Strong knowledge of IC fabrication, packaging (including chiplet),\u0026amp;nbsp;test processes,\u0026amp;nbsp;board assembly (SMT)\u0026amp;nbsp;and testing,\u0026amp;nbsp;rack-scale system product manufacturing and testing,\u0026amp;nbsp;and\u0026amp;nbsp;optical product manufacturing and testing.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;8\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Familiarity with reliability qualification methodologies in the application of IPC, Telcordia, JEDEC requirements.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;8\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Proficiency with quality engineering tools (FMEA, APQP, PPAP, SPC, OE, etc.).\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;8\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience using analytics tools (e.g., JMP, SQL, Excel) to support quality insights. Exposure to AI/ML frameworks is a\u0026amp;nbsp;plus, but\u0026amp;nbsp;not required.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;8\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Strong project management and problem-solving skills, and capable of working independently as well as part of a team\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;8\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Excellent communication and soft skills are essential.\u0026amp;nbsp;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;8\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;7\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Fluent\u0026amp;nbsp;in English and Mandarin\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184389005,"name":"Quality APAC","child_ids":[],"parent_id":null}],"offices":[{"id":4002875005,"name":"China","location":"China","child_ids":[4002876005,4061056005,4002878005,4009038005,4002877005],"parent_id":null}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4738838005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4456918005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Design Verification","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4738838005,"updated_at":"2026-09-30T11:08:01-04:00","requisition_id":"2026-448","title":"Principal Verification Engineer","company_name":"Astera Labs","first_published":"2026-09-29T09:01:30-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p8i6j01 paragraph\u0026quot;\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is seeking a \u0026lt;strong\u0026gt;Principal Design Verification Engineer\u0026lt;/strong\u0026gt; with strong problem-solving abilities and a passion for developing robust verification methodologies for complex ASICs. The ideal candidate will have a solid background in SystemVerilog and experience with C/C++, Python, or similar scripting languages. This role involves full lifecycle verification—from planning and test development to debugging and coverage closure—contributing to the success of cutting-edge SoC designs.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Lead the functional verification of advanced ASICs, including test planning, development, execution, and coverage analysis.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate closely with software and system validation teams to create and execute test plans on emulation platforms.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Apply both directed and constrained-random verification techniques using SystemVerilog/UVM and other relevant tools.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Debug test failures, analyze coverage results, and close functional coverage gaps to ensure comprehensive verification.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work with RTL designers to troubleshoot and resolve design issues.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive verification strategy and methodology for SoCs in server and networking applications.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s degree in Electrical Engineering (Master’s preferred).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;8+ years of experience in SoC verification, particularly for server and networking applications.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Expertise in SystemVerilog/UVM and hands-on experience across the full verification lifecycle.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency with industry-standard simulators, version control, and regression systems.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong debugging and coverage analysis skills.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience developing and executing test sequences, generating stimuli, and identifying verification holes.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with verification of switching architectures, including packet processing and forwarding engines.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent communication skills and ability to work independently with minimal supervision.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience with third-party Verification IP for protocols such as PCIe, Ethernet, and InfiniBand.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Background in Network-on-Chip (NoC) architectures for smart NICs and AI accelerators.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of Ethernet/PCIe switching and central buffer architectures.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with emulation platforms and hardware-software co-verification\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Salary range is $185,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p8i6j01 paragraph\u0026quot;\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184260005,"name":"Design Verification CCE2","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4730490005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4452758005,"location":{"name":"Aachen, North Rhine-Westphalia, Germany"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":null,"value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4730490005,"updated_at":"2026-10-08T00:08:12-04:00","requisition_id":"2715","title":"Process Engineer Cleaning \u0026 Coating /Day Shift","company_name":"Astera Labs","first_published":"2026-09-10T12:28:29-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot; data-olk-copy-source=\u0026quot;MessageBody\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Job Title:\u0026lt;/strong\u0026gt; Process Engineer Cleaning \u0026amp;amp; Coating\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Location\u0026lt;/strong\u0026gt;: Aachen, Germany\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Job Type:\u0026lt;/strong\u0026gt; Full-time, dayshift\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;About the Role:\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;We are seeking for a motivated Process Engineer to join our high-tech assembly process and test team. In this role, you will develop, optimize, and manage surface treatment process steps in the back-end semiconductor manufacturing process for a high-end optical component. You will fine-tune methods like chemical/ultrasonic cleaning and thin film deposition. You will work in a fast-paced high tech environment, supporting high-volume production while ensuring maximum yield and quality. You will be reporting to the manager engineering.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;Key Responsibilities:\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;Process Monitoring \u0026amp;amp; Maintenance: Monitor daily coating and cleaning process parameters using Statistical Process Control (SPC) to ensure stability and quality.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;Troubleshooting: Identify and resolve process shifts or equipment issues on the production floor, working closely with maintenance and equipment engineering teams.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;Yield Optimization: Perform root cause analysis on defects and drive continuous improvement projects to reduce waste and improve assembly line efficiency.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;New Product Introduction (NPI): Assist in defining process parameters and qualifying new coatings and cleaning processes or advanced surface treat technologies for new product launches.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;Documentation: Develop and maintain Standard Operating Procedures (SOPs) and technical reports for all cleaning and coating operations.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;Team Collaboration: Train and coach operations staff on dicing fundamentals and safe equipment handling.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;Qualifications:\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;Education: Bachelor’s or Master\u0026#39;s degree in Chemistry, Materials Science, Physics, or a related technical field.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;Experience: 2–4 years of experience in a high-tech manufacturing environment. Relevant internships or co-op experience in semiconductor assembly is highly valued.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;Technical Skills:\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;Foundational knowledge of semiconductor (or similar) fabrication and assembly processes.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;Experience with coating or cleaning equipment is a pre.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;Familiarity with data analysis tools such as Minitab.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;Basic understanding of Design of Experiments (DOE) and Lean Six Sigma methodologies.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;Soft Skills:\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;Strong analytical problem-solving abilities and attention to detail.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;Hand-on mentality\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;Excellent communication skills for collaborating with cross-functional teams.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;Ability to thrive in a fast-paced, high-pressure manufacturing environment.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;What We Offer:\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;Opportunity to work with cutting-edge semiconductor assembly technology.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;Structured career progression and mentorship from seasoned technical staff.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;Competitive compensation package and comprehensive benefits.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184399005,"name":"Signal Connectivity Group","child_ids":[],"parent_id":null}],"offices":[{"id":4056756005,"name":"Aachen","location":"Germany","child_ids":[],"parent_id":4056755005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4725542005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4450199005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":null,"value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4725542005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2706","title":"Product Application Engineer PCIe/CXL","company_name":"Astera Labs","first_published":"2026-08-18T20:04:49-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;h2\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/h2\u0026gt;\n\u0026lt;p\u0026gt;As an Astera Labs \u0026lt;strong\u0026gt;Principal Product Application Engineer\u0026lt;/strong\u0026gt;, you will need to provide technical guidance to customers to overcome design challenges, generate collateral for existing and new products, and drive innovation by providing insightful feedback to other internal teams to continuously improve products and processes.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is seeking a Principal Product Applications Asia Region Lead with 8+ years of experience supporting the development and design-in of semiconductor products for PCIe/CXL. Regional leads focus on development, debugging, and design-in activities related to customers in a designed geography, and help coordinate with local development teams in Astera Labs Headquarters.\u0026amp;nbsp;\u0026lt;strong\u0026gt;This role will be supporting our China region. Role is required to work approximately from 12:00 PM to 9:00 PM PST to enable real-time collaboration with stakeholders in the Asia Pacific time zone.\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, Master’s is preferred.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Minimum of 3 years’ experience in designing in complex SoC/silicon products with a high speed (preferably PCIe) interface.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!\u0026lt;strong\u0026gt;\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Full professional proficiency in Mandarin (written and spoken) required to communicate directly with Asia region customer contacts\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Experience\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong working knowledge of PCIe LTSSM at a physical layer level, associated standards, and debug. Most recent experience with PCIe 5.0 at a minimum, some experience with 6.0/CXL preferred.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Silicon/System bring-up and debug experience in customer systems.\u0026amp;nbsp;\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Technical ownership of issue resolution: Driving and directing internal teams toward issue resolution. Driving communication with customers, FAEs, and sales team members\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Firsthand experience with lab equipment such as protocol analyzers/exercisers, high-speed oscilloscopes, or BERTs.\u0026amp;nbsp;\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Comfort working with software/firmware associated with semiconductor products, such as: Firmware development with C-language, scripting with Python or other equivalent programming languages.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred experience\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Triaging complex customer reported issues which require taking into account multiple layers of conditions. For instance, silicon, firmware, hardware board design, and system environment.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with common data center BMC implementation, and BIOS configuration\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Development/support for PCIe or Ethernet Switch or Retimer products.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;PCIe compliance testing methodology and troubleshooting.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Understanding of Data Center systems like Servers, JBOGs/JBODs, Networking switches/routers/interconnects etc.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Mandarin language proficiency preferred. Candidate must be able to speak Mandarin to effectively communicate with our China region customers and team members.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Candidate will need to be open work approximately from 12:00 PM to 9:00 PM PST to enable real-time collaboration with stakeholders in the Asia Pacific time zone\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Base salary range is $185,000 to $240,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184754005,"name":"Signal Connectivity Group (US_SCG)","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4597484005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4388907005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":"Fabrics \u0026 Controllers Product Applications","value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Product Applications Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Early Career","value_type":"single_select"}],"id":4597484005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"1885","title":"Product Applications Engineer (NCG 2026)","company_name":"Astera Labs","first_published":"2026-06-16T14:01:21-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Job Description:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As an Astera Labs \u0026lt;strong\u0026gt;Firmware Product Application Engineer\u0026lt;/strong\u0026gt;, you will sit at the intersection of firmware engineering and customer-facing technical engagement. You will help enable Leo CXL Smart Memory Controllers at hyperscale customers and OEM partners — assisting with firmware bring-up, validation, and customer issue resolution from early silicon through production ramp.\u0026lt;br\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;You will help to provide technical guidance to customers to overcome design challenges, generate collateral for existing and new products, and drive innovation by providing insightful feedback to other internal teams to continuously improve products and processes.\u0026amp;nbsp;There are opportunities to support key customers directly, and also to dive deep in the lab to address the challenges associated with leading edge semiconductor products.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This position is required onsite in San Jose, CA.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Assist with customer engagements for Leo CXL Smart Memory Controllers, including bring-up support, feature enablement, and issue triage on customer platforms\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop, validate, and debug firmware using\u0026amp;nbsp;C\u0026amp;nbsp;and\u0026amp;nbsp;Python\u0026amp;nbsp;across Leo\u0026#39;s PCIe/CXL and DDR memory subsystems\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Assist with end-to-end firmware validation of\u0026amp;nbsp;DDR4/DDR5 DRAM\u0026amp;nbsp;interfaces, including initialization, training, RAS (Reliability, Availability, Serviceability) features, and performance tuning\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with cross-functional teams (FW engineering, HW, systems, product management) to help deliver firmware releases and customer collateral on schedule\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop and maintain Python-based test scripts, automation frameworks, and diagnostic tools to support validation and customer debug workflows\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Contribute to technical documentation including application notes, release notes, design guides, and customer-facing collateral\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, Computer Science, or a related technical field;\u0026amp;nbsp;Master\u0026#39;s\u0026amp;nbsp;degree preferred\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Professional attitude with the ability to prioritize a dynamic list of tasks and work with minimal guidance\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Entrepreneurial, open-minded behavior and can-do attitude — think and act fast with the customer in mind!\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Authorized to work in the US and available to start immediately\u0026lt;strong\u0026gt;\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Experience\u0026lt;/strong\u0026gt; \u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Proficiency in C\u0026amp;nbsp;for embedded firmware development in RTOS environments\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency in Python\u0026amp;nbsp;for scripting, test automation, and diagnostic tooling\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge with firmware bring-up, debug, and validation of memory or I/O subsystems on server platforms\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong debugging skills with the ability to triage and root-cause issues in complex embedded systems\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with SoC interfaces including DDR controllers, PCIe controllers, and on-chip memory subsystems\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of developer workflows: SCM (preferably Git), code reviews, CI/CD pipelines\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Technical writing skills to generate clear, precise documentation including application notes and similar guides for internal and customer-facing audiences.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Working knowledge of\u0026amp;nbsp;CXL (Compute Express\u0026amp;nbsp;Link)\u0026amp;nbsp;—\u0026amp;nbsp;CXL 1.1/2.0/3.0 — including memory expansion, pooling, and sharing concepts\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with\u0026amp;nbsp;PCIe\u0026amp;nbsp;endpoint firmware at the PHY, Link, and Transaction layers; familiarity with PCIe enumeration, MSI/MSI-X, SR-IOV, and error handling\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of\u0026amp;nbsp;high-speed memory interfaces\u0026amp;nbsp;— DDR4 and/or DDR5 DRAM — including initialization sequences, training algorithms, timing margins, and ECC/RAS features\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience with PCIe/CXL protocol analyzers, BERT, and other lab debug equipment\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with BIOS/BMC/OS interactions with PCIe/CXL devices and MMIO/RAS concepts\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with server memory performance tuning — latency and bandwidth optimization\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Prior customer-facing or field applications experience in a semiconductor or systems company is a strong plus\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;The base pay for this range is between $140,000 - $150,000 dependent on education level.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184283005,"name":"Fabrics \u0026 Controllers Product Applications","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4695147005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4435718005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Quality Assurance Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Early Career","value_type":"single_select"}],"id":4695147005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2546","title":"Product Quality Engineer (NCG)","company_name":"Astera Labs","first_published":"2026-05-13T16:43:51-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;div class=\u0026quot;my-2\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is seeking a Quality Engineer to join our Product Quality Engineering team in San Jose, CA. This is an exciting opportunity for an early-career engineer to dive into the heart of AI infrastructure connectivity, working hands-on with cutting-edge semiconductor devices that power the world\u0026#39;s most advanced data centers.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;div class=\u0026quot;my-2\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;In this role, you will be instrumental in driving root-cause analysis of failures across circuit, package, firmware, and protocol layers — directly impacting the reliability and quality of our PCIe and Ethernet connectivity solutions. You\u0026#39;ll work with state-of-the-art lab instrumentation, build infrastructure to accelerate failure analysis, and collaborate across engineering disciplines to ensure Astera Labs continues to deliver best-in-class silicon to hyperscale customers. If you\u0026#39;re passionate about high-speed SERDES, signal integrity, and solving complex hardware problems at the intersection of AI and connectivity, this is the role for you.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;div class=\u0026quot;my-2\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;div class=\u0026quot;my-2\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Failure Analysis \u0026amp;amp; Root-Cause Infrastructure\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Enable and develop infrastructure such as databases to optimize and reduce time to root-cause failures in circuit, package, firmware, or protocol-level iterations\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Participate in the new product development process to enable improvements and capabilities for failure analysis\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Document product quality engineering processes and methodologies to ensure repeatability and scalability\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Lab Measurement \u0026amp;amp; Debug\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Perform measurements on high-speed SERDES, PCIe, and Ethernet devices to characterize and debug quality issues\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Set up and use advanced lab instrumentation including BERT, high-bandwidth oscilloscopes, protocol analyzers, VNAs, TDR, and spectrum analyzers to support debug and root-cause activities\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional Collaboration\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Collaborate with design, validation, hardware, and system engineering teams to resolve quality issues and drive continuous improvement\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Support cross-functional efforts to improve product reliability and manufacturing quality\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;div class=\u0026quot;my-2\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;div class=\u0026quot;my-2\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, Computer Engineering, or a related field\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Understanding of high-speed serial interfaces (PCIe, Ethernet, SERDES)\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Familiarity with lab instrumentation such as oscilloscopes, BERT, TDR, or spectrum analyzers\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Strong analytical and problem-solving skills\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Excellent documentation and communication skills\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;div class=\u0026quot;my-2\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;div class=\u0026quot;my-2\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Internship or project experience in semiconductor quality, product engineering, or hardware validation\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Exposure to signal integrity concepts and high-speed measurement techniques\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience with database tools or scripting languages (Python, SQL) for data analysis and infrastructure development\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Familiarity with failure analysis methodologies in a semiconductor environment\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Knowledge of PCIe or Ethernet protocol specifications\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;div class=\u0026quot;my-2\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;The salary range for this position is $120,000 to $140,000 depending on experience and education level. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4011733005,"name":"Quality","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4677688005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4426994005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":"Compute Connectivity Engineering 2","value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Digital Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4677688005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2412","title":"Product Technical Chip Lead, Senior Director ","company_name":"Astera Labs","first_published":"2026-04-09T13:18:21-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Astera Labs is seeking an Senior Director OR Associate Vice President, Product Technical Lead (Chip Lead) to drive the end-to-end success of our next-generation UALink switching products in San Jose. This is an executive technical leadership role where you will connect architecture, design, validation, firmware, systems, and operations to ensure clarity, alignment, and predictable execution across the full product lifecycle.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;As the technical integrator for the product line, you will lead through influence and cross-functional authority, working on\u0026amp;nbsp;cutting-edge\u0026amp;nbsp;UALink, UCIe, and PCIe Gen6/Gen7 technologies that power the largest AI clusters in the world.\u0026amp;nbsp;You\u0026#39;ll\u0026amp;nbsp;be the central technical voice ensuring our switching products scale with Astera\u0026#39;s hyper-growth while delivering world-class silicon to\u0026amp;nbsp;customers\u0026amp;nbsp;enabling rack-scale AI and hyperscale data centers.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;Location - San Jose, CA OR Israel\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; 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data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Own the full technical lifecycle of the product line—architecture assumptions, design integration, validation strategy, readiness, and customer enablement\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; 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data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Collaborate with DFT teams on test architecture, scan insertion, BIST, and manufacturing test strategies\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; 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data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Provide structured, data-driven decision-making and\u0026amp;nbsp;maintain\u0026amp;nbsp;a crisp operational cadence across the product line\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Transform conflicts to foster a culture of ownership over ego, mentoring and elevating teams while strengthening technical judgment, accountability, and cross-functional collaboration\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Model steady, calm leadership, particularly in high-stakes or ambiguous situations\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Shape engineering culture and talent strategy to support Astera\u0026#39;s rapid growth trajectory\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Basic Qualifications\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, Computer Engineering, or related field\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;15+ years of experience across architecture, silicon design, validation, systems, or related domains\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Proven\u0026amp;nbsp;track record\u0026amp;nbsp;of developing large-scale chips (300mm²+) through successful\u0026amp;nbsp;tapeout\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Hands-on experience with 2.5D and 3D advanced packaging technologies and chiplet-based architectures\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Strong understanding of RTL design, design verification, DFT, and physical design flows\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience with high-speed serial interfaces such as PCIe, Ethernet, or switching architectures\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;7\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Demonstrated executive leadership of cross-functional technical programs with end-to-end product cycle ownership\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;8\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Strong communication\u0026amp;nbsp;and executive presence with the ability to influence at all levels of the organization\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Preferred Qualifications\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Master\u0026#39;s degree in Electrical Engineering or Computer Engineering\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; 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data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Systems Thinking: See the big picture while managing details\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Emotional Intelligence: Calm under pressure, empathetic, and influential\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Adaptability: Thrive in ambiguity and fast-changing environments\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Execution Discipline: Deliver predictable results without sacrificing innovation\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;Base salary range is $260,000 to $295,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184233005,"name":"Compute Connectivity Engineering 2","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4670952005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_optional","internal_job_id":4423706005,"location":{"name":"Taipei, Taiwan"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Sales","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Internship","value_type":"single_select"}],"id":4670952005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2350","title":"Sales Intern","company_name":"Astera Labs","first_published":"2026-03-09T22:26:54-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;div\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Astera Labs is seeking highly motivated Interns to join the Sales team in the TW team.\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;If you are:\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;A Junior going into Senior year or Senior graduating by the end of this year\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Have strong academics and technical background in Electrical Engineering\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Someone with a professional attitude, ability to prioritize a dynamic list of multiple tasks and work with minimal guidance and supervision\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong in analytical skills, self-motivated and a challenge taker\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;What we are looking for:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Develop regional sales analysis and planning materials by identifying market segments, opportunity sizing, and internal execution strategies\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support sales initiatives by partnering closely with FAEs and internal stakeholders to prepare product information, roadmap materials, technology training content, and internal documentation\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Consolidate and analyze input from internal teams to support product planning, roadmap alignment, and internal issue tracking\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Coordinate cross-functional information flow among sales, operations, and supply-related teams to support quarterly revenue planning and mid-term demand projections\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Assist in market and ecosystem research across CPU, GPU, FPGA, Networking, Memory, and BMC segments to identify co-development and strategic opportunity areas\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;If the above position excites you, we would love to hear from you.\u0026lt;/p\u0026gt;\n\u0026lt;/div\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4000197005,"name":"Sales","child_ids":[],"parent_id":null}],"offices":[{"id":4009035005,"name":"Taipei","location":"Taiwan","child_ids":[],"parent_id":4002874005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4649872005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4414108005,"location":{"name":"Israel"},"metadata":[{"id":12122734005,"name":"Country","value":"Israel","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Tel Aviv","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":"Silicon Engineering CCE2","value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Digital Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4649872005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2204","title":"Senior ASIC Design Engineer","company_name":"Astera Labs","first_published":"2026-01-15T19:43:19-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is establishing a strategic R\u0026amp;amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical \u0026#39;data bottlenecks\u0026#39; enabling the future of AI at scale. As we expand our presence in Israel, we\u0026#39;re seeking a talented\u0026lt;strong\u0026gt; \u0026lt;span class=\u0026quot;TextRun Underlined SCXW209305118 BCX0\u0026quot; lang=\u0026quot;EN-US\u0026quot; data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;NormalTextRun SCXW209305118 BCX0\u0026quot;\u0026gt;Senior ASIC Design Engineer\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026amp;nbsp;\u0026lt;/strong\u0026gt;to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful product ownership in a new site, designing the digital blocks that sit at the heart of our most ambitious connectivity projects.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As a\u0026lt;strong\u0026gt; \u0026lt;span class=\u0026quot;TextRun Underlined SCXW209305118 BCX0\u0026quot; lang=\u0026quot;EN-US\u0026quot; data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;NormalTextRun SCXW209305118 BCX0\u0026quot;\u0026gt;Senior ASIC Design Engineer\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;, you won\u0026#39;t just build chips—you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world\u0026#39;s largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving challenging problems in deep-submicron processes and want to contribute to the digital design foundation for AI infrastructure connectivity, this is your opportunity.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Design Ownership \u0026amp;amp; Implementation\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Serve as the point of contact for your logic blocks, interacting with Architecture, Verification, and Backend teams\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Quality Assurance \u0026amp;amp; Design Optimization\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Utilize industry-leading EDA tools (Lint, CDC, Synthesis, Timing, Power) and in-house quality assurance tools to ensure designs are robust, scalable, and power-efficient\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Apply design techniques to meet PPA (Power, Performance, Area) targets\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Contribute to design quality through verification and validation activities\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Methodology Innovation \u0026amp;amp; Collaboration\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Participate in design methodology improvements and tool automation initiatives\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Leverage AI assistance tools and contribute to in-house automation development to make engineering workflows faster and smarter\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Collaborate effectively across teams to ensure seamless integration\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering or related technical field\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;3+ years of experience in logic design at semiconductor companies\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Knowledge and experience in Verilog and/or SystemVerilog\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Excellent communication skills with ability to work effectively across teams\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Understanding of digital design principles and RTL coding best practices\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Master\u0026#39;s degree in Electrical Engineering or related field\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Knowledge of DDR and PCIe protocols and implementation\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Understanding of power management techniques for low-power design\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Familiarity with Clock Domain Crossing, simulation, debugging, synthesis, and timing analysis\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Proficiency in scripting languages such as Python or Perl\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience with high-speed serial interface designs or connectivity protocols\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184339005,"name":"Silicon Engineering CCE2","child_ids":[],"parent_id":null}],"offices":[{"id":4008937005,"name":"Israel","location":"Israel","child_ids":[4052111005,4061058005,4056876005],"parent_id":null}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4728526005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4451767005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Test Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4728526005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2026-196","title":"Senior ATE Test Engineer","company_name":"Astera Labs","first_published":"2026-08-31T16:11:56-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;We are looking for \u0026lt;strong\u0026gt;Senior ATE Test Engineers\u0026amp;nbsp;\u0026lt;/strong\u0026gt;with proven experience in developing and supporting complex mixed-signal silicon SoC products to lead ATE Test solutions. The ideal candidate will develop and oversee SoC test strategy, interact with manufacturing partners, define, and implement ATE programs and own the product from design, initial samples all the way through high volume production ramp. The candidate should have working knowledge of communication/interface protocols such as PCI-Express (Gen-4/5/6), Ethernet, Infiniband, DDR, NVMe, USB, etc. This is an opportunity to contribute hands-on technical expertise within Astera Labs’ hyper-growth connectivity business and help deliver purpose-built solutions that scale with the demands of rack-scale AI systems.\u0026lt;/p\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;574\u0026quot;\u0026gt;\u0026lt;strong data-renderer-mark=\u0026quot;true\u0026quot;\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;598\u0026quot;\u0026gt;Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, and a Master’s is preferred.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;742\u0026quot;\u0026gt;≥2 year experience releasing complex SoC/silicon products to high volume manufacturing.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;833\u0026quot;\u0026gt;Working knowledge of high-speed protocols like PCIe, Ethernet, Infiniband, DDR, NVMe, USB, etc.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;932\u0026quot;\u0026gt;Professional attitude with ability to execute on multiple tasks with minimal supervision.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;1025\u0026quot;\u0026gt;Strong team player with good communication skills to work alongside a team of high caliber engineers.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;1130\u0026quot;\u0026gt;Entrepreneurial, open-mind behavior and can-do attitude.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong data-renderer-mark=\u0026quot;true\u0026quot;\u0026gt;Required Experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;1213\u0026quot;\u0026gt;Hands-on experience with high-speed mixed signal SoC test program/hardware development on multiple high-speed test platforms.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;1342\u0026quot;\u0026gt;Collaboration with design team to define test strategy, create and own test plan.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;1427\u0026quot;\u0026gt;Tester platform selection, design, and development of ATE hardware for wafer sort and final test.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;1528\u0026quot;\u0026gt;Familiar with high-speed load board design techniques.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;1586\u0026quot;\u0026gt;Proven track record of implementing ATE patterns to optimize tester resources and minimize ATE test time while maintaining product quality.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;1729\u0026quot;\u0026gt;Strong knowledge and development of DFT techniques implemented in silicon that provide maximum defect and parametric device coverage – SCAN, MEMBIST, SerDes and other functional tests.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;1917\u0026quot;\u0026gt;Skilled in control interfaces – I2C, I3C, SPI, MDIO, JTAG etc.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;1983\u0026quot;\u0026gt;Expertise in production test of high speed SerDes operating at 16Gbps and higher.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;2068\u0026quot;\u0026gt;Skilled in ATE programming, silicon/ATE bring-up, bench-ATE correlation and debug.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;2154\u0026quot;\u0026gt;Experience with lab equipment including protocol analyzers and oscilloscopes.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;2235\u0026quot;\u0026gt;Experience with using Advantest 93k ATE platform.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;2290\u0026quot;\u0026gt;Proficiency in, at least, one modern programming language such as C/C++, Python.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong data-renderer-mark=\u0026quot;true\u0026quot;\u0026gt;Preferred Experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;2398\u0026quot;\u0026gt;Fluent in data processing using high level programming languages.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;2398\u0026quot;\u0026gt;Experience in running External loopback at wafer sort.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;2467\u0026quot;\u0026gt;Familiarity with modern databases\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Salary range is $135,500 to $170,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184355005,"name":"Test Engineering","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4738049005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4456507005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Design Verification","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4738049005,"updated_at":"2026-10-08T07:14:24-04:00","requisition_id":"2026-453","title":"Senior Design Verification Engineer","company_name":"Astera Labs","first_published":"2026-09-28T17:15:04-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot; data-ccp-parastyle-defn=\u0026quot;{\u0026amp;quot;ObjectId\u0026amp;quot;:\u0026amp;quot;276295ed-5df2-5456-988c-5fdbab071054|1\u0026amp;quot;,\u0026amp;quot;ClassId\u0026amp;quot;:1073872969,\u0026amp;quot;Properties\u0026amp;quot;:[201342446,\u0026amp;quot;1\u0026amp;quot;,201342447,\u0026amp;quot;5\u0026amp;quot;,201342448,\u0026amp;quot;1\u0026amp;quot;,201342449,\u0026amp;quot;1\u0026amp;quot;,469777841,\u0026amp;quot;Aptos\u0026amp;quot;,469777842,\u0026amp;quot;Arial\u0026amp;quot;,469777843,\u0026amp;quot;Aptos\u0026amp;quot;,469777844,\u0026amp;quot;Aptos\u0026amp;quot;,201341986,\u0026amp;quot;1\u0026amp;quot;,469769226,\u0026amp;quot;Aptos,Arial\u0026amp;quot;,268442635,\u0026amp;quot;24\u0026amp;quot;,335559739,\u0026amp;quot;180\u0026amp;quot;,335559738,\u0026amp;quot;180\u0026amp;quot;,469775450,\u0026amp;quot;First Paragraph\u0026amp;quot;,201340122,\u0026amp;quot;2\u0026amp;quot;,134234082,\u0026amp;quot;true\u0026amp;quot;,134233614,\u0026amp;quot;true\u0026amp;quot;,469778129,\u0026amp;quot;FirstParagraph\u0026amp;quot;,335572020,\u0026amp;quot;1\u0026amp;quot;,469775498,\u0026amp;quot;Body Text\u0026amp;quot;,469778324,\u0026amp;quot;Body Text\u0026amp;quot;]}\u0026quot;\u0026gt;Role Overview\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:180,\u0026amp;quot;335559739\u0026amp;quot;:180}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Body Text\u0026quot;\u0026gt;As a Senior Design Verification Engineer, you will help define and deliver robust verification for next-generation connectivity silicon that enables rack-scale AI infrastructure. You will partner closely with RTL, architecture, firmware, and post-silicon teams to build verification strategies that prove complex switching behavior across high-bandwidth protocols and demanding system environments.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:180,\u0026amp;quot;335559739\u0026amp;quot;:180}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Body Text\u0026quot;\u0026gt;This role offers the opportunity to own meaningful verification challenges within CCE2, from planning and testbench architecture through coverage closure and silicon learning. You will contribute to Astera Labs’ hyper-growth mission by helping deliver \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Body Text\u0026quot;\u0026gt;highly reliable\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Body Text\u0026quot;\u0026gt; PCIe and \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Body Text\u0026quot;\u0026gt;UALink\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Body Text\u0026quot;\u0026gt; connectivity products that keep AI accelerators, memory, and compute resources \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Body Text\u0026quot;\u0026gt;operating\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Body Text\u0026quot;\u0026gt; at scale.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:180,\u0026amp;quot;335559739\u0026amp;quot;:180}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Body Text\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:180,\u0026amp;quot;335559739\u0026amp;quot;:180}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;0\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot; data-ccp-parastyle-defn=\u0026quot;{\u0026amp;quot;ObjectId\u0026amp;quot;:\u0026amp;quot;eafb41c0-47a4-52dc-ac6b-3b5a7536b560|1\u0026amp;quot;,\u0026amp;quot;ClassId\u0026amp;quot;:1073872969,\u0026amp;quot;Properties\u0026amp;quot;:[201342446,\u0026amp;quot;1\u0026amp;quot;,201342447,\u0026amp;quot;5\u0026amp;quot;,201342448,\u0026amp;quot;1\u0026amp;quot;,201342449,\u0026amp;quot;1\u0026amp;quot;,469777841,\u0026amp;quot;Aptos\u0026amp;quot;,469777842,\u0026amp;quot;Arial\u0026amp;quot;,469777843,\u0026amp;quot;Aptos\u0026amp;quot;,469777844,\u0026amp;quot;Aptos\u0026amp;quot;,201341986,\u0026amp;quot;1\u0026amp;quot;,469769226,\u0026amp;quot;Aptos,Arial\u0026amp;quot;,268442635,\u0026amp;quot;24\u0026amp;quot;,335559739,\u0026amp;quot;36\u0026amp;quot;,335559738,\u0026amp;quot;36\u0026amp;quot;,469775450,\u0026amp;quot;Compact\u0026amp;quot;,201340122,\u0026amp;quot;2\u0026amp;quot;,134234082,\u0026amp;quot;true\u0026amp;quot;,134233614,\u0026amp;quot;true\u0026amp;quot;,469778129,\u0026amp;quot;Compact\u0026amp;quot;,335572020,\u0026amp;quot;1\u0026amp;quot;,469778324,\u0026amp;quot;Body Text\u0026amp;quot;]}\u0026quot;\u0026gt;Verification Strategy and Planning\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;0\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Develop block- and subsystem-level verification plans from specifications, architecture, and design requirements.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Define test scenarios, coverage models, checkers, assertions, and scoreboards for complex switching functionality.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Review designs and verification plans with architecture and RTL teams to \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;identify\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; corner cases early.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Environment Development and Execution\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;0\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Build and enhance reusable UVM-based \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;SystemVerilog\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; testbenches, agents, sequences, monitors, and reference models.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Create directed, constrained-random, and power-on-reset scenarios spanning PCIe Gen 6/Gen 7, \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;UALink\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;, and UCI behavior.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Debug simulation failures using waveform analysis, logs, assertions, and cross-functional collaboration.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Coverage, Quality, and Silicon Readiness\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;0\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Drive functional and code coverage analysis, \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;identify\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; verification gaps, and close coverage to agreed milestones.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Develop regression strategies and automation to improve test quality, turnaround time, and failure triage.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Partner with design and post-silicon teams on \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;issue\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; isolation, root-cause analysis, and silicon bring-up readiness.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot;\u0026gt;Basic Qualifications\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:180,\u0026amp;quot;335559739\u0026amp;quot;:180}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Bachelor’s degree in Electrical Engineering\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;, Computer Engineering, or \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;a related\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; technical field.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;2–5 years of experience in design verification for complex ASICs or SoCs.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Hands-on experience with \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;SystemVerilog\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; and UVM-based verification environments.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Experience developing verification plans, testbenches, assertions, scoreboards, and functional coverage models.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;7\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Familiarity with simulation, waveform-debug, regression, and coverage tools.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;8\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Strong debugging, communication, and collaboration skills in a fast-paced product development environment.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot;\u0026gt;Preferred Qualifications\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:180,\u0026amp;quot;335559739\u0026amp;quot;:180}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;9\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Master’s degree in Electrical Engineering\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;, Computer Engineering, or \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;a related\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; field.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;10\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Experience verifying PCIe, \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;UALink\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;, UCI, or other high-speed connectivity and switching protocols.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;11\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Knowledge of protocol checkers, formal verification, emulation, or hardware acceleration methodologies.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;12\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Experience with Python, Perl, or \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Tcl\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; for \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;verification\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; automation and regression infrastructure.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; 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This role may be eligible for discretionary \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot;\u0026gt;bonus\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot;\u0026gt;, \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot;\u0026gt;incentives\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot;\u0026gt; and benefits.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184260005,"name":"Design Verification CCE2","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4731808005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4453485005,"location":{"name":"Toronto, Ontario, Canada"},"metadata":[{"id":12122734005,"name":"Country","value":"Canada","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Toronto","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Design Verification","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4731808005,"updated_at":"2026-09-30T11:06:36-04:00","requisition_id":"2026-011","title":"Senior Design Verification Engineer","company_name":"Astera Labs","first_published":"2026-09-11T13:24:40-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 2\u0026quot;\u0026gt;Role Overview\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335559738\u0026amp;quot;:160,\u0026amp;quot;335559739\u0026amp;quot;:80}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot; data-ccp-parastyle-defn=\u0026quot;{\u0026amp;quot;ObjectId\u0026amp;quot;:\u0026amp;quot;276295ed-5df2-5456-988c-5fdbab071054|1\u0026amp;quot;,\u0026amp;quot;ClassId\u0026amp;quot;:1073872969,\u0026amp;quot;Properties\u0026amp;quot;:[201342446,\u0026amp;quot;1\u0026amp;quot;,201342447,\u0026amp;quot;5\u0026amp;quot;,201342448,\u0026amp;quot;1\u0026amp;quot;,201342449,\u0026amp;quot;1\u0026amp;quot;,469777841,\u0026amp;quot;Aptos\u0026amp;quot;,469777842,\u0026amp;quot;Arial\u0026amp;quot;,469777843,\u0026amp;quot;Aptos\u0026amp;quot;,469777844,\u0026amp;quot;Aptos\u0026amp;quot;,201341986,\u0026amp;quot;1\u0026amp;quot;,469769226,\u0026amp;quot;Aptos,Arial\u0026amp;quot;,268442635,\u0026amp;quot;24\u0026amp;quot;,335559739,\u0026amp;quot;180\u0026amp;quot;,335559738,\u0026amp;quot;180\u0026amp;quot;,469775450,\u0026amp;quot;First Paragraph\u0026amp;quot;,201340122,\u0026amp;quot;2\u0026amp;quot;,134234082,\u0026amp;quot;true\u0026amp;quot;,134233614,\u0026amp;quot;true\u0026amp;quot;,469778129,\u0026amp;quot;FirstParagraph\u0026amp;quot;,335572020,\u0026amp;quot;1\u0026amp;quot;,469775498,\u0026amp;quot;Body Text\u0026amp;quot;,469778324,\u0026amp;quot;Body Text\u0026amp;quot;]}\u0026quot;\u0026gt;As a Senior Design Verification Engineer, you will help build and\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot;\u0026gt;validate\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot;\u0026gt;\u0026amp;nbsp;complex connectivity silicon that enables the next generation of AI infrastructure. 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data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;0\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Create directed and\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;constrained-random\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;\u0026amp;nbsp;tests, transaction-level sequences, and user-controlled random constraints.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Write assertions and cover properties, analyze coverage data, and drive closure against verification goals.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Automate verification infrastructure and regression workflows using Python or Perl.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Debug and Cross-Functional Collaboration\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;0\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Collaborate with RTL designers and other engineers to isolate, debug, and resolve failures across simulation, co-simulation, and FPGA-based emulation.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Apply third-party verification IP to\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;validate\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;\u0026amp;nbsp;protocols including PCIe, Ethernet, InfiniBand, DDR,\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;NVMe\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;, and USB.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Contribute to technical reviews, communicate verification status clearly, and manage priorities across multiple deliverables.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 2\u0026quot;\u0026gt;Basic Qualifications\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335559738\u0026amp;quot;:160,\u0026amp;quot;335559739\u0026amp;quot;:80}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Bachelor’s degree in Electrical Engineering\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;\u0026amp;nbsp;or\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;a related\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;\u0026amp;nbsp;field.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;2 - 5 years of experience developing or verifying complex SoC or silicon products.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Hands-on experience with\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;SystemVerilog\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;, UVM, and C/C++ in production verification environments.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Experience integrating C/C++ with\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;SystemVerilog\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;\u0026amp;nbsp;environments using DPI or PLI.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;7\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Experience developing verification infrastructure and tests in directed and constrained-random environments.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;8\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Strong debugging, prioritization, collaboration, and communication skills.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; 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data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;10\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Experience verifying PCIe across the physical, link, and transaction layers.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;11\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Experience with DDR4, DDR5, or HBM memory technologies.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;12\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Experience with FPGA-based verification or emulation.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;13\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Experience verifying Ethernet protocols across the PMA,\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;PCS\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;\u0026amp;nbsp;and MAC layers.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;14\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Experience debugging SoC software, including kernels, device drivers, or U-Boot.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;15\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Familiarity with\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;verification\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;\u0026amp;nbsp;IP from third-party vendors and protocol-level modeling.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;16\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Self-directed, adaptable approach with a strong focus on quality, execution, and customer impact.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184340005,"name":"Silicon Engineering SCE","child_ids":[],"parent_id":null}],"offices":[{"id":4000119005,"name":"Toronto","location":"Canada","child_ids":[],"parent_id":4004709005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4701333005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4438397005,"location":{"name":"Tel Aviv-Yafo, Tel Aviv District, Israel"},"metadata":[{"id":12122734005,"name":"Country","value":"Israel","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Tel Aviv","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Design Verification","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4701333005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2601","title":"Senior Design Verification Engineer ","company_name":"Astera Labs","first_published":"2026-06-01T05:43:30-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is establishing a strategic R\u0026amp;amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical \u0026#39;data bottlenecks\u0026#39; enabling the future of AI at scale. As we expand our presence in Israel, we\u0026#39;re seeking a talented\u0026amp;nbsp;\u0026lt;strong\u0026gt;Senior Design Verification Engineer\u0026lt;/strong\u0026gt;\u0026amp;nbsp;to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, developing the verification environments that ensure our next-generation AI silicon performs flawlessly.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As a\u0026amp;nbsp;\u0026lt;strong\u0026gt;Senior Design Verification Engineer\u0026lt;/strong\u0026gt;, you will be a vital contributor to the quality and reliability of our Israel R\u0026amp;amp;D center. You will work on the front lines of functional verification, developing testbenches and environments that validate high-performance digital blocks, subsystems, and full-chip designs. You will tackle complex verification challenges that ensure our connectivity solutions meet the rigorous demands of the world\u0026#39;s largest AI clusters. If you thrive on solving technical puzzles and want to play a key role in delivering cutting-edge AI infrastructure connectivity, this is your opportunity.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Verification Environment Development\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Contribute to the design and development of ASIC verification environments, focusing on unit-level and subsystem functional blocks\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Develop and maintain SystemVerilog/UVM-based components including traffic generators, monitors, and checkers to ensure robust testing\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Execute detailed verification plans for challenging digital designs, ensuring all functional requirements are met and verified\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Coverage \u0026amp;amp; Quality Assurance\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Implement functional coverage models and analyze results to identify gaps in the verification process\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Drive designs toward 100% verification closure through comprehensive test development\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Contribute to verification methodology improvements and best practices\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Debug \u0026amp;amp; Cross-Functional Collaboration\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Work closely with design engineers to identify, root-cause, and resolve complex hardware bugs early in the development cycle\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Apply analytical skills and debugging techniques to solve intricate verification challenges\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Collaborate effectively in a fast-paced, team-oriented R\u0026amp;amp;D environment\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering or related technical field\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;3+ years of proven experience in ASIC verification within the semiconductor industry\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Hands-on experience developing components within complex verification environments using SystemVerilog\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Strong working knowledge of standard verification methodologies, specifically UVM\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Sharp analytical mind with passion for debugging and technical problem-solving\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Excellent communication skills with ability to thrive in collaborative R\u0026amp;amp;D environments\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Master\u0026#39;s degree in Electrical Engineering or related field\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Familiarity with Formal Verification or Emulation flows\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Basic proficiency in scripting languages such as Python or Tcl to automate verification tasks\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Exposure to industry-standard protocols such as AMBA, PCIe, Ethernet, or CXL\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience with assertion-based verification and constrained-random testing\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Background in connectivity or networking silicon verification\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4052111005,"name":"Haifa","location":"Israel","child_ids":[],"parent_id":4008937005},{"id":4056876005,"name":"Tel Aviv","location":"Israel","child_ids":[],"parent_id":4008937005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4731809005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4453486005,"location":{"name":"Toronto, Ontario, Canada"},"metadata":[{"id":12122734005,"name":"Country","value":"Canada","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Toronto","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Digital Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4731809005,"updated_at":"2026-09-30T11:07:07-04:00","requisition_id":"2026-012","title":"Senior Digital Design Engineer","company_name":"Astera Labs","first_published":"2026-09-10T18:21:14-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 2\u0026quot;\u0026gt;Role Overview\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335559738\u0026amp;quot;:160,\u0026amp;quot;335559739\u0026amp;quot;:80}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot; data-ccp-parastyle-defn=\u0026quot;{\u0026amp;quot;ObjectId\u0026amp;quot;:\u0026amp;quot;276295ed-5df2-5456-988c-5fdbab071054|1\u0026amp;quot;,\u0026amp;quot;ClassId\u0026amp;quot;:1073872969,\u0026amp;quot;Properties\u0026amp;quot;:[201342446,\u0026amp;quot;1\u0026amp;quot;,201342447,\u0026amp;quot;5\u0026amp;quot;,201342448,\u0026amp;quot;1\u0026amp;quot;,201342449,\u0026amp;quot;1\u0026amp;quot;,469777841,\u0026amp;quot;Aptos\u0026amp;quot;,469777842,\u0026amp;quot;Arial\u0026amp;quot;,469777843,\u0026amp;quot;Aptos\u0026amp;quot;,469777844,\u0026amp;quot;Aptos\u0026amp;quot;,201341986,\u0026amp;quot;1\u0026amp;quot;,469769226,\u0026amp;quot;Aptos,Arial\u0026amp;quot;,268442635,\u0026amp;quot;24\u0026amp;quot;,335559739,\u0026amp;quot;180\u0026amp;quot;,335559738,\u0026amp;quot;180\u0026amp;quot;,469775450,\u0026amp;quot;First Paragraph\u0026amp;quot;,201340122,\u0026amp;quot;2\u0026amp;quot;,134234082,\u0026amp;quot;true\u0026amp;quot;,134233614,\u0026amp;quot;true\u0026amp;quot;,469778129,\u0026amp;quot;FirstParagraph\u0026amp;quot;,335572020,\u0026amp;quot;1\u0026amp;quot;,469775498,\u0026amp;quot;Body Text\u0026amp;quot;,469778324,\u0026amp;quot;Body Text\u0026amp;quot;]}\u0026quot;\u0026gt;As a Senior Digital Design Engineer, you will design and integrate high-performance connectivity silicon for the next generation of AI infrastructure. You will contribute across architecture, micro-architecture, RTL implementation, synthesis, timing closure, and IP integration for PCIe and Ethernet controllers, bridges, switches, and related SerDes interfaces.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:180,\u0026amp;quot;335559739\u0026amp;quot;:180}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Body Text\u0026quot;\u0026gt;You will work with cross-functional teams to turn complex connectivity requirements into robust, production-ready designs. Your work will span block-level and full-chip development at advanced process nodes and help enable reliable, high-bandwidth connections among CPUs, GPUs, memory, storage, and networking devices in rack-scale AI systems. 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data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Bachelor’s degree in Electrical Engineering, Electronics Engineering, or a related field.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;2 - 5 years of experience in digital design and implementation for complex SoC or silicon products.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Hands-on experience developing RTL in SystemVerilog or Verilog, including synthesis and timing closure.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Experience with PCIe or Ethernet controller, bridge, switch, PCS, PHY, or SerDes design and IP integration.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;7\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Experience with front-end design, gate-level simulation, clock-domain crossing, lint, or related design-quality methodologies.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;8\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Experience using Python or Perl to automate design, integration, or analysis workflows.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;9\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Ability to collaborate effectively across design, verification, physical design, DFT, firmware, and system teams.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;10\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Authorized to work in Canada.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 2\u0026quot;\u0026gt;Preferred Qualifications\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335559738\u0026amp;quot;:160,\u0026amp;quot;335559739\u0026amp;quot;:80}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;11\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Experience with PCIe or Ethernet SerDes controller or IP-level design, including PCIe Gen 6/7, UALink, or UCI.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;12\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Experience with block-level and full-chip implementation at advanced process nodes of 16 nm or smaller.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;13\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Knowledge of PAD design, DFT, floor planning, and top-level integration.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;14\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Experience developing NIC, switch, storage, or other high-performance connectivity products with embedded firmware interaction.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;15\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Familiarity with continuous integration and continuous delivery workflows for design and verification.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;16\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Experience with FPGA-based prototyping, emulation, or post-silicon debug.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot;\u0026gt;Salary range is $139,500 to $155,000 CAD depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:180,\u0026amp;quot;335559739\u0026amp;quot;:180}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184340005,"name":"Silicon Engineering SCE","child_ids":[],"parent_id":null}],"offices":[{"id":4000119005,"name":"Toronto","location":"Canada","child_ids":[],"parent_id":4004709005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4738468005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4456733005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Digital Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4738468005,"updated_at":"2026-09-30T11:05:55-04:00","requisition_id":"2026-458","title":"Senior Digital Design Engineer","company_name":"Astera Labs","first_published":"2026-09-28T17:40:45-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;/span\u0026gt;\u0026lt;a href=\u0026quot;http://www.asteralabs.com/\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-charstyle=\u0026quot;Hyperlink\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/a\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Job Description\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;We are looking for \u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Digital Design Engineers \u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;with experience developing micro-architecture and implementation of the front-end circuit design, including RTL, synthesis, IP integration for high performance network controllers. The candidate is preferred to have knowledge of communication/interface protocols such as PCI-Express (Gen-3 and above), Ualink, Esun, Ethernet etc.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Basic Qualifications:\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE is required, and a Master’s degree is preferred.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Professional attitude with the ability to prioritize a dynamic list of multiple tasks.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Entrepreneurial, open-mind behavior and can-do attitude.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Authorized to work in the US and start immediately.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Required Experience:\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Hands-on, prefer knowledge of high-speed protocols like PCIe, Ualink, Esun, Ethernet, etc.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; 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By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;h3\u0026gt;Role Overview\u0026lt;/h3\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is seeking a \u0026lt;strong\u0026gt;Senior Director of Corporate Development\u0026lt;/strong\u0026gt; to lead strategic transactions — including acquisitions, investments, and partnerships — that will shape the future of AI connectivity. Reporting to the Head of Corporate Development, you will partner with engineering, product, and executive leadership to identify, evaluate, and execute opportunities that align with our long-term growth strategy.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This is a high-visibility opportunity to join a hyper-growth semiconductor company at the epicenter of rack-scale AI infrastructure. Your work will directly influence executive and board-level decisions and help scale the purpose-built connectivity backbone powering the next generation of AI data centers.\u0026lt;/p\u0026gt;\n\u0026lt;h3\u0026gt;Key Responsibilities\u0026lt;/h3\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Strategic Transaction Leadership\u0026lt;/strong\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Lead corporate development transactions end-to-end, from target identification through close and integration\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Partner with executive and engineering leaders to evaluate opportunities, address strategic gaps, and drive build/buy/partner analyses\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Own deal project management across the full lifecycle, ensuring timely execution and stakeholder alignment\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Financial \u0026amp;amp; Strategic Analysis\u0026lt;/strong\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Conduct detailed valuation, pro forma modeling, and investment assessments to evaluate deal alignment\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop executive and board-ready presentation materials with clear recommendations\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Research adjacent and new market opportunities, including opportunity sizing, target landscaping, and competitive analysis\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional Collaboration \u0026amp;amp; Integration\u0026lt;/strong\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Drive diligence workstreams across engineering, product, finance, legal, and operations to validate key assumptions and value drivers\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Oversee post-merger integration to ensure deals deliver long-term strategic and financial value\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Continually refine the company\u0026#39;s framework and playbook for acquiring new capabilities and partnerships\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Market Intelligence\u0026lt;/strong\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Build deep expertise in emerging AI infrastructure technologies, companies, and business models\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Monitor industry trends and competitive dynamics to inform corporate development strategy and executive decision-making\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h3\u0026gt;Basic Qualifications\u0026lt;/h3\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor\u0026#39;s degree in Business Administration, Electrical Engineering, Computer Science, or related field\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;12+ years of overall professional experience across corporate development, investment banking, private equity, venture capital, or related roles, with 5–8 years in a leadership or management capacity\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Semiconductor corporate development experience, or investment banking experience covering the semiconductor sector\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Demonstrated track record leading strategic transactions and engaging directly with executive leadership\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong analytical skills with expertise in valuation, financial modeling, and strategic analysis\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent communication and presentation skills, with the ability to convey complex concepts clearly to diverse audiences\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h3\u0026gt;Preferred Qualifications\u0026lt;/h3\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;MBA or advanced degree\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Direct M\u0026amp;amp;A experience in the semiconductor or data center infrastructure space\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with post-merger integration planning and execution\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with AI/ML infrastructure trends and the evolving data center connectivity landscape\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Willingness to travel as needed for deals, industry events, and conferences\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Base salary range is $220,000 to $280,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4144039005,"name":"Corporate Development","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4661550005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4419495005,"location":{"name":"San Jose, CA"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"System Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4661550005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2283","title":"Senior Director System Validation Engineer ","company_name":"Astera Labs","first_published":"2026-02-20T21:02:24-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;Astera Labs is seeking an exceptional \u0026lt;strong\u0026gt;Senior Director System Validation\u0026lt;/strong\u0026gt; to lead our AI Fabric Validation organization. Connectivity is a critical component of every AI accelerator deployment and hyperscale data center architecture. As part of the AI Fabric Engineering group, you will play a key role in ensuring that Astera Labs’ fabric solutions perform at scale and deliver system-level performance across the most demanding AI and ML workloads. This role offers a unique opportunity to shape validation strategy for cutting-edge connectivity silicon and gain deep insight into next-generation AI infrastructure platforms. Your primary responsibility will be to build and lead a world-class validation organization tasked with validating all silicon, firmware, and system-level solutions at scale, ensuring performance, reliability, and production readiness across customer deployments.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Job Description\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Seeking a strong technical leader who has delivered multiple SoC products.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead and scale the system validation organization for Astera Labs\u0026#39; AI fabric portfolio, building a high-performing team across multiple concurrent product programs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Understand the performance and functionality requirements of our AI fabric switches to enable customers to develop Data Center systems using Astera Labs\u0026#39; connectivity products for AI and ML applications.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Own comprehensive validation strategies for AI fabric switch products. Drive execution through scalable automation platforms and data-centric testing with automated reporting and specification compliance verification.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate cross-functionally with Architecture, Hardware, Firmware, and Software teams to influence product requirements and ensure validation excellence.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ensure timely bring‑up of new silicon and platforms, driving root‑cause analysis and cross‑functional debug of hardware, firmware, and system issues.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deliver high‑confidence validation results that support product qualification, customer sampling, and mass production readiness.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Engage directly with key customers to understand their requirements and highlight the unique capabilities of Astera Labs\u0026#39; solutions.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;The ideal candidate brings deep expertise in silicon/system validation, a strong architectural mindset, and a proven ability to scale organizations in fast‑moving, high‑performance computing environments.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work closely with silicon design, architecture, Firmware, software engineering teams to ensure cohesive validation strategies.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive a culture of technical excellence, accountability, and continuous improvement.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Manage resource planning, and vendor/partner relationships.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong academic background in Electrical or Computer Engineering. Bachelor\u0026#39;s required, Master\u0026#39;s preferred.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;≥15 years\u0026#39; experience supporting or developing complex SoC/silicon products for Server, Storage, Networking applications and high‑performance hardware companies.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;≥5 years hands-on experience with Silicon/System bring-up, validation, and debug, including in customer systems.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;≥5 years building high performance Engineering teams and validation methodologies.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep understanding of CPU, GPU, SoC, or AI/ML accelerator architectures, including memory subsystems, I/O, power management, and firmware interactions.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Expertise in validation methodologies: pre‑silicon simulation/emulation, post‑silicon bring‑up, system validation, stress testing, and performance characterization.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong background in debug methodologies, lab infrastructure, and automation frameworks.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent communication skills and ability to influence executives and cross‑functional partners.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;≥8 years leading validation teams planning, execution and maintaining project visibility.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;≥10 years hands-on experience with Silicon/System bring-up, validation, and debug, including in customer systems.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Thorough knowledge of high-speed protocols like PCIe, CXL, NVMe, or Ethernet.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep understanding of High-Speed Signaling Principles and x86/ARM architecture, UEFI/Linux boot sequence.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;The base salary range is $240,000 USD - $300,000 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025528005,"name":"Software Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4703734005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4439574005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Firmware/Software Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4703734005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2621","title":"Senior Embedded Software Engineer - Ethernet Retimers","company_name":"Astera Labs","first_published":"2026-06-05T18:38:56-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs\u0026#39; Taurus product line includes Ethernet retimers and gearboxes deployed in active electrical cables and in-system applications at the heart of AI infrastructure. As AI clusters scale to tens of thousands of GPUs connected by high-speed Ethernet fabrics, the firmware running on these connectivity devices is mission-critical — and so is the ability to debug it fast when something breaks.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;We\u0026#39;re looking for a \u0026lt;strong\u0026gt;Firmware Engineer\u0026lt;/strong\u0026gt; who can bridge our system validation team and firmware development organization. When something goes wrong in the lab or in the field, you won\u0026#39;t be waiting on others to dig into the firmware. You\u0026#39;ll be the person in the room who understands both sides — can pull up the code, identify the problem, and fix it. If you\u0026#39;ve worked at a networking company, know how Ethernet actually works from the MAC down through the PHY, have debugged real link failures, and have written or modified firmware or low-level drivers, this role was designed for you.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Your primary focus will be debug and system integration. You will be an integral part of the firmware team and work on new feature development, but you will be the point person in the lab helping to unblock other teams — triaging failures, understanding what the firmware is doing, and making targeted fixes without requiring a long handoff loop. Beyond that, you\u0026#39;ll contribute to feature development and help bring new products from initial bringup into customer deployment.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Debug \u0026amp;amp; System Integration\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Work directly with the system validation team to debug firmware behavior across different Ethernet configurations, link states, and failure modes\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Investigate and fix firmware issues in embedded C, leveraging deep understanding of how Layer 1 PHY, SERDES, FEC/PCS, MAC, and retimer components interact\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Serve as the connective tissue between firmware and system validation teams, triaging issues and driving them to resolution without long handoff loops\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Customer Bring-Up \u0026amp;amp; Field Support\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Support customer bring-up and integration activities, including triaging field issues and coordinating fixes with internal teams\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Partner with field applications engineers to diagnose and resolve deployment issues quickly\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Firmware Feature Development\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Contribute to firmware feature development for SERDES configuration, link training, equalization, and diagnostics\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Partner with SoC, field applications, and platform teams across the full product lifecycle\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Help bring new Taurus products from initial silicon bringup through customer deployment\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;5+ years of experience in firmware development or embedded systems engineering\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Hands-on experience with Ethernet at the system or device level: Layer 1 PHY, SERDES, retimers, gearboxes, NICs, switches, or related devices\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Solid embedded C/C++ skills and comfort working in a firmware codebase on real hardware\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Ability to debug across the hardware/software boundary: register accesses, embedded SDKs, link state machines, PHY telemetry, debug print logs\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Familiarity with Linux development tools: gcc/clang, make, bash, gdb, git\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Strong communication skills and comfort working in a fast-moving environment where the problem in front of you may not have a clean solution\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience with switch or NIC management software, SAI, or OpenBMC\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Knowledge of PMA, FEC, or other PHY-layer subsystems beyond the SERDES\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Background with retimer or gearbox firmware or SDK/API development\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Python scripting for debug, test automation, or data analysis\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience with lab equipment: BERT, oscilloscopes, Viavi/Lecroy/Exfo/Keysight/Tektronix or similar\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Understanding of signal integrity: equalization, jitter, eye diagrams, link margin\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Prior experience mentoring engineers or leading debug efforts across teams\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Salary range is $133,200 to $185,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025528005,"name":"Software Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4649850005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4414096005,"location":{"name":"Israel"},"metadata":[{"id":12122734005,"name":"Country","value":"Israel","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Tel Aviv","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":"Silicon Engineering CCE2","value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Design Emulation","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4649850005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2201","title":"Senior Emulation Engineer","company_name":"Astera Labs","first_published":"2026-01-15T19:52:32-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is establishing a strategic R\u0026amp;amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical \u0026#39;data bottlenecks\u0026#39; enabling the future of AI at scale. As we expand our presence in Israel, we\u0026#39;re seeking a talented \u0026lt;strong\u0026gt;Senior\u0026lt;/strong\u0026gt; \u0026lt;strong\u0026gt;Emulation Engineer\u0026lt;/strong\u0026gt; to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, implementing the emulation strategy for chips that power the world\u0026#39;s largest AI clusters.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As an \u0026lt;strong\u0026gt;Senior Emulation Engineer\u0026lt;/strong\u0026gt;, you will be a core technical driver of our Israel R\u0026amp;amp;D center, working at the intersection of hardware and software to ensure our silicon meets extreme quality and performance targets. You will execute end-to-end emulation flows, bridge the gap between RTL and functional validation, and partner with cross-functional teams to enable seamless hardware-software integration. If you thrive on solving complex technical challenges and want to play a key role in validating cutting-edge AI infrastructure connectivity solutions, this is your opportunity.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Emulation Flow Execution \u0026amp;amp; Implementation\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Execute end-to-end emulation flow from high-level model generation and RTL synthesis to complex system-level testing and silicon-accurate debugging\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Work directly with next-generation emulation platforms (Zebu, Palladium, or Veloce) to implement cutting-edge methodologies\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Maintain and evolve emulation flows to reduce compile times and increase execution speed, directly impacting time-to-market\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;System-Level Debug \u0026amp;amp; Validation\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Drive initial model bring-up process in high-stakes environment, identifying and resolving complex bugs\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Ensure rapid cycles from RTL to functional stability through systematic debug approaches\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Own technical blocks and drive them to completion independently\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional Collaboration\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Partner with Firmware, Software, and Validation teams to debug complex system-level scenarios\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Ensure seamless hardware-software integration for AI infrastructure connectivity\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Collaborate with Design and Verification teams to optimize emulation strategies\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, Computer Engineering, or related technical field\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;3+ years of hands-on experience in Emulation at semiconductor companies\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Deep expertise in emulation flows for large-scale chips using industry-standard emulators (Zebu, Palladium, or Veloce)\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Strong background in SystemVerilog for developing, testing, and debugging complex SoC designs\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience developing and maintaining execution flows for building, running, and debugging emulation models\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\u0026quot;Can-do\u0026quot; approach with ability to own technical blocks and drive them to completion independently\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Master\u0026#39;s degree in Electrical Engineering, Computer Engineering, or related field\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Familiarity with EDA tools for Lint, Clock Domain Crossing (CDC), simulation, and synthesis\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Proficiency in scripting languages such as Python or TCL for automation and flow enhancement\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience with standard debug environments (e.g., Verdi)\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Knowledge of high-speed interface protocols (PCIe, Ethernet, CXL, UALink)\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Background in hardware-software co-verification methodologies\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184339005,"name":"Silicon Engineering CCE2","child_ids":[],"parent_id":null}],"offices":[{"id":4056876005,"name":"Tel Aviv","location":"Israel","child_ids":[],"parent_id":4008937005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4720222005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4447550005,"location":{"name":"Singapore, Singapore"},"metadata":[{"id":12122734005,"name":"Country","value":"Singapore","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Singapore City","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Analog/AMS Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4720222005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":null,"title":"Senior Engineer PD","company_name":"Astera Labs","first_published":"2026-08-04T03:19:01-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;About the Role\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;We are seeking a Senior Physical Design Engineer to join our high-performance design team working on next-generation transceiver IPs targeting the TSMC 3nm and advanced technology nodes\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Perform block-level and top-level physical implementation including floorplanning, placement, clock tree synthesis (CTS), routing, and physical verification for high-speed designs in advanced technology nodes.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Collaborate with RTL and STA teams to ensure clean handoffs and support timing, area, and power convergence.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Apply advanced physical design techniques to support multiple voltage and frequency domains, hierarchical design, and physical-aware synthesis.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Work on key physical design areas including:\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;EM/IR analysis and power grid optimization\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Congestion analysis and mitigation\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Clock skew optimization and clock quality improvement\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;RC extraction-aware placement and routing\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Integrate IPs and top-level blocks with attention to physical interfaces, constraints, and timing alignment.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Support floorplan development and chip partitioning for high-speed transceiver designs.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Perform ECO implementation and assist with tapeout signoff activities.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Ensure DRC, LVS, ANT, CELL, and ERC clean databases using industry-standard physical verification tools.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Use industry-standard tools such as ICC2, Innovus, Voltus, RedHawk, and Calibre for implementation and signoff.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Develop and maintain automation scripts in Tcl, Python, or Perl to improve physical design flows and productivity.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, or a related field.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;5+ years of experience in physical design, preferably with advanced technology nodes.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Strong experience with:\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Floorplanning, placement, CTS, routing, and IR drop mitigation\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Signoff checks such as DRC, LVS, ANT, and ERC, along with debugging\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Timing closure support in collaboration with STA teams\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Hands-on use of tools such as Synopsys ICC2, Cadence Innovus, Calibre, and Voltus\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Experience integrating high-speed IPs such as SerDes or PHYs into SoC or chiplet-based environments.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Experience working on high-frequency datapath and DSP-related designs.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Solid scripting skills for automation and productivity enhancement.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Good problem-solving skills and the ability to work effectively in cross-functional teams.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184199005,"name":"AMS-PHY","child_ids":[],"parent_id":null}],"offices":[{"id":4052115005,"name":"Singapore City","location":"Singapore","child_ids":[],"parent_id":4050465005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4740292005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4457648005,"location":{"name":"Tel Aviv-Yafo, Tel Aviv District, Israel"},"metadata":[{"id":12122734005,"name":"Country","value":"Israel","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Tel Aviv","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Firmware/Software Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4740292005,"updated_at":"2026-10-05T05:00:04-04:00","requisition_id":null,"title":"Senior Firmware SW Engineer","company_name":"Astera Labs","first_published":"2026-10-04T12:46:39-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;h2 class=\u0026quot;wnfdnti _1ibi0s35e _1ibi0s36a\u0026quot;\u0026gt;The Role and Its Impact\u0026lt;/h2\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Our firmware team develops the embedded firmware that brings Astera Labs\u0026#39; compute connectivity silicon to life, from boot and initialization through link management, telemetry, error handling, and diagnostics. This firmware runs on the embedded processors inside our chips and ships in data centers powering AI infrastructure around the world. Beyond the firmware, the team also develops the COSMOS SDK, the software layer customers and internal teams use to configure, monitor, update, and debug our devices in their systems.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;We are looking for an experienced firmware engineer who enjoys working close to the hardware, owns features end to end, and is equally comfortable in a pre-silicon emulation environment and in the lab with real silicon. You understand the whole system, not just the chip: how our devices behave inside customer platforms, and how a customer requirement turns into firmware and SDK. You\u0026#39;ll work alongside architects, design and verification engineers, validation teams, and our global firmware teams to take new products from early pre-silicon development through bring-up and into customer deployment.\u0026lt;/p\u0026gt;\n\u0026lt;h2 class=\u0026quot;wnfdnti _1ibi0s35e _1ibi0s36a\u0026quot;\u0026gt;What You\u0026#39;ll Be Doing\u0026lt;/h2\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdntf\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Having fun! by being part of a very strong and cohesive group.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Design, implement, and maintain real-time embedded firmware in C for high-performance connectivity\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Develop low-level drivers, initialization flows, interrupt handling, and control logic for complex hardware blocks\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Bring up and debug firmware in pre-silicon environments (emulation) ahead of tape-out, and on silicon after it arrives\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Work closely with architecture, design, and verification teams to define HW/FW interfaces and to resolve issues across the hardware/software boundary\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Triage and resolve firmware issues reported by validation, product applications, and customers\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Take part in design reviews and code reviews, and help improve our firmware quality, tooling, and development practices\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Develop and extend the company SDK, including APIs, device management, firmware update, telemetry, and diagnostics capabilities, and keep it aligned with firmware features\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Support customer requests and engagements together with product applications and field teams, analyze system-level use cases, and adjust firmware and SDK development to meet customer needs\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Collaborate with firmware teams across sites to deliver features on schedule\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h2 class=\u0026quot;wnfdnti _1ibi0s35e _1ibi0s36a\u0026quot;\u0026gt;What We\u0026#39;re Looking For\u0026lt;/h2\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Required:\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdntf\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;BSc/MSc in Computer Science, Electrical Engineering, Computer Engineering, or a related field\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;10+ years of hands-on experience as a firmware engineer\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Proven experience in embedded and real-time firmware development\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Strong programming skills in C on resource-constrained, bare-metal, or RTOS-based systems\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Solid understanding of processor architecture, memory-mapped registers, interrupts, and HW/SW interaction\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Strong debugging skills on real hardware using JTAG debuggers, logs, and register-level analysis\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Broad system-level understanding of how silicon, firmware, SDK, host software, and platform interact, with the ability to turn customer requirements into technical solutions\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;A team player with excellent communication skills who works well in a collaborative, cross-site environment\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Comfort with ambiguity and ownership in a fast-moving, high-growth company\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Advantage:\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdntf\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Experience with pre-silicon emulation platforms such as Cadence Palladium or Synopsys ZeBu\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Knowledge of PCIe (link training, enumeration, configuration space, error handling)\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Experience developing SDKs, host-side libraries, or APIs (C/C++ or Python) that interface with embedded firmware\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Experience working directly with customers or supporting customer integration and field issues\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Experience with silicon bring-up of new SoCs\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdnte _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Python scripting for test automation, debug, or data analysis\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184367005,"name":"Firmware \u0026 Software CCE2","child_ids":[],"parent_id":null}],"offices":[{"id":4052111005,"name":"Haifa","location":"Israel","child_ids":[],"parent_id":4008937005},{"id":4056876005,"name":"Tel Aviv","location":"Israel","child_ids":[],"parent_id":4008937005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4727604005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4451268005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Digital Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4727604005,"updated_at":"2026-10-08T03:37:14-04:00","requisition_id":"2026-237","title":"Senior Manager, Digital Design","company_name":"Astera Labs","first_published":"2026-09-17T12:49:52-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As Senior Manager/Manager, Digital Design, you will lead the front-end digital design of high-performance PCIe \u0026amp;amp; CXL, UAL, ethernet devices that enable reliable connectivity in rack-scale AI infrastructure. You will guide projects from requirements and architecture through RTL development, verification, physical design, tape-out, and product shipment, ensuring that complex designs meet demanding performance, quality, and schedule objectives.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This is an opportunity to influence the development of purpose-built connectivity products at a hyper-growth company, establish scalable design practices, and help deliver silicon that advances the next generation of AI systems.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;End-to-End Chip Development\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Lead digital design execution from product requirements and architecture through RTL, verification, tape-out, and production shipment.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive delivery of at least two complex devices, maintaining clear milestones, technical decisions, risk tracking, and schedule accountability.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Partner with architecture and system teams to translate PCIe \u0026amp;amp; CXL, UAL, ethernet requirements into robust, scalable digital implementations.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;RTL Quality and Tape-Out Readiness\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Set expectations for high-quality front-end RTL that enables efficient synthesis, timing closure, physical implementation, and smooth tape-out.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Establish and maintain design checklists, review gates, coding standards, and signoff criteria across the digital design lifecycle.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Resolve design, performance, power, area, clocking, and integration issues in partnership with verification, physical design, DFT, and validation teams.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Team and Cross-Functional Leadership\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Lead, mentor, and develop a team of 6–8 digital design engineers, fostering technical excellence, accountability, and effective collaboration.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Influence cross-functional development decisions and align engineering teams around quality, risk reduction, and on-time execution.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Communicate technical status, tradeoffs, dependencies, and mitigation plans to engineering and program leadership.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with PCIe \u0026amp;amp; CXL, UAL, ethernet digital design, including protocol implementation, high-speed connectivity requirements, and physical-layer considerations.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;3-5 years of experience in engineering management or technical leadership in digital IC or ASIC design.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Demonstrated ownership of chip design and development from requirements through tape-out and shipment for at least two devices of reasonable complexity.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong hands-on expertise developing front-end RTL and applying design practices that support predictable physical design progress and tape-out quality.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ability to lead 6–8 engineers and influence execution across architecture, verification, physical design, DFT, firmware, validation, and operations.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Expertise in RTL quality methodologies, design reviews, lint, clock-domain and reset-domain considerations, synthesis, timing, and signoff readiness.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience defining or improving design checklists, development flows, quality gates, and cross-functional tape-out processes.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Building design blocks with large physical floorplan sizes is a plus\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Track record of balancing performance, power, area, schedule, and risk across large SoC or ASIC programs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Master’s or PhD in Electrical Engineering, Computer Engineering, or a related field.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Salary range is $216,000 to $240,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184338005,"name":"Silicon Engineering CCE1","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4715728005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4442295005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":"Information Systems","value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"IT \u0026 Infrastructure","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4715728005,"updated_at":"2026-09-29T19:40:10-04:00","requisition_id":"2668","title":"Senior Oracle Fusion Financials Architect","company_name":"Astera Labs","first_published":"2026-07-15T19:11:37-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;h3 class=\u0026quot;wnfdnth _1ibi0s33y _1ibi0s34u\u0026quot; data-pm-slice=\u0026quot;1 3 []\u0026quot;\u0026gt;Role Overview\u0026lt;/h3\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;We are seeking a\u0026lt;strong\u0026gt; Senior Solutions Architect (Oracle Cloud Fusion Financials)\u0026lt;/strong\u0026gt; to lead the architecture and design of enterprise financial systems supporting financial accounting, reporting, and revenue processes. This role is responsible for defining and governing the solution architecture across Oracle Cloud Fusion platforms supporting the Finance organization. The architect will ensure the current platform is scalable, compliant, and aligned with the long-term enterprise ERP strategy. The position works closely with Finance Business users and translates business requirements into robust system architecture that supports financial operations, regulatory compliance, and reporting integrity.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;This role reports to Director of Information Systems and sits at the intersection of Finance and Enterprise Technology, supporting high-visibility, high-impact financial systems used for operational accounting, revenue management, and financial reporting. You will collaborate with Finance. The team operates in a highly collaborative environment, partnering closely with internal stakeholders across Accounting, Revenue, Treasury, FP\u0026amp;amp;A, and Enterprise Architecture, as well as strategic implementation partners.\u0026lt;/p\u0026gt;\n\u0026lt;h3 class=\u0026quot;wnfdnth _1ibi0s33y _1ibi0s34u\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/h3\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdnte\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Own the end-to-end solution architecture for Oracle ERP Financial modules.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Define scalable architecture patterns, system integrations, and data flows supporting financial operations.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Establish and enforce architecture standards, design governance, and technical controls across finance systems.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Ensure system designs support financial controls, audit requirements, and reporting integrity.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Define integration patterns between ERP and billing, procurement, banking, and data platforms, ensuring end-to-end data quality.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Contribute to the long-term ERP strategy and guide platform modernization toward Oracle Cloud.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Provide architecture oversight for implementations, upgrades, enhancements, and cross-functional projects.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Serve as a technical escalation point for complex financial system challenges.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h2 class=\u0026quot;wnfdnth _1ibi0s33y _1ibi0s34u\u0026quot;\u0026gt;Basic Qualifications\u0026lt;/h2\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdnte\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;8+ years of hands-on experience with Oracle Cloud Fusion ERP Financial modules including General Ledger, Accounts Payable, Accounts Receivable, Fixed Assets, Subledger Accounting, and Revenue Recognition, Cash Management.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Bachelor\u0026#39;s degree in computer science, Information Systems, CPA or a related field.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Proven experience designing and implementing complex financial system architectures in large enterprise environments.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Experience designing enterprise integrations and end-to-end financial data flows across multiple upstream and downstream systems.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Experience supporting large-scale Oracle Cloud ERP implementations or transformations.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Background working with global financial operations, multiple legal entities, and diverse regulatory environments.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Familiarity with financial reporting platforms, data platforms, and enterprise integration technologies.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Base salary range is $160,000 to $200,000 depending on experience, level, and business need. This role is eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025529005,"name":"IT and Infrastructure","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4735854005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4455360005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Packaging Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4735854005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":null,"title":"Senior Packaging Integration Lead","company_name":"Astera Labs","first_published":"2026-09-22T17:58:49-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Job Description\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335551550\u0026amp;quot;:6,\u0026amp;quot;335551620\u0026amp;quot;:6,\u0026amp;quot;335559738\u0026amp;quot;:144,\u0026amp;quot;335559739\u0026amp;quot;:144,\u0026amp;quot;335559745\u0026amp;quot;:60,\u0026amp;quot;335559746\u0026amp;quot;:60}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;We are seeking a\u0026amp;nbsp;Senior\u0026amp;nbsp;Packaging Integration\u0026amp;nbsp;Lead\u0026amp;nbsp;to serve as the single-threaded\u0026amp;nbsp;packaging owner for one or more of Astera Labs’ advanced connectivity products. This role owns the end-to-end packaging solution from customer requirements\u0026amp;nbsp;and package architecture definition through development, qualification, and production ramp\u0026amp;nbsp;\u0026amp;amp;\u0026amp;nbsp;represents packaging across the customer, internal cross-functional teams, business units, and the OSAT, foundry, and substrate supply base.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335551550\u0026amp;quot;:6,\u0026amp;quot;335551620\u0026amp;quot;:6,\u0026amp;quot;335559738\u0026amp;quot;:144,\u0026amp;quot;335559739\u0026amp;quot;:144,\u0026amp;quot;335559745\u0026amp;quot;:60,\u0026amp;quot;335559746\u0026amp;quot;:60}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;This is a senior individual-contributor technical leadership role who can set packaging technical direction, make architecture and technology-selection decisions, and drive alignment across stakeholders without direct authority. You will partner with packaging leadership on strategy while owning the technical direction for your products — defining package architecture and test vehicles to de-risk technology, and guiding execution engineers and external partners to deliver robust, manufacturable packages on schedule.\u0026amp;nbsp;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335551550\u0026amp;quot;:6,\u0026amp;quot;335551620\u0026amp;quot;:6,\u0026amp;quot;335559738\u0026amp;quot;:144,\u0026amp;quot;335559739\u0026amp;quot;:144,\u0026amp;quot;335559745\u0026amp;quot;:60,\u0026amp;quot;335559746\u0026amp;quot;:60}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335551550\u0026amp;quot;:6,\u0026amp;quot;335551620\u0026amp;quot;:6,\u0026amp;quot;335559738\u0026amp;quot;:144,\u0026amp;quot;335559739\u0026amp;quot;:144,\u0026amp;quot;335559745\u0026amp;quot;:60,\u0026amp;quot;335559746\u0026amp;quot;:60}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;Arial\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:460,\u0026amp;quot;335559991\u0026amp;quot;:260,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Own the packaging solution end-to-end for assigned products — serve as the single point of accountability from a packaging standpoint across definition, development, qualification, and production ramp\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335551550\u0026amp;quot;:6,\u0026amp;quot;335551620\u0026amp;quot;:6,\u0026amp;quot;335559738\u0026amp;quot;:144,\u0026amp;quot;335559739\u0026amp;quot;:144,\u0026amp;quot;335559745\u0026amp;quot;:60,\u0026amp;quot;335559746\u0026amp;quot;:60}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;Arial\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:460,\u0026amp;quot;335559991\u0026amp;quot;:260,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Act as the primary packaging interface to the customer: capture and translate customer packaging, mechanical, thermal,\u0026amp;nbsp;SIPI, and reliability requirements into package architecture, specifications, and a clear execution roadmap\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335551550\u0026amp;quot;:6,\u0026amp;quot;335551620\u0026amp;quot;:6,\u0026amp;quot;335559738\u0026amp;quot;:144,\u0026amp;quot;335559739\u0026amp;quot;:144,\u0026amp;quot;335559745\u0026amp;quot;:60,\u0026amp;quot;335559746\u0026amp;quot;:60}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;Arial\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:460,\u0026amp;quot;335559991\u0026amp;quot;:260,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Define package architecture, structure and technology selection (e.g., 2.5D/3D integration, chiplet/interposer, CoWoS-class, organic substrate) with feasibility, cost, performance, and manufacturability trade-off analysis\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335551550\u0026amp;quot;:6,\u0026amp;quot;335551620\u0026amp;quot;:6,\u0026amp;quot;335559738\u0026amp;quot;:144,\u0026amp;quot;335559739\u0026amp;quot;:144,\u0026amp;quot;335559745\u0026amp;quot;:60,\u0026amp;quot;335559746\u0026amp;quot;:60}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;Arial\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:460,\u0026amp;quot;335559991\u0026amp;quot;:260,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Define and drive test vehicle (TV) strategy and requirements to de-risk new package technology, characterize interconnect/SIPI performance, and validate assembly and reliability ahead of product builds\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335551550\u0026amp;quot;:6,\u0026amp;quot;335551620\u0026amp;quot;:6,\u0026amp;quot;335559738\u0026amp;quot;:144,\u0026amp;quot;335559739\u0026amp;quot;:144,\u0026amp;quot;335559745\u0026amp;quot;:60,\u0026amp;quot;335559746\u0026amp;quot;:60}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;Arial\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:460,\u0026amp;quot;335559991\u0026amp;quot;:260,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Represent packaging across internal cross-functional teams — silicon design, package design, SIPI, thermal, product engineering, test engineering, validation, quality, and operations — and align packaging requirements to product and business-unit roadmaps\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335551550\u0026amp;quot;:6,\u0026amp;quot;335551620\u0026amp;quot;:6,\u0026amp;quot;335559738\u0026amp;quot;:144,\u0026amp;quot;335559739\u0026amp;quot;:144,\u0026amp;quot;335559745\u0026amp;quot;:60,\u0026amp;quot;335559746\u0026amp;quot;:60}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;Arial\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:460,\u0026amp;quot;335559991\u0026amp;quot;:260,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Partner with\u0026amp;nbsp;product planning, architecture,\u0026amp;nbsp;and program management on product roadmap, packaging feasibility, technology readiness, cost targets, and schedule commitments\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335551550\u0026amp;quot;:6,\u0026amp;quot;335551620\u0026amp;quot;:6,\u0026amp;quot;335559738\u0026amp;quot;:144,\u0026amp;quot;335559739\u0026amp;quot;:144,\u0026amp;quot;335559745\u0026amp;quot;:60,\u0026amp;quot;335559746\u0026amp;quot;:60}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;Arial\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:460,\u0026amp;quot;335559991\u0026amp;quot;:260,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;7\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Set technical direction with OSAT, foundry\u0026amp;nbsp;\u0026amp;amp;\u0026amp;nbsp;substrate partners — driving technology selection, design-rule alignment, and development roadmaps across the supply base\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335551550\u0026amp;quot;:6,\u0026amp;quot;335551620\u0026amp;quot;:6,\u0026amp;quot;335559738\u0026amp;quot;:144,\u0026amp;quot;335559739\u0026amp;quot;:144,\u0026amp;quot;335559745\u0026amp;quot;:60,\u0026amp;quot;335559746\u0026amp;quot;:60}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;Arial\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:460,\u0026amp;quot;335559991\u0026amp;quot;:260,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;8\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Own package definition deliverables and\u0026amp;nbsp;sign-offs, including POR/TOR, design rules, stack-up, package BOM, DFM alignment, and pre-tape-out design-integration readiness\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335551550\u0026amp;quot;:6,\u0026amp;quot;335551620\u0026amp;quot;:6,\u0026amp;quot;335559738\u0026amp;quot;:144,\u0026amp;quot;335559739\u0026amp;quot;:144,\u0026amp;quot;335559745\u0026amp;quot;:60,\u0026amp;quot;335559746\u0026amp;quot;:60}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;Arial\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:460,\u0026amp;quot;335559991\u0026amp;quot;:260,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;9\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Drive risk identification, technology-gap closure, and mitigation across the product’s packaging roadmap; escalate and resolve critical cross-functional and supplier issues with urgency.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335551550\u0026amp;quot;:6,\u0026amp;quot;335551620\u0026amp;quot;:6,\u0026amp;quot;335559738\u0026amp;quot;:144,\u0026amp;quot;335559739\u0026amp;quot;:144,\u0026amp;quot;335559745\u0026amp;quot;:60,\u0026amp;quot;335559746\u0026amp;quot;:60}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;Arial\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:460,\u0026amp;quot;335559991\u0026amp;quot;:260,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;10\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Communicate packaging status, risks, and key decisions to executive leadership, customers, and cross-functional stakeholders\u0026amp;nbsp;\u0026amp;amp;\u0026amp;nbsp;external partners.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335551550\u0026amp;quot;:6,\u0026amp;quot;335551620\u0026amp;quot;:6,\u0026amp;quot;335559738\u0026amp;quot;:144,\u0026amp;quot;335559739\u0026amp;quot;:144,\u0026amp;quot;335559745\u0026amp;quot;:60,\u0026amp;quot;335559746\u0026amp;quot;:60}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Basic Qualifications\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335551550\u0026amp;quot;:6,\u0026amp;quot;335551620\u0026amp;quot;:6,\u0026amp;quot;335559738\u0026amp;quot;:144,\u0026amp;quot;335559739\u0026amp;quot;:144,\u0026amp;quot;335559745\u0026amp;quot;:60,\u0026amp;quot;335559746\u0026amp;quot;:60}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;Arial\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:460,\u0026amp;quot;335559991\u0026amp;quot;:260,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;11\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;B.S. or M.S. in Materials Science, Electrical Engineering, Mechanical Engineering, Chemical Engineering, or a related discipline; advanced degree preferred.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335551550\u0026amp;quot;:6,\u0026amp;quot;335551620\u0026amp;quot;:6,\u0026amp;quot;335559738\u0026amp;quot;:144,\u0026amp;quot;335559739\u0026amp;quot;:144,\u0026amp;quot;335559745\u0026amp;quot;:60,\u0026amp;quot;335559746\u0026amp;quot;:60}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;Arial\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:460,\u0026amp;quot;335559991\u0026amp;quot;:260,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;12\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;5-7+ yrs\u0026amp;nbsp;of experience in advanced packaging technologies such as 2.5D/3D integration, TSV, chiplets, and interposers. Optical / co-packaged optics experience is a plus.\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335551550\u0026amp;quot;:6,\u0026amp;quot;335551620\u0026amp;quot;:6,\u0026amp;quot;335559738\u0026amp;quot;:144,\u0026amp;quot;335559739\u0026amp;quot;:144,\u0026amp;quot;335559745\u0026amp;quot;:60,\u0026amp;quot;335559746\u0026amp;quot;:60}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;Arial\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:460,\u0026amp;quot;335559991\u0026amp;quot;:260,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;13\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Demonstrated end-to-end ownership of a product or platform packaging solution, from definition and architecture through qualification and production ramp\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335551550\u0026amp;quot;:6,\u0026amp;quot;335551620\u0026amp;quot;:6,\u0026amp;quot;335559738\u0026amp;quot;:144,\u0026amp;quot;335559739\u0026amp;quot;:144,\u0026amp;quot;335559745\u0026amp;quot;:60,\u0026amp;quot;335559746\u0026amp;quot;:60}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;Arial\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:460,\u0026amp;quot;335559991\u0026amp;quot;:260,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;14\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience defining package architecture and driving technology selection, including trade-off analysis across performance, cost, reliability, and manufacturability\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335551550\u0026amp;quot;:6,\u0026amp;quot;335551620\u0026amp;quot;:6,\u0026amp;quot;335559738\u0026amp;quot;:144,\u0026amp;quot;335559739\u0026amp;quot;:144,\u0026amp;quot;335559745\u0026amp;quot;:60,\u0026amp;quot;335559746\u0026amp;quot;:60}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;Arial\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:460,\u0026amp;quot;335559991\u0026amp;quot;:260,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;15\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience defining test vehicles and characterization/qualification strategies to de-risk new packaging technology.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335551550\u0026amp;quot;:6,\u0026amp;quot;335551620\u0026amp;quot;:6,\u0026amp;quot;335559738\u0026amp;quot;:144,\u0026amp;quot;335559739\u0026amp;quot;:144,\u0026amp;quot;335559745\u0026amp;quot;:60,\u0026amp;quot;335559746\u0026amp;quot;:60}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;Arial\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:460,\u0026amp;quot;335559991\u0026amp;quot;:260,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;16\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Direct customer-facing experience translating product and system requirements into package specifications and commitments.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335551550\u0026amp;quot;:6,\u0026amp;quot;335551620\u0026amp;quot;:6,\u0026amp;quot;335559738\u0026amp;quot;:144,\u0026amp;quot;335559739\u0026amp;quot;:144,\u0026amp;quot;335559745\u0026amp;quot;:60,\u0026amp;quot;335559746\u0026amp;quot;:60}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;Arial\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:460,\u0026amp;quot;335559991\u0026amp;quot;:260,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;17\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Strong architecture-level understanding of signal/power integrity (SIPI), thermal, and thermo-mechanical reliability considerations in advanced packages\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335551550\u0026amp;quot;:6,\u0026amp;quot;335551620\u0026amp;quot;:6,\u0026amp;quot;335559738\u0026amp;quot;:144,\u0026amp;quot;335559739\u0026amp;quot;:144,\u0026amp;quot;335559745\u0026amp;quot;:60,\u0026amp;quot;335559746\u0026amp;quot;:60}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;Arial\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:460,\u0026amp;quot;335559991\u0026amp;quot;:260,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;18\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Proven ability to lead and influence across internal cross-functional teams, business units, and external OSAT/foundry/substrate partners without direct authority.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335551550\u0026amp;quot;:6,\u0026amp;quot;335551620\u0026amp;quot;:6,\u0026amp;quot;335559738\u0026amp;quot;:144,\u0026amp;quot;335559739\u0026amp;quot;:144,\u0026amp;quot;335559745\u0026amp;quot;:60,\u0026amp;quot;335559746\u0026amp;quot;:60}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;Arial\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:460,\u0026amp;quot;335559991\u0026amp;quot;:260,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;19\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Hands-on background working with foundries, OSATs, substrate suppliers, and material vendors.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335551550\u0026amp;quot;:6,\u0026amp;quot;335551620\u0026amp;quot;:6,\u0026amp;quot;335559738\u0026amp;quot;:144,\u0026amp;quot;335559739\u0026amp;quot;:144,\u0026amp;quot;335559745\u0026amp;quot;:60,\u0026amp;quot;335559746\u0026amp;quot;:60}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;Arial\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:460,\u0026amp;quot;335559991\u0026amp;quot;:260,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; 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data-font=\u0026quot;Arial\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:460,\u0026amp;quot;335559991\u0026amp;quot;:260,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;22\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience with CoWoS-class, silicon-bridge, or advanced fan-out packaging platforms\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335551550\u0026amp;quot;:6,\u0026amp;quot;335551620\u0026amp;quot;:6,\u0026amp;quot;335559738\u0026amp;quot;:144,\u0026amp;quot;335559739\u0026amp;quot;:144,\u0026amp;quot;335559745\u0026amp;quot;:60,\u0026amp;quot;335559746\u0026amp;quot;:60}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; 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data-font=\u0026quot;Arial\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:460,\u0026amp;quot;335559991\u0026amp;quot;:260,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;24\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Track record engaging foundry and OSAT partners on advanced-packaging technology roadmaps\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335551550\u0026amp;quot;:6,\u0026amp;quot;335551620\u0026amp;quot;:6,\u0026amp;quot;335559738\u0026amp;quot;:144,\u0026amp;quot;335559739\u0026amp;quot;:144,\u0026amp;quot;335559745\u0026amp;quot;:60,\u0026amp;quot;335559746\u0026amp;quot;:60}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184332005,"name":"Packaging","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4720467005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4447674005,"location":{"name":"Germany (Onsite)"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":null,"value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4720467005,"updated_at":"2026-09-24T18:33:01-04:00","requisition_id":"2704","title":"Senior Principal ASIC Design Engineer","company_name":"Astera Labs","first_published":"2026-08-02T08:43:10-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;h1\u0026gt;\u0026lt;strong\u0026gt;Senior Principal ASIC Design Engineer\u0026lt;/strong\u0026gt;\u0026lt;/h1\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Location:\u0026lt;/strong\u0026gt; Germany (on-site)\u0026lt;/p\u0026gt;\n\u0026lt;h2\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/h2\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is building purpose-built silicon for rack-scale AI infrastructure. As a Distinguished Engineer, you will be a senior technical leader driving ASIC design for next-generation Ethernet and Scale-Up (ESUN) connectivity products.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;You will set technical direction across the full ASIC design flow, spanning high-speed Ethernet, UALink, UCIe, and PCIe Gen 6/7. You will solve complex scale-up networking challenges, mentor senior engineers, and turn ambitious product goals into robust, manufacturable silicon.\u0026lt;/p\u0026gt;\n\u0026lt;h2\u0026gt;\u0026lt;strong\u0026gt;Technical Leadership \u0026amp;amp; Architecture\u0026lt;/strong\u0026gt;\u0026lt;/h2\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Define and drive ASIC architecture for Ethernet/ESUN connectivity products across UALink, UCIe, PCIe Gen 6/7, and Ethernet.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead architecture and microarchitecture for high-performance Ethernet controllers, MACs, NIC datapaths, packet processing pipelines, and AI interconnect fabrics.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Define scalable, low-latency, high-bandwidth data movement, scheduling, buffering, congestion management, QoS, reliability, and flow control.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Architect hardware acceleration for NIC functions, RDMA, DMA, virtualization, and protocol offloads.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead tradeoff analysis across performance, power, area, latency, scalability, resiliency, and programmability.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Serve as a technical authority across digital, networking, and system domains.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h2\u0026gt;\u0026lt;strong\u0026gt;ASIC Design \u0026amp;amp; Execution\u0026lt;/strong\u0026gt;\u0026lt;/h2\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Lead RTL design and microarchitecture development for Ethernet controllers, MACs, NIC datapaths, protocol engines, and AI networking subsystems.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Design packet processing architectures, DMA engines, queue management, scheduling, buffering, and memory subsystem interfaces.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop hardware mechanisms for RDMA, zero-copy data movement, congestion control, transport reliability, and protocol acceleration.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Design scalable architectures supporting virtualization, multi-tenant isolation, traffic management, and quality of service.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Partner with firmware and software teams to define hardware/software interfaces for initialization, management, telemetry, performance monitoring, and diagnostics.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive execution from architecture through RTL, integration, verification, tapeout, and post-silicon bring-up.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Partner cross-functionally to meet performance, timing, power, area, manufacturability, and reliability targets.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h2\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/h2\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;12+ years of ASIC/SoC design experience, with a track record of delivering complex, high-speed networking or connectivity silicon from architecture through production.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep expertise in RTL design and microarchitecture for high-performance networking and connectivity ASICs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Extensive experience designing Ethernet controllers, MACs, NIC architectures, packet processing engines, or network interface subsystems.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of RDMA architectures and transport protocols such as RoCE, InfiniBand concepts, or similar low-latency networking technologies.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience designing hardware for packet parsing, scheduling, buffering, DMA, queue management, flow control, congestion management, and transport acceleration.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of high-speed interconnects and protocols, including Ethernet, PCIe, and AI scale-up fabrics.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience across the complete ASIC development flow, including architecture, RTL design, integration, synthesis, timing closure, physical implementation, tapeout, and post-silicon validation.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Demonstrated technical leadership across multiple teams and product programs.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h2\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/h2\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Master’s or PhD in Electrical Engineering, Computer Engineering, or a related technical discipline.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Direct experience with UALink, UCIe, PCIe Gen 6/7, and/or advanced Ethernet architectures and protocols.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience designing Ethernet MACs, controllers, SmartNICs, DPUs, NICs, switch datapaths, or packet processing engines.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience developing Ethernet-based scale-up networking solutions for AI and HPC systems.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience leading architecture or design for multiple successful advanced-node ASIC tapeouts.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent communication, collaboration, and mentorship skills.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184256005,"name":"Design Engineering CCE2","child_ids":[],"parent_id":null}],"offices":[{"id":4065803005,"name":"Germany (Onsite)","location":"Germany","child_ids":[],"parent_id":4056755005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4672620005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4424476005,"location":{"name":"San Jose, CA"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Digital Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4672620005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2361","title":"Senior Principal Digital Design Engineer ","company_name":"Astera Labs","first_published":"2026-03-12T15:00:10-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;br\u0026gt;Astera Labs is seeking a \u0026lt;strong\u0026gt;Senior Principal Digital Design Engineer\u0026lt;/strong\u0026gt; to drive the architecture and implementation of next-generation digital designs powering AI infrastructure connectivity. This is a high-impact technical leadership role where you\u0026#39;ll define micro-architecture strategies for better power, performance and area tradeoff, own complex chip-level design decisions, and guide multiple blocks from concept through silicon bring-up for industry-leading products supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As a senior technical leader, you\u0026#39;ll shape design methodologies, mentor engineering teams, and collaborate cross-functionally with verification, physical design, DFT, and post-silicon teams to deliver high-performance, production-quality silicon. You\u0026#39;ll also influence roadmap decisions and drive design excellence across the organization, ensuring Astera Labs continues to set the standard for AI connectivity solutions.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Architecture \u0026amp;amp; Technical Leadership\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Define and drive micro-architecture for complex digital blocks and subsystems across multiple product lines\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Establish architectural standards and best practices that scale across the design organization\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Provide technical guidance and decision-making on critical design trade-offs impacting performance, power, and area\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Design Execution \u0026amp;amp; Ownership\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Lead RTL implementation of complex designs from architecture definition through GDS and silicon bring-up\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive timing constraints and closure strategies and implement robust Design-for-Test (DFT) methodologies\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Own accountability for design quality, schedule, and successful production delivery\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional Collaboration\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Partner with verification teams to develop comprehensive test plans, achieve coverage closure, and debug complex issues\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with physical design, DFT, and post-silicon teams to ensure seamless integration and bring-up\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work with firmware and software teams to optimize hardware-software interfaces\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Mentorship \u0026amp;amp; Process Excellence\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Mentor and develop junior and senior engineers, elevating team technical capabilities\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive continuous improvement of silicon development processes, CAD automation, and design infrastructure\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Contribute to organizational knowledge sharing and technical reviews\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering or equivalent\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;12+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Demonstrated expertise in architecture definition, micro-architecture development, RTL coding, synthesis, and timing closure\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep knowledge of at least one high-speed protocol: PCIe, CXL, Ethernet, DDR, or similar\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Production experience with advanced CMOS nodes (≤7nm)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency with Cadence and/or Synopsys digital design flows\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Track record of delivering multiple high-performance designs to production\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Master\u0026#39;s degree in Electrical Engineering or related field\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with multiple high-speed protocols (PCIe Gen 5/6, CXL, UALink, Ethernet, DDR4/DDR5)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on collaboration with embedded firmware teams and familiarity with RISC-V or Arm subsystems\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven contributions to design methodology, CAD automation, or infrastructure improvements\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience leading technical teams or driving cross-functional initiatives in data center environments\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Salary range is $205,000 to $255,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4687560005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4431679005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":"Program Management","value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Program Management","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4687560005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2473","title":"Senior Principal Engineering Program Manager","company_name":"Astera Labs","first_published":"2026-04-22T19:36:13-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is looking for a \u0026lt;strong\u0026gt;Senior Principal Engineering Program Manager\u0026lt;/strong\u0026gt; to lead end-to-end execution of advanced-node ASIC products from concept through production. This is a high-visibility role with direct accountability for delivering revenue-critical silicon on time, on spec, and at scale.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Program Ownership \u0026amp;amp; Execution\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Own full ASIC lifecycle execution: architecture, RTL, verification, physical design, tapeout, validation, customer sampling, qualification, and RTM\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Serve as the single point of ownership for assigned ASIC programs\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Drive program planning, schedules, budgets, resources, and risk management\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional Leadership \u0026amp;amp; Issue Resolution\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Lead cross-functional teams across design, validation, product, test, firmware, software, and operations\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Resolve complex pre-silicon and post-silicon issues through strong technical judgment\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Stakeholder Management \u0026amp;amp; Alignment\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Manage scope, schedule, and cost trade-offs and communicate clearly with executives and stakeholders\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Champion program execution while aligning engineering delivery with business and customer goals\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;BS or MS in Electrical, Electronics, or Computer Engineering\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;10+ years of ASIC product development experience in a semiconductor environment\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Strong understanding of ASIC development flows, with hands-on experience in RTL, DSP, or Physical Design\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience delivering ASICs in advanced nodes (\u0026amp;lt;10nm)\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Proven ability to lead in a matrixed, high-pressure environment\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Strong program management skills; familiarity with MS Project, Jira, Atlassian tools, Scrum/WBS\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;5 or more years of experience as an ASIC Program Manager\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience with PCIe, memory, or high-speed data communication ASICs\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Salary range is $205,000 to $250,000 depending on experience, level, and business need. This role is eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4043426005,"name":"Program Management","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4739394005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4457205005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Recruiting","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4739394005,"updated_at":"2026-09-30T14:10:59-04:00","requisition_id":"2026-486","title":"Senior Principal Executive Recruiter","company_name":"Astera Labs","first_published":"2026-09-30T14:04:21-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Senior Principal Executive Recruiter\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;The Senior Principal Executive Recruiter will serve as a strategic talent advisor to executive leaders, helping Astera Labs understand its leadership needs before a requisition opens. translate business priorities into proactive executive talent strategies that support the company’s next phase of growth.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Working six or more months ahead of anticipated hiring needs, you will combine semiconductor and silicon market intelligence with a deep understanding of Astera Labs’ organization. This fully in-person role in San Jose will shape how a hyper-growth company builds the leadership capacity required to advance rack-scale AI infrastructure.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Organizational \u0026amp;amp; Executive Talent Strategy\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Partner with executive leaders to understand business priorities, organizational design, and capability gaps across the company.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop rolling six-month executive talent plans that anticipate leadership needs well before roles are formally approved or posted.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Translate business growth plans into clear recommendations on which capabilities, leadership profiles, and talent pools Astera Labs should prioritize.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Market Intelligence \u0026amp;amp; Strategic Advisory\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Analyze semiconductor and silicon talent markets, competitor activity, talent availability, and leadership trends to inform planning.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Partner with stakeholders to surface emerging capability needs, align on future leadership priorities, and shape proactive talent strategies.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Use market insight and organizational context to challenge assumptions, sharpen role definitions, and guide investment in critical talent.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Proactive Executive Pipeline Development\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Build and maintain relationships with high-impact executives well before a requisition opens, creating durable pipelines for future priorities.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop targeted talent maps for engineering and other executive functions across the semiconductor ecosystem.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Create engagement strategies that keep priority talent connected to Astera Labs’ mission, technology, and long-term opportunity.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Executive Partnership \u0026amp;amp; Search Leadership\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Advise senior stakeholders on leadership profiles, assessment criteria, and timing for opening critical roles.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Establish a clear search strategy and decision framework, then guide execution from kickoff through close in alignment with the broader talent plan.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deliver concise executive-level updates that connect talent-market signals, organizational gaps, and recommended actions.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;15+ years of relevant recruiting or talent acquisition experience, including at least 5 years focused on executive recruiting.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Must-have: Proven recruiting experience within the semiconductor, silicon, or adjacent hardware technology industry.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Demonstrated ability to understand organizational priorities, diagnose leadership gaps, and turn business needs into proactive talent plans.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Track record advising VP, C-suite, and other executive-level stakeholders on critical talent decisions.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Demonstrated success closing candidates from Senior Director through C-suite roles, including navigating complex motivations, stakeholders, and offers.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent judgment, discretion, communication skills, and ability to influence senior leaders in a fast-paced environment.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience leading executive talent reviews, succession planning, workforce planning, or organization-design initiatives.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience building talent intelligence frameworks that connect business strategy, capability gaps, market data, and future hiring priorities.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Established long-term relationships with senior leaders across semiconductor, silicon, hardware, systems, or related AI infrastructure markets.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience partnering with CEOs, executive leadership teams, and board-level stakeholders on multi-year leadership planning.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience recruiting across multiple executive functions, including engineering, product, operations, sales, or go-to-market leadership.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot; data-pm-slice=\u0026quot;1 1 []\u0026quot;\u0026gt;Salary range is $190,000 to $240,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184350005,"name":"Talent Acquisition","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4696244005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4436236005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":"Signal Connectivity Group","value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Optical Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4696244005,"updated_at":"2026-09-29T14:26:38-04:00","requisition_id":"2555-1","title":"Senior Principal Photonics Test Engineer","company_name":"Astera Labs","first_published":"2026-05-19T12:23:54-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;div class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Job Summary\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;We are seeking a highly technical and hands-on \u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Senior Principal Photonics Test Engineer\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026amp;nbsp;to serve as the technical authority for photonics test engineering across our product portfolio. This role will define end-to-end test architectures and drive advanced test development for silicon photonics devices, subsystems, and optical modules from early R\u0026amp;amp;D through high-volume manufacturing.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;The ideal candidate brings deep expertise in silicon photonics test methodologies, strong system-level thinking, and a proven ability to solve complex yield and performance challenges while building scalable, automated test solutions.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Define and own the end-to-end test architecture and test roadmap including wafer-level testing, package-level validation, optical engine and module characterization, as well as production and reliability testing.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Lead the development of advanced wafer probe and package-level test solutions for silicon photonics devices and subsystems.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Architect and implement automated test flows for engineering characterization, validation, and production.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Design, develop, and implement optical test plans and procedures for co-packaged optics modules, including silicon photonics engines, laser sources, photodetectors, and optical fiber connectors.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Debug and resolve yield issues and critical technical challenges, including electrical/optical performance failures, process \u0026amp;amp; test induced variations.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Develop and drive the hardware and software roadmap for next-generation optical test systems.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;7\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Collaborate across cross-functional organizations such as silicon and photonics design teams, packaging, validation, reliability and qualification teams.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;8\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Define and implement test and yield analytics frameworks to accelerate yield learning and root cause identification.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;9\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Provide deep technical input in Design-for-Test (DfT) and product development reviews.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;10\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Define test specifications, acceptance criteria, and pass/fail limits based on IEEE, OIF, and internal standards\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Required Qualifications\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;MS or PhD in Electrical Engineering, Optics, Physics, Semiconductor Engineering, or a related field.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;10+ years of experience in optical testing, photonic device characterization, or optical transceiver module test.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Strong understanding of silicon photonics devices (modulators, photodetectors, multiplexers, grating couplers, edge couplers), optical probing and fiber coupling, Electro-Optical (EO) characterization, high-speed optical testing and BER measurement.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Proven experience leading development of wafer-level and package-level optical test systems.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Programming skills in Python, MATLAB, LabVIEW, or C/C++ for test automation\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Knowledge of optical communication standards (IEEE 802.3, OIF-CEI, CMIS)\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;7\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Familiarity with statistical analysis methods and data visualization tools. Strong experience debugging yield issues and complex system-level problems.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;8\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Excellent collaboration and communication skills, with the ability to influence across engineering disciplines.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Preferred Qualifications\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience specifically with co-packaged optics or on-board optics architectures.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Knowledge of 2.5D/3D packaging technologies (interposers, chiplets, UCIe etc.).\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience with external laser source (ELS) integration and characterization.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience with ATE platforms and custom photonics test setups.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience in transitioning test processes from lab/prototype to high-volume manufacturing (HVM)\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Salary range is $185,000 to $240,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/div\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184399005,"name":"Signal Connectivity Group","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4736140005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4455444005,"location":{"name":"Bengaluru, Karnataka, India"},"metadata":[{"id":12122734005,"name":"Country","value":"India","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Bengaluru","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Physical Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4736140005,"updated_at":"2026-09-30T02:22:00-04:00","requisition_id":null,"title":"Senior Principal Physical Design Engineer","company_name":"Astera Labs","first_published":"2026-09-30T02:22:00-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at \u0026lt;a href=\u0026quot;https://cts.businesswire.com/ct/CT?id=smartlink\u0026amp;amp;url=http%3A%2F%2Fwww.asteralabs.com\u0026amp;amp;esheet=53912781\u0026amp;amp;newsitemid=20240319028854\u0026amp;amp;lan=en-US\u0026amp;amp;anchor=www.asteralabs.com\u0026amp;amp;index=1\u0026amp;amp;md5=103150f0c434797e9822ff0eefa9ec61\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;www.asteralabs.com\u0026lt;/strong\u0026gt;\u0026lt;/a\u0026gt;\u0026lt;strong\u0026gt;.\u0026lt;/strong\u0026gt; \u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic qualifications:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE / Computer is required, and a Master’s degree is preferred.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;≥6 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required experience\u0026lt;/strong\u0026gt;:\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Hands-on and thorough knowledge of synthesis, place and route, CTS, extraction timing analysis/STA, Physical Verification and other backend tools and methodologies for technologies 16nm or less, preferably 7nm or less.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven expertise in synthesis, timing closure and formal verification (equivalence) at the block and full-chip level.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Full chip or block level ownership from architecture to GDSII, driving multiple complex designs to production.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with Cadence and/or Synopsys physical design tools/flows.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity and working knowledge of System Verilog/Verilog.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with DFT tools and techniques.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience in working with IP vendors for both RTL and hard-mac blocks.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Good scripting skills in python or Perl\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred :\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Good knowledge of design for test (DFT), stuck-at and transition scan test insertion.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with DFT test coverage and debug.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with ECO methodologies and tools.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p class=\u0026quot;p8i6j01 paragraph\u0026quot;\u0026gt;\u0026lt;br\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184374005,"name":"Physical Design AMS","child_ids":[],"parent_id":null}],"offices":[{"id":4049113005,"name":"Bengaluru","location":"India","child_ids":[],"parent_id":4052109005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4738209005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4456591005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Supply Chain Operations","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4738209005,"updated_at":"2026-09-25T17:57:09-04:00","requisition_id":null,"title":" Senior Principal Program Manager, Business Acceleration ","company_name":"Astera Labs","first_published":"2026-09-25T17:57:09-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;About Astera Labs\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Astera Labs is a global leader in semiconductor-based connectivity solutions that enable AI and cloud infrastructure. Our products help the world\u0026#39;s leading technology companies build scalable, high-performance computing and AI systems.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;We are looking for a technical, high-energy \u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Senior Principal Program Manager, Business Acceleration\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; to help drive execution across some of Astera Labs\u0026#39; most strategically important customer and business initiatives.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;This is a highly visible role that works directly with senior leadership and partners across Sales, Product, Engineering, Field Applications, Supply Chain, and other functions to identify execution gaps, drive accountability, and accelerate business outcomes.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;The Opportunity\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;The ideal candidate is more than a traditional program manager. You are technically credible, highly organized, comfortable operating with senior executives, and willing to relentlessly drive teams toward resolution.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;You will bring structure to complex, cross-functional initiatives across strategic sales opportunities and product development operations involving semiconductor connectivity programs. You will identify blockers, establish clear ownership, track progress, escalate issues, and ensure that critical actions are completed.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Success in this role requires someone who can walk into a room with engineers, product leaders, sales executives, and senior management and quickly understand what roadblocks are in the company\u0026#39;s strategic sales opportunities, ask the right questions, and drive the organization toward action and execution so that those opportunities convert into revenue.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Strategic Business Program Management\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; 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data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Partner with Sales, Product, Engineering, FAE, and other teams to identify blockers, dependencies, and execution risks.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Establish clear action owners, timelines, and follow-through mechanisms.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Track open issues to resolution and proactively escalate stalled or high-impact items.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Develop concise executive-level reporting that clearly communicates progress, risks, blockers, and required leadership actions.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Hold cross-functional stakeholders accountable for commitments and drive timely resolution of critical issues.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Customer \u0026amp;amp; Market Program Intelligence\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Develop and maintain a view of major AI infrastructure buildout programs across key customers and market segments.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Work with Sales, Product Marketing, Product Management, and other teams to understand customer programs, product adoption, competitive dynamics, and whitespace opportunities.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Build customer and market heatmaps that identify where Astera Labs products are deployed today and where future opportunities may exist.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Lead recurring executive readouts on customer program developments and business opportunities.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Business Acceleration \u0026amp;amp; Strategic Planning\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Own programs designed to accelerate growth and close execution gaps against company objectives.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Develop frameworks that connect customer opportunities, product initiatives, and execution priorities to broader business goals.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Partner closely with senior leadership to track progress against strategic objectives.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Identify systemic execution issues and help establish mechanisms to improve organizational responsiveness and accountability.\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Semiconductor \u0026amp;amp; Supply Chain Program Management\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Develop an understanding of semiconductor product development and manufacturing processes, including silicon development, validation, tape-out, foundry, packaging, and production.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Over time, support monitoring of critical semiconductor supply-chain risks and dependencies across foundry, OSAT, substrate, and other key suppliers.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Establish reporting mechanisms to identify emerging supply constraints and risks.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;What You Bring\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline; advanced degree preferred.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Significant experience in \u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;program management, product operations, business acceleration, product management, or a related cross-functional role\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; within the semiconductor, hardware, connectivity, computing, or AI infrastructure industry.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Strong understanding of semiconductor and hardware product development processes.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Ability to understand complex technical issues and communicate them clearly to both technical and executive audiences.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Exceptional PowerPoint skills, with the ability to build clear, executive-ready slide narratives quickly, and demonstrated fluency with AI tools to accelerate analysis, reporting, and communication.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience working across Engineering, Product, Sales, FAE, Operations, and/or Supply Chain organizations.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;7\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Demonstrated ability to manage multiple high-priority initiatives simultaneously and maintain rigorous follow-through.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;8\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Strong analytical, organizational, and executive communication skills.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;9\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience working with semiconductor, connectivity, networking, compute, storage, or AI infrastructure products is highly desirable.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Leadership Characteristics\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;We are looking for someone who:\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Drives accountability\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; rather than simply tracking status.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Is comfortable challenging senior stakeholders and escalating when commitments are not being met.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Has exceptional executive presence and communication skills.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Can operate effectively with incomplete information and rapidly changing priorities.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Is highly persistent and willing to chase down the information needed to move an initiative forward.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Combines technical depth with strong business judgment.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;7\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Thinks like an operator and takes ownership of outcomes.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;8\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Has the potential to grow into broader business or general management leadership.\u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Why This Role Matters\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;This is a highly visible opportunity to work directly with Astera Labs leadership on initiatives that span customers, products, engineering, and the broader business.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;You will have the opportunity to build the operating mechanisms that help Astera Labs execute against its next phase of growth while working at the center of the AI infrastructure ecosystem.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;This role is designed for a high-impact operator who wants to grow beyond traditional program management and take on increasingly broad business leadership responsibilities.\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p8i6j01 paragraph\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p8i6j01 paragraph\u0026quot;\u0026gt;Salary range is $205,000 to $ 260,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184741005,"name":"Procurement \u0026 Business Acceleration (USA_Procurement \u0026 Business Acceleration)","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4696478005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4436346005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":"CTO Office","value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Executive Leadership","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4696478005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2559","title":"Senior Principal Technologist – Memory","company_name":"Astera Labs","first_published":"2026-05-18T14:23:06-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Are you\u0026amp;nbsp;passionate about pushing the boundaries of\u0026amp;nbsp;system,\u0026amp;nbsp;memory,\u0026amp;nbsp;software,\u0026amp;nbsp;and\u0026amp;nbsp;chip\u0026amp;nbsp;architecture? Do you\u0026amp;nbsp;thrive when\u0026amp;nbsp;pitching\u0026amp;nbsp;cutting-edge technology solutions to\u0026amp;nbsp;customers\u0026amp;nbsp;and\u0026amp;nbsp;industry\u0026amp;nbsp;partners? We are seeking\u0026amp;nbsp;a creative customer facing\u0026amp;nbsp;Technologist\u0026amp;nbsp;to help facilitate\u0026amp;nbsp;Astera’s development\u0026amp;nbsp;of\u0026amp;nbsp;data center\u0026amp;nbsp;memory\u0026amp;nbsp;solutions.\u0026amp;nbsp;In this role, you will play a pivotal role in driving the\u0026amp;nbsp;architecture and definition\u0026amp;nbsp;of future products by leveraging your expertise in\u0026amp;nbsp;system architecture,\u0026amp;nbsp;SOC\u0026amp;nbsp;memory sub-system\u0026amp;nbsp;architecture, PCIe/CXL\u0026amp;nbsp;technologies,\u0026amp;nbsp;DRAM/memory architecture,\u0026amp;nbsp;and\u0026amp;nbsp;hardware-software\u0026amp;nbsp;co-design. You will have the opportunity to directly engage with customers,\u0026amp;nbsp;influence product features and roadmap,\u0026amp;nbsp;and help drive innovation to better solve our\u0026amp;nbsp;customers’\u0026amp;nbsp;bottlenecks in hyperscale data centers.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:2,\u0026amp;quot;335559740\u0026amp;quot;:300}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;This role is fully in person, in\u0026amp;nbsp;San Jose.\u0026amp;nbsp;Some travel may be required.\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:2,\u0026amp;quot;335559740\u0026amp;quot;:300}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Basic qualifications\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt; \u0026lt;/span\u0026gt; \u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;BS in Electrical or computer engineering, MS or PhD preferred. \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:2,\u0026amp;quot;335559740\u0026amp;quot;:300}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;≥10 year’s experience developing memory-related solutions and integrating them into systems/racks for data centers\u0026amp;nbsp;\u0026lt;/span\u0026gt; \u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep experience with PCIe 5/6, and CXL including protocol level depth\u0026amp;nbsp; \u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Expertise in OS software integration including memory allocation/management \u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Recent experience with silicon architecture and development especially SOCs with memory controllers (DDR*, LPDDR*, HBM, etc) \u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep expertise and understanding of memory components (DRAM, etc) \u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of datacenter system architecture and design challenges \u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of “full stack” solutions from silicon to application integration \u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience working in a customer-facing role with the ability to articulate technical concepts, influence decision-making, and build business cases \u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ability to dig deeply into technical challenges and use cases\u0026amp;nbsp; \u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent communication and interpersonal skills with the ability to collaborate effectively with internal teams and external partners. \u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Demonstrated leadership capabilities with a track record of driving cross-functional technical initiatives and delivering results in a fast-paced environment. \u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Willingness to travel occasionally for customer meetings and industry events.\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:2,\u0026amp;quot;335559740\u0026amp;quot;:300}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Preferred experience\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt; \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:2,\u0026amp;quot;335559740\u0026amp;quot;:300}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Expertise in\u0026amp;nbsp;JEDEC-defined memory interface specifications\u0026lt;/span\u0026gt; \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;Expertise in memory ECC and error handling \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;Experience in product integration with BIOS, kernel, OS, tooling, and BMCs \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;Experience with board and system design \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;Existing engagement and robust network within industry organizations such as PCI-SIG, OCP, JEDEC, CXL, etc.\u0026amp;nbsp; \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;Hands-on silicon development experience \u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:2,\u0026amp;quot;335559740\u0026amp;quot;:300}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:2,\u0026amp;quot;335559740\u0026amp;quot;:300}\u0026quot;\u0026gt;Salary range is $205,000 to $255,000 depending on experience, level, and business need. This role is eligible for discretionary bonus, incentives and benefits.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184226005,"name":"CTO Office","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4730847005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4452950005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Test Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4730847005,"updated_at":"2026-10-01T13:31:47-04:00","requisition_id":"2026-132","title":"Senior Principal Test Engineer","company_name":"Astera Labs","first_published":"2026-10-01T13:31:47-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;strong data-olk-copy-source=\u0026quot;MessageBody\u0026quot;\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;Astera Labs is seeking a Senior Principal Test Engineer to serve as a technical authority for test engineering across complex mixed-signal silicon and high-speed connectivity products. You will define Test strategies for SCM High Volume Manufacturing and Validation Boards shipped to customer development and own execution from early product engagement through high-volume manufacturing.\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;This role is central to delivering reliable, scalable connectivity for rack-scale AI infrastructure. You will influence product quality, coverage, yield, test cost, and time to market while partnering with design, DFT, product engineering, operations, and manufacturing teams in a fast-moving, hyper-growth environment.\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Test Strategy and Product Ownership\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Define and own comprehensive test strategies, specifications, and plans from product definition through high-volume production.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Establish coverage, quality, yield, test-time, and cost objectives, and drive measurable improvements across the product lifecycle.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Partner with design and product engineering teams to identify testability requirements and make effective design-for-test tradeoffs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Architect tester solutions and guide development of Tester HW design to meet specific and roadmap of products\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Validate Tester Designs and characterize before implementing into Mass Production.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Apply understanding of physical-layer behavior to investigate failures, interpret lab and production data, and resolve complex performance issues.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead root-cause analysis and yield improvement using protocol analyzers, oscilloscopes, manufacturing data, and structured failure analysis.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Technical Leadership and Cross-Functional Execution\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Serve as a senior technical advisor across test, DFT, design, operations, quality, and external manufacturing organizations.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Establish best-known methods, scalable test processes, and automation practices that improve engineering effectiveness and manufacturing readiness.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Mentor engineers, influence technical decisions, and communicate risks, tradeoffs, and recommendations to cross-functional stakeholders.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;12–20 years of experience in Test engineering or Product Engineering from development through high-volume manufacturing.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Strong experience developing custom test solutions for high-speed, mixed-signal products for high volume manufacturing.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Working knowledge of high-speed protocols and physical-layer behavior, including PCIe, Ethernet, DDR, NVMe, or USB.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Experience with Test SW development, production debug, and test-time optimization.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Proven experience developing and designing custom Test Hardware for PCBA High volume manufacturing.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Master’s or PhD in Electrical Engineering, Computer Engineering, or a related field.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Experience with Electrical HW board design on complex Test HW implementation.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong knowledge of DFT techniques such as SCAN, MBIST, SerDes, and functional test, along with control interfaces such as I2C, I3C, SPI, MDIO, and JTAG.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency in C/C++ or Python for ATE programming, data processing, and test automation; familiarity with databases and yield analytics.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Demonstrated ability to provide technical leadership, mentor engineers, influence cross-functional decisions, and deliver results in a fast-paced, high-growth environment.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Proficient in Mandarin Chinese.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;The base salary range is $205,000 USD - $260,000 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184318005,"name":"Manufacturing Test Engineering","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4588342005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4384501005,"location":{"name":"San Jose, CA"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Design Verification","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4588342005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"1837","title":"Senior SoC Verification/Validation Engineer ","company_name":"Astera Labs","first_published":"2025-08-20T13:47:33-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Job Description\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;We are looking for\u0026lt;strong\u0026gt; Senior SoC Verification/Validation Engineer\u0026amp;nbsp;\u0026lt;/strong\u0026gt;who are passionate about bringing next-generation SoCs to life on industry-leading emulation platforms. You will play a critical role in validating complex SoCs for AI connectivity and cloud infrastructure, ensuring functionality and performance well before silicon tape-out.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;span id=\u0026quot;content-1755655491226\u0026quot; class=\u0026quot;fui-Primitive ___1omhnq5 fqtknz5 fyvcxda\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Play a key role in developing complex SOCs for AI connectivity and cloud infrastructures\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Bring up and validate high-speed serial interfaces such as PCIe, Ethernet and UALink, and overall SoC functionality\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate closely with Architecture, Design, Verification,\u0026amp;nbsp;and SW/FW teams to define and execute functional/performance validation plans\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop C/C++ FW and tests to validate and execute all test plan items\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Build tools and methodologies to validate and debug all HW and SW/FW issues on the emulation platform\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Qualification\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;BS/MS in Electrical Engineering, Computer Engineering or related field.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;5+ years of hands-on experience in pre-silicon verification/validation.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong hands-on experience in running and debugging SOC simulation.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Protocol knowledge in high-speed protocols such as PCIe, UALink and/or Ethernet is essential\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency in programming and scripting languages (System Verilog, C/C++, Python)\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong debugging\u0026amp;nbsp;and analytical skills\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent communication skills and ability to\u0026amp;nbsp;work independently with minimal supervision.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Currently based locally or open to relocation.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Experience:\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bring up and validation experience using the industry standard emulation platforms (Palladium or Zebu)\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience in running and debugging SOC simulation and emulation platforms.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;The base salary range is $165,000 USD - $195,000 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4716523005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4445678005,"location":{"name":"Taipei, Taiwan"},"metadata":[{"id":12122734005,"name":"Country","value":"Taiwan","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Taipei","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Procurement","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4716523005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":null,"title":"Senior Sourcing Specialist – Asia Procurement ","company_name":"Astera Labs","first_published":"2026-07-20T09:04:14-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Role Overview\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Astera Labs is seeking a hands-on \u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Senior Sourcing Specialist – Asia Corporate Services \u0026amp;amp; Operations\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; to support sourcing, procurement, supplier management, and purchasing activities across our Asia operations, based in Taipei, Taiwan. This role will support laboratories, engineering infrastructure, capital equipment, facilities, corporate services, and office operations across \u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Taipei, Shanghai, Ho Chi Minh City, and Singapore\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;The ideal candidate will work closely with Engineering, Facilities, IT, Finance, and Business Operations teams to ensure the timely and cost-effective acquisition of equipment, services, and infrastructure required to support Astera Labs\u0026#39; continued growth throughout Asia.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;This position requires strong sourcing and procurement fundamentals, supplier relationship management skills, attention to detail, and the ability to manage multiple projects and purchasing activities in a fast-paced environment. Fluency in both English and Mandarin is required to effectively collaborate with internal stakeholders and regional suppliers.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;A Day in the Life\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;In this role, you\u0026#39;ll work closely with Engineering, Facilities, IT, and site leadership teams across Asia to support the operational needs of rapidly growing offices and laboratories. You will help enable new lab deployments, office expansions, and ongoing site operations by sourcing equipment, managing supplier relationships, issuing purchase orders, and ensuring the timely delivery of goods and services.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Your responsibilities will range from obtaining supplier quotations and coordinating purchases for laboratory equipment and test infrastructure to supporting office build-outs, facility projects, workplace services, and operational expenditures across multiple locations. You\u0026#39;ll collaborate with internal stakeholders and external suppliers to resolve sourcing and procurement challenges, track deliveries, and support business continuity across Astera Labs\u0026#39; regional operations.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;This is a highly collaborative role requiring strong organization, responsiveness, customer service, and the ability to manage multiple sourcing projects simultaneously.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;23\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Support sourcing and procurement activities for Astera Labs operations across \u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Taipei, Shanghai, Ho Chi Minh City, and Singapore\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;23\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Source and purchase laboratory equipment, test infrastructure, facilities equipment, office furnishings, IT hardware, and corporate services.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;23\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Execute RFQs, supplier evaluations, bid comparisons, and commercial negotiations in partnership with internal stakeholders.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;23\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Support supplier selection, contract administration, and purchasing activities across assigned spend categories.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;23\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Develop and maintain relationships with suppliers, contractors, and service providers throughout Asia.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;23\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Partner with Engineering teams to procure lab equipment, tools, test systems, and infrastructure required for product development and validation.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;23\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;7\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Support Facilities teams with office build-outs, site expansions, facility upgrades, furniture purchases, contractor sourcing, and workplace infrastructure projects.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;23\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;8\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Manage purchase requisitions, purchase orders, delivery tracking, invoice resolution, and supplier communications.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;23\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;9\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Coordinate supplier onboarding, documentation collection, and compliance requirements.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;23\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;10\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Monitor supplier performance and support vendor business reviews.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;23\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;11\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Collaborate with Finance and Global Procurement to ensure purchasing activities align with budgets, policies, and company procedures.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;23\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;12\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Identify opportunities for cost savings, supplier improvements, and process efficiencies.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;23\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;13\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Assist with logistics coordination for equipment shipments, imports, exports, and site deliveries when required.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;23\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;14\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Maintain accurate procurement records and ensure compliance with company policies and applicable regulations.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Basic Qualifications\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;24\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Business Administration, Supply Chain Management, Operations, Engineering, or a related field.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;24\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;5–8+ years\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; of experience in sourcing, procurement, purchasing, supply chain, or related functions.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;24\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience sourcing capital equipment, laboratory equipment, facilities-related purchases, technical products, or corporate services.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;24\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience working with suppliers, negotiating pricing, and supporting commercial agreements.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;24\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Familiarity with procurement and ERP systems such as Coupa, Oracle, SAP, or similar platforms.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;24\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Strong organizational and project management skills with the ability to manage multiple priorities.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;24\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;7\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Strong analytical, problem-solving, and communication skills.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;24\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;8\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Fluency in both English and Mandarin (written and spoken) is required.\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;24\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;9\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience working with suppliers and service providers throughout Taiwan and the broader Asia-Pacific region.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Preferred Qualifications\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;25\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience supporting semiconductor, electronics, hardware, laboratory, or engineering organizations.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;25\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience supporting semiconductor R\u0026amp;amp;D labs, validation labs, or engineering development environments.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;25\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Knowledge of supplier markets and sourcing practices across Taiwan and the Asia-Pacific region.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;25\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience supporting laboratory build-outs, office build-outs, facility expansions, or workplace infrastructure projects.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;25\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Familiarity with CapEx procurement and facilities project sourcing.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; 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data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;25\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;8\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;CPSM, CSCP, or similar professional certifications are a plus.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Why Join Us?\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;26\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Be part of a high-growth company advancing the future of AI infrastructure.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;26\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Help support laboratory expansion, office growth, and operational excellence across Asia.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;26\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Partner closely with Engineering, Facilities, IT, and Operations teams on impactful projects.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;26\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Build supplier partnerships that directly support Astera Labs\u0026#39; continued growth.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;26\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Gain exposure to sourcing and procurement activities across multiple international locations.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;26\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Competitive compensation, equity, and benefits.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184383005,"name":"Procurement \u0026 Business Acceleration","child_ids":[],"parent_id":null}],"offices":[{"id":4009035005,"name":"Taipei","location":"Taiwan","child_ids":[],"parent_id":4002874005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4721055005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4447997005,"location":{"name":"Aachen, North Rhine-Westphalia, Germany"},"metadata":[{"id":12122734005,"name":"Country","value":"Germany","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Aachen","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Business Operations","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4721055005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":null,"title":"Senior Sourcing Specialist – Germany Operations \u0026 Manufacturing ","company_name":"Astera Labs","first_published":"2026-08-04T06:45:13-04:00","language":"de","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;About Astera Labs\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) is a pioneering fabless semiconductor company headquartered in Silicon Valley, driving the evolution of AI and cloud infrastructure through purpose-built connectivity solutions. As a leader in rack-scale architecture, Astera Labs is enabling the shift to AI Infrastructure 2.0, where compute is optimized at the rack level to support next-generation workloads.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Our portfolio spans high-performance silicon, software, and system-level solutions that address critical bottlenecks in data movement across compute, memory, and networking domains. We are committed to open standards, continuous innovation, and building a collaborative environment to solve complex challenges\u0026amp;nbsp;at\u0026amp;nbsp;scale.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Role Overview\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Astera Labs is seeking a hands-on\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Senior Sourcing Specialist – Germany Operations \u0026amp;amp; Manufacturing\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026amp;nbsp;to support sourcing and procurement activities for our operations in Aachen, Germany. This role is responsible for supplier management, purchasing operations, commercial negotiations, and procurement support for manufacturing operations, engineering infrastructure, capital equipment, facilities, laboratories, and corporate services. The role will also provide support for materials management and logistics activities as needed to help ensure efficient operation of the Aachen site.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;The ideal candidate will serve as a key sourcing partner for the Aachen site, working closely with Manufacturing, Engineering, Operations, Facilities, Finance, and Global Procurement teams to ensure the timely and cost-effective acquisition of equipment, materials, and services required to support manufacturing operations and site growth.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;The ideal candidate will bring experience supporting\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;optical communications technologies\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;, advanced manufacturing, engineering,\u0026amp;nbsp;laboratory, or other highly technical operating environments. Experience sourcing capital equipment, technical equipment, specialized services, or manufacturing-related products and services is highly desirable.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;This position requires strong sourcing and procurement fundamentals, supplier relationship management skills, attention to detail, and cross-functional collaboration. The successful candidate will help execute sourcing initiatives, support supplier relationships, negotiate pricing and commercial terms, and contribute to procurement process improvements that support Astera Labs\u0026#39; continued growth.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;A Day in the Life\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;In this role, you\u0026#39;ll work closely with Manufacturing, Engineering, Facilities, Quality, Finance, and Operations teams to support a growing production and engineering environment. You will help ensure manufacturing and operational readiness by sourcing critical equipment, managing supplier relationships, obtaining quotations, supporting commercial discussions, and coordinating the procurement of materials and services needed to support day-to-day operations.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Your responsibilities will range from sourcing production capital equipment and manufacturing consumables to supporting facility expansion projects, supplier performance initiatives, and logistics coordination. While the primary focus of this role is sourcing and procurement, you will also assist with materials planning, inventory tracking, and supplier delivery management to help support operational continuity as the Aachen operation continues to scale.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;This is a highly collaborative role requiring strong organization, responsiveness, customer service, and the ability to manage multiple sourcing activities across a diverse group of stakeholders.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;33\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Support sourcing and procurement activities for Astera Labs\u0026#39; Aachen manufacturing and operations site.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;33\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Source and purchase production capital equipment, manufacturing consumables, laboratory equipment, facilities equipment, MRO supplies, IT equipment, and corporate services.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;33\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Execute RFQs, supplier evaluations, bid analyses, and commercial negotiations in partnership with internal stakeholders.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;33\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Support supplier selection, contract administration, and purchasing activities across assigned spend categories.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;33\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Develop and maintain strong relationships with suppliers, contractors, service providers, logistics providers, and equipment vendors.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;33\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Partner with Manufacturing and Engineering teams to procure production equipment, test systems, tooling, spare parts, manufacturing consumables, laboratory equipment, technical equipment, and engineering support services.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;33\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;7\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Source specialized manufacturing equipment, laboratory equipment, automation systems, precision instrumentation, and technical services supporting production and engineering activities.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;33\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;8\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Support Facilities teams with site expansions, facility upgrades, equipment installations, contractor sourcing, and workplace infrastructure projects.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;33\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;9\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Assist with materials planning, inventory monitoring, and supplier delivery coordination to help ensure material availability and continuity of operations.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;33\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;10\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Support logistics coordination, including inbound shipments, freight management, import/export activities, shipment tracking, and supplier delivery performance.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;33\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;11\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Manage purchase requisitions, purchase orders, delivery tracking, and invoice resolution activities.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;33\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;12\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Coordinate supplier onboarding, compliance documentation, and supplier performance reviews.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;33\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;13\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Collaborate with Manufacturing, Finance, Operations, and Global Procurement teams to ensure purchasing activities\u0026amp;nbsp;align\u0026amp;nbsp;with production schedules, budgets, forecasts, and company policies.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;33\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;14\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Identify opportunities for cost savings, supplier improvements, process efficiencies, and operational enhancements.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;33\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;15\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Maintain procurement records and ensure compliance with company policies and applicable regulatory requirements.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Basic Qualifications\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;34\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Supply Chain Management, Business Administration, Operations, Engineering, Logistics, or a related field.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;34\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;5–8+ years\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026amp;nbsp;of experience in sourcing, procurement, purchasing operations, supply chain, manufacturing support, or related functions.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;34\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience sourcing capital equipment, manufacturing consumables, production materials, MRO supplies, laboratory equipment, or technical products and services.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;34\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience negotiating pricing with suppliers and supporting commercial agreements.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;34\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience supporting manufacturing, production, engineering,\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;optical communications\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;, laboratory, or industrial operations.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;34\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Familiarity with ERP and procurement systems such as SAP, Oracle, Coupa, or similar platforms.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;34\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;7\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Working knowledge of materials planning, inventory management, and logistics processes.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;34\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;8\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Strong organizational and project management skills with the ability to manage multiple priorities across stakeholders.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;34\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;9\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Strong analytical, problem-solving, and communication skills.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;34\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;10\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Fluency in both English and German (written and spoken) is required.\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;34\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;11\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience working with suppliers and service providers throughout Germany and Europe.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Preferred Qualifications\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;35\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience supporting\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;optical communications technologies\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;, electronics, advanced manufacturing, laboratory, or engineering organizations.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;35\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience supporting manufacturing operations, research laboratories, product development environments, or other technical operating environments.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;35\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience sourcing specialized manufacturing equipment, production tooling, laboratory equipment, automation systems, cleanroom equipment, or precision manufacturing technologies.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; 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data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;35\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;9\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;CPSM, CSCP, CPIM, or similar professional certifications are a plus.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Why Join Us?\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;36\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Be part of a high-growth company advancing the future of AI infrastructure.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;36\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Help support manufacturing operations, production readiness, and operational excellence in Germany.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;36\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Partner closely with Manufacturing, Engineering, Facilities, and Global Operations teams on impactful business initiatives.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;36\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Build supplier partnerships that directly support Astera Labs\u0026#39; operational success and growth.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;36\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Gain exposure to sourcing, procurement, logistics, and manufacturing support activities within a highly technical environment.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;36\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Contribute to the continued expansion of a growing manufacturing and engineering organization.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;36\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;7\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Competitive compensation, equity, and benefits.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184383005,"name":"Procurement \u0026 Business Acceleration","child_ids":[],"parent_id":null}],"offices":[{"id":4056756005,"name":"Aachen","location":"Germany","child_ids":[],"parent_id":4056755005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4727003005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4450974005,"location":{"name":"Ahmedabad, Gujarat, India"},"metadata":[{"id":12122734005,"name":"Country","value":"India","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Ahmedabad","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Physical Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4727003005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":null,"title":"Senior STA Engineer","company_name":"Astera Labs","first_published":"2026-09-11T02:21:20-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;h1 class=\u0026quot;PDq2pG_selectionAnchorContainer\u0026quot; data-section-id=\u0026quot;l2rpfr\u0026quot; data-start=\u0026quot;0\u0026quot; data-end=\u0026quot;39\u0026quot;\u0026gt;Senior STA Engineer – Job Description\u0026lt;/h1\u0026gt;\n\u0026lt;p data-start=\u0026quot;41\u0026quot; data-end=\u0026quot;163\u0026quot;\u0026gt;\u0026lt;strong data-start=\u0026quot;41\u0026quot; data-end=\u0026quot;54\u0026quot;\u0026gt;Position:\u0026lt;/strong\u0026gt; Senior STA Engineer\u0026lt;br data-start=\u0026quot;74\u0026quot; data-end=\u0026quot;77\u0026quot;\u0026gt;\u0026lt;strong data-start=\u0026quot;77\u0026quot; data-end=\u0026quot;92\u0026quot;\u0026gt;Experience:\u0026lt;/strong\u0026gt; 6+ years\u0026lt;br data-start=\u0026quot;103\u0026quot; data-end=\u0026quot;106\u0026quot;\u0026gt;\u0026lt;strong data-start=\u0026quot;106\u0026quot; data-end=\u0026quot;119\u0026quot;\u0026gt;Location:\u0026lt;/strong\u0026gt; Ahmedabad\u0026lt;br data-start=\u0026quot;130\u0026quot; data-end=\u0026quot;133\u0026quot;\u0026gt;\u0026lt;strong data-start=\u0026quot;133\u0026quot; data-end=\u0026quot;153\u0026quot;\u0026gt;Employment Type:\u0026lt;/strong\u0026gt; Full-time\u0026lt;/p\u0026gt;\n\u0026lt;h3 data-section-id=\u0026quot;1gkutcd\u0026quot; data-start=\u0026quot;165\u0026quot; data-end=\u0026quot;180\u0026quot;\u0026gt;Job Summary\u0026lt;/h3\u0026gt;\n\u0026lt;p data-start=\u0026quot;181\u0026quot; data-end=\u0026quot;519\u0026quot;\u0026gt;We are looking for a \u0026lt;strong data-start=\u0026quot;202\u0026quot; data-end=\u0026quot;225\u0026quot;\u0026gt;Senior STA Engineer\u0026lt;/strong\u0026gt; with strong expertise in Static Timing Analysis, timing signoff, and timing closure for complex ASIC/SoC designs. The candidate will own timing analysis activities across the design flow and work closely with RTL, Synthesis, Physical Design, and Signoff teams to resolve complex timing issues.\u0026lt;/p\u0026gt;\n\u0026lt;h3 data-section-id=\u0026quot;164ueu3\u0026quot; data-start=\u0026quot;521\u0026quot; data-end=\u0026quot;545\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/h3\u0026gt;\n\u0026lt;ul data-start=\u0026quot;546\u0026quot; data-end=\u0026quot;1999\u0026quot;\u0026gt;\n\u0026lt;li data-section-id=\u0026quot;1r7x2uk\u0026quot; data-start=\u0026quot;546\u0026quot; data-end=\u0026quot;642\u0026quot;\u0026gt;Own \u0026lt;strong data-start=\u0026quot;552\u0026quot; data-end=\u0026quot;578\u0026quot;\u0026gt;STA and timing signoff\u0026lt;/strong\u0026gt; activities from synthesis through physical design and tape-out.\u0026lt;/li\u0026gt;\n\u0026lt;li data-section-id=\u0026quot;177s0zq\u0026quot; data-start=\u0026quot;643\u0026quot; data-end=\u0026quot;720\u0026quot;\u0026gt;Perform \u0026lt;strong data-start=\u0026quot;653\u0026quot; data-end=\u0026quot;682\u0026quot;\u0026gt;MCMM/MMMC timing analysis\u0026lt;/strong\u0026gt; across all functional and test modes.\u0026lt;/li\u0026gt;\n\u0026lt;li data-section-id=\u0026quot;17vnu9f\u0026quot; data-start=\u0026quot;721\u0026quot; data-end=\u0026quot;815\u0026quot;\u0026gt;Analyze and debug \u0026lt;strong data-start=\u0026quot;741\u0026quot; data-end=\u0026quot;814\u0026quot;\u0026gt;setup, hold, recovery, removal, min/max, and clock-related violations\u0026lt;/strong\u0026gt;.\u0026lt;/li\u0026gt;\n\u0026lt;li data-section-id=\u0026quot;1ai3568\u0026quot; data-start=\u0026quot;816\u0026quot; data-end=\u0026quot;970\u0026quot;\u0026gt;Develop, review, and validate \u0026lt;strong data-start=\u0026quot;848\u0026quot; data-end=\u0026quot;867\u0026quot;\u0026gt;SDC constraints\u0026lt;/strong\u0026gt;, including clocks, generated clocks, I/O delays, false paths, multicycle paths, and timing exceptions.\u0026lt;/li\u0026gt;\n\u0026lt;li data-section-id=\u0026quot;bevsbq\u0026quot; data-start=\u0026quot;971\u0026quot; data-end=\u0026quot;1102\u0026quot;\u0026gt;Perform detailed \u0026lt;strong data-start=\u0026quot;990\u0026quot; data-end=\u0026quot;1030\u0026quot;\u0026gt;clock tree and clock timing analysis\u0026lt;/strong\u0026gt;, including skew, latency, uncertainty, jitter, and clock reconvergence.\u0026lt;/li\u0026gt;\n\u0026lt;li data-section-id=\u0026quot;168a4rc\u0026quot; data-start=\u0026quot;1103\u0026quot; data-end=\u0026quot;1199\u0026quot;\u0026gt;Drive \u0026lt;strong data-start=\u0026quot;1111\u0026quot; data-end=\u0026quot;1129\u0026quot;\u0026gt;timing closure\u0026lt;/strong\u0026gt; in collaboration with RTL, synthesis, physical design, and ECO teams.\u0026lt;/li\u0026gt;\n\u0026lt;li data-section-id=\u0026quot;fknoyd\u0026quot; data-start=\u0026quot;1200\u0026quot; data-end=\u0026quot;1302\u0026quot;\u0026gt;Analyze critical timing paths and recommend design, synthesis, placement, routing, or ECO solutions.\u0026lt;/li\u0026gt;\n\u0026lt;li data-section-id=\u0026quot;6uo78c\u0026quot; data-start=\u0026quot;1303\u0026quot; data-end=\u0026quot;1426\u0026quot;\u0026gt;Perform timing analysis considering \u0026lt;strong data-start=\u0026quot;1341\u0026quot; data-end=\u0026quot;1425\u0026quot;\u0026gt;OCV/AOCV/POCV, derates, SI/crosstalk, and process-voltage-temperature variations\u0026lt;/strong\u0026gt;.\u0026lt;/li\u0026gt;\n\u0026lt;li data-section-id=\u0026quot;1u8ejn\u0026quot; data-start=\u0026quot;1427\u0026quot; data-end=\u0026quot;1517\u0026quot;\u0026gt;Review timing constraints and methodology to ensure \u0026lt;strong data-start=\u0026quot;1481\u0026quot; data-end=\u0026quot;1516\u0026quot;\u0026gt;signoff-quality timing analysis\u0026lt;/strong\u0026gt;.\u0026lt;/li\u0026gt;\n\u0026lt;li data-section-id=\u0026quot;1qzqer7\u0026quot; data-start=\u0026quot;1518\u0026quot; data-end=\u0026quot;1604\u0026quot;\u0026gt;Support \u0026lt;strong data-start=\u0026quot;1528\u0026quot; data-end=\u0026quot;1543\u0026quot;\u0026gt;timing ECOs\u0026lt;/strong\u0026gt; and evaluate their impact across multiple corners and modes.\u0026lt;/li\u0026gt;\n\u0026lt;li data-section-id=\u0026quot;14jafit\u0026quot; data-start=\u0026quot;1605\u0026quot; data-end=\u0026quot;1713\u0026quot;\u0026gt;Develop and maintain \u0026lt;strong data-start=\u0026quot;1628\u0026quot; data-end=\u0026quot;1653\u0026quot;\u0026gt;Tcl/Python automation\u0026lt;/strong\u0026gt; for STA analysis, report generation, and flow optimization.\u0026lt;/li\u0026gt;\n\u0026lt;li data-section-id=\u0026quot;2q7pk2\u0026quot; data-start=\u0026quot;1714\u0026quot; data-end=\u0026quot;1799\u0026quot;\u0026gt;Debug complex timing issues and provide technical guidance to junior STA engineers.\u0026lt;/li\u0026gt;\n\u0026lt;li data-section-id=\u0026quot;1rocp64\u0026quot; data-start=\u0026quot;1800\u0026quot; data-end=\u0026quot;1888\u0026quot;\u0026gt;Participate in methodology development, flow improvements, and timing signoff reviews.\u0026lt;/li\u0026gt;\n\u0026lt;li data-section-id=\u0026quot;1o8j8uc\u0026quot; data-start=\u0026quot;1889\u0026quot; data-end=\u0026quot;1999\u0026quot;\u0026gt;Coordinate with cross-functional teams to ensure project milestones and \u0026lt;strong data-start=\u0026quot;1963\u0026quot; data-end=\u0026quot;1985\u0026quot;\u0026gt;tape-out schedules\u0026lt;/strong\u0026gt; are achieved.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h3 data-section-id=\u0026quot;akeeu6\u0026quot; data-start=\u0026quot;2001\u0026quot; data-end=\u0026quot;2030\u0026quot;\u0026gt;Required Technical Skills\u0026lt;/h3\u0026gt;\n\u0026lt;ul data-start=\u0026quot;2031\u0026quot; data-end=\u0026quot;2730\u0026quot;\u0026gt;\n\u0026lt;li data-section-id=\u0026quot;1x7tdtf\u0026quot; data-start=\u0026quot;2031\u0026quot; data-end=\u0026quot;2099\u0026quot;\u0026gt;Strong expertise in \u0026lt;strong data-start=\u0026quot;2053\u0026quot; data-end=\u0026quot;2098\u0026quot;\u0026gt;Static Timing Analysis and timing closure\u0026lt;/strong\u0026gt;.\u0026lt;/li\u0026gt;\n\u0026lt;li data-section-id=\u0026quot;1i2njrj\u0026quot; data-start=\u0026quot;2100\u0026quot; data-end=\u0026quot;2191\u0026quot;\u0026gt;Hands-on experience with \u0026lt;strong data-start=\u0026quot;2127\u0026quot; data-end=\u0026quot;2165\u0026quot;\u0026gt;Synopsys PrimeTime, Cadence Tempus\u0026lt;/strong\u0026gt;, or equivalent STA tools.\u0026lt;/li\u0026gt;\n\u0026lt;li data-section-id=\u0026quot;1pgzu10\u0026quot; data-start=\u0026quot;2192\u0026quot; data-end=\u0026quot;2259\u0026quot;\u0026gt;Excellent knowledge of \u0026lt;strong data-start=\u0026quot;2217\u0026quot; data-end=\u0026quot;2258\u0026quot;\u0026gt;SDC constraints and timing exceptions\u0026lt;/strong\u0026gt;.\u0026lt;/li\u0026gt;\n\u0026lt;li data-section-id=\u0026quot;1wqrvkb\u0026quot; data-start=\u0026quot;2260\u0026quot; data-end=\u0026quot;2353\u0026quot;\u0026gt;Strong understanding of \u0026lt;strong data-start=\u0026quot;2286\u0026quot; data-end=\u0026quot;2352\u0026quot;\u0026gt;ASIC/SoC design, synthesis, physical design, and signoff flows\u0026lt;/strong\u0026gt;.\u0026lt;/li\u0026gt;\n\u0026lt;li data-section-id=\u0026quot;dp6e8d\u0026quot; data-start=\u0026quot;2354\u0026quot; data-end=\u0026quot;2392\u0026quot;\u0026gt;Expertise in \u0026lt;strong data-start=\u0026quot;2369\u0026quot; data-end=\u0026quot;2391\u0026quot;\u0026gt;MCMM/MMMC analysis\u0026lt;/strong\u0026gt;.\u0026lt;/li\u0026gt;\n\u0026lt;li data-section-id=\u0026quot;1rs6cru\u0026quot; data-start=\u0026quot;2393\u0026quot; data-end=\u0026quot;2493\u0026quot;\u0026gt;Good understanding of \u0026lt;strong data-start=\u0026quot;2417\u0026quot; data-end=\u0026quot;2492\u0026quot;\u0026gt;OCV/AOCV/POCV, CPPR, SI/crosstalk, derating, and variation-aware timing\u0026lt;/strong\u0026gt;.\u0026lt;/li\u0026gt;\n\u0026lt;li data-section-id=\u0026quot;2jokkc\u0026quot; data-start=\u0026quot;2494\u0026quot; data-end=\u0026quot;2595\u0026quot;\u0026gt;Strong knowledge of clock-domain timing, clock uncertainty, skew, latency, and clock reconvergence.\u0026lt;/li\u0026gt;\n\u0026lt;li data-section-id=\u0026quot;1eqpk46\u0026quot; data-start=\u0026quot;2596\u0026quot; data-end=\u0026quot;2670\u0026quot;\u0026gt;Proficiency in \u0026lt;strong data-start=\u0026quot;2613\u0026quot; data-end=\u0026quot;2630\u0026quot;\u0026gt;Tcl scripting\u0026lt;/strong\u0026gt;; Python/Perl scripting is an advantage.\u0026lt;/li\u0026gt;\n\u0026lt;li data-section-id=\u0026quot;1owq8ci\u0026quot; data-start=\u0026quot;2671\u0026quot; data-end=\u0026quot;2730\u0026quot;\u0026gt;Strong debugging, analytical, and problem-solving skills.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h3 data-section-id=\u0026quot;lodrpc\u0026quot; data-start=\u0026quot;2732\u0026quot; data-end=\u0026quot;2761\u0026quot;\u0026gt;Senior-Level Expectations\u0026lt;/h3\u0026gt;\n\u0026lt;ul data-start=\u0026quot;2762\u0026quot; data-end=\u0026quot;3260\u0026quot;\u0026gt;\n\u0026lt;li data-section-id=\u0026quot;u8kito\u0026quot; data-start=\u0026quot;2762\u0026quot; data-end=\u0026quot;2833\u0026quot;\u0026gt;Ability to \u0026lt;strong data-start=\u0026quot;2775\u0026quot; data-end=\u0026quot;2832\u0026quot;\u0026gt;independently own STA for a block or full-chip design\u0026lt;/strong\u0026gt;.\u0026lt;/li\u0026gt;\n\u0026lt;li data-section-id=\u0026quot;1uizkal\u0026quot; data-start=\u0026quot;2834\u0026quot; data-end=\u0026quot;2923\u0026quot;\u0026gt;Ability to identify root causes of complex timing violations and drive them to closure.\u0026lt;/li\u0026gt;\n\u0026lt;li data-section-id=\u0026quot;37tjb2\u0026quot; data-start=\u0026quot;2924\u0026quot; data-end=\u0026quot;3018\u0026quot;\u0026gt;Ability to interact effectively with \u0026lt;strong data-start=\u0026quot;2963\u0026quot; data-end=\u0026quot;3017\u0026quot;\u0026gt;design, RTL, synthesis, PD, CTS, and signoff teams\u0026lt;/strong\u0026gt;.\u0026lt;/li\u0026gt;\n\u0026lt;li data-section-id=\u0026quot;8p99e4\u0026quot; data-start=\u0026quot;3019\u0026quot; data-end=\u0026quot;3088\u0026quot;\u0026gt;Experience mentoring junior engineers and reviewing their STA work.\u0026lt;/li\u0026gt;\n\u0026lt;li data-section-id=\u0026quot;7nlt1w\u0026quot; data-start=\u0026quot;3089\u0026quot; data-end=\u0026quot;3154\u0026quot;\u0026gt;Strong ownership, communication, and project-management skills.\u0026lt;/li\u0026gt;\n\u0026lt;li data-section-id=\u0026quot;a46flu\u0026quot; data-start=\u0026quot;3155\u0026quot; data-end=\u0026quot;3260\u0026quot;\u0026gt;Ability to work in a fast-paced semiconductor environment and deliver against tight tape-out schedules.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h3 data-section-id=\u0026quot;g9ewcs\u0026quot; data-start=\u0026quot;3262\u0026quot; data-end=\u0026quot;3275\u0026quot;\u0026gt;Education\u0026lt;/h3\u0026gt;\n\u0026lt;p data-start=\u0026quot;3276\u0026quot; data-end=\u0026quot;3374\u0026quot; data-is-last-node=\u0026quot;\u0026quot; data-is-only-node=\u0026quot;\u0026quot;\u0026gt;\u0026lt;strong data-start=\u0026quot;3276\u0026quot; data-end=\u0026quot;3303\u0026quot;\u0026gt;B.E./B.Tech/M.E./M.Tech\u0026lt;/strong\u0026gt; in Electronics, Electrical Engineering, VLSI, or a related discipline.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184232005,"name":"Compute Connectivity Engineering 1","child_ids":[],"parent_id":null}],"offices":[{"id":4065037005,"name":"Ahmedabad","location":"India","child_ids":[],"parent_id":4052109005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4674496005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4425410005,"location":{"name":"Tel Aviv-Yafo, Tel Aviv District, Israel"},"metadata":[{"id":12122734005,"name":"Country","value":"Israel","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Tel Aviv","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":"Silicon Engineering CCE2","value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Design Verification","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4674496005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2374","title":"Senior/ Staff Formal Verification Engineer","company_name":"Astera Labs","first_published":"2026-03-18T12:55:17-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is establishing a strategic R\u0026amp;amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical \u0026#39;data bottlenecks\u0026#39; enabling the future of AI at scale. As we expand our presence in Israel, we\u0026#39;re seeking a visionary \u0026lt;strong\u0026gt;Formal Verification Engineer\u0026lt;/strong\u0026gt; to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the formal verification strategy for chips that power the world\u0026#39;s largest AI clusters.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span class=\u0026quot;TextRun SCXW214065216 BCX0\u0026quot; lang=\u0026quot;EN-US\u0026quot; data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;NormalTextRun SCXW214065216 BCX0\u0026quot;\u0026gt;As the Formal Verification Engineer, you will be a foundational member of our Israel R\u0026amp;amp;D center. You won’t just execute tasks; you will define the\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span class=\u0026quot;TextRun SCXW214065216 BCX0\u0026quot; lang=\u0026quot;EN-US\u0026quot; data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;NormalTextRun SCXW214065216 BCX0\u0026quot;\u0026gt;Formal verification strategy\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span class=\u0026quot;TextRun SCXW214065216 BCX0\u0026quot; lang=\u0026quot;EN-US\u0026quot; data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;NormalTextRun SCXW214065216 BCX0\u0026quot;\u0026gt; for chips that drive the world’s largest AI clusters. You will dive deep into the technical details, proving the correctness of complex designs and ensuring they flawlessly meet specifications.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li style=\u0026quot;text-align: left;\u0026quot; data-path-to-node=\u0026quot;6,0,0\u0026quot;\u0026gt;Own and develop formal verification environments from scratch through to sign-off\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;6,1,0\u0026quot;\u0026gt;Apply formal verification methodologies and strategies to prove the correctness of intricate designs\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;6,2,0\u0026quot;\u0026gt;Work closely with the Architecture, Design, and DV teams to identify verification needs and pinpoint design requirements\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;6,3,0\u0026quot;\u0026gt;Create robust formal environments, analyze complex RTL designs, and apply advanced formal techniques to find corner-case bugs\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;6,4,0\u0026quot;\u0026gt;Analyze verification results, identify failures, and collaborate directly with designers to resolve issues efficiently\u0026lt;/li\u0026gt;\n\u0026lt;li style=\u0026quot;text-align: left;\u0026quot; data-path-to-node=\u0026quot;6,5,0\u0026quot;\u0026gt;Architect and develop generic, common formal functions and properties to be reused across multiple projects\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;8,0,0\u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering or a related technical field\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;8,1,0\u0026quot;\u0026gt;4+ years of hands-on experience in Formal Verification within semiconductor companies\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;8,2,0\u0026quot;\u0026gt;Deep expertise in formal verification methodologies, tools, and flows\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;8,3,0\u0026quot;\u0026gt;Strong understanding of RTL design and verification principles\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;8,4,0\u0026quot;\u0026gt;Experience with industry-standard formal verification tools (Jasper, VC Formal, or similar)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;8,5,0\u0026quot;\u0026gt;Excellent communication skills, strong analytical thinking, and a proactive, \u0026quot;can-do\u0026quot; approach to problem-solving\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;10,0,0\u0026quot;\u0026gt;Track record of successfully taking complex blocks or subsystems through the entire formal verification lifecycle\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;10,1,0\u0026quot;\u0026gt;Experience with SystemVerilog UVM-based design verification\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;10,2,0\u0026quot;\u0026gt;Knowledge of networking standards (Ethernet, NVLink, UALink, PCIe)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;10,3,0\u0026quot;\u0026gt;Background in high-speed serial interface verification\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184339005,"name":"Silicon Engineering CCE2","child_ids":[],"parent_id":null}],"offices":[{"id":4056876005,"name":"Tel Aviv","location":"Israel","child_ids":[],"parent_id":4008937005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4675017005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4425641005,"location":{"name":"Israel"},"metadata":[{"id":12122734005,"name":"Country","value":"Israel","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Tel Aviv","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":"Silicon Engineering CCE2","value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"CAD/EDA Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4675017005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2390","title":"Senior/ Staff Front-End CAD Engineer","company_name":"Astera Labs","first_published":"2026-03-19T11:38:30-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;EOP SCXW38165641 BCX0\u0026quot; data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:160}\u0026quot;\u0026gt;Astera Labs is establishing a strategic R\u0026amp;amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical \u0026#39;data bottlenecks\u0026#39; enabling the future of AI at scale. As we expand our presence in Israel, \u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;we\u0026#39;re seeking a highly skilled\u0026lt;strong\u0026gt; Front-End CAD Engineer\u0026amp;nbsp;\u0026lt;/strong\u0026gt;to join our local engineering powerhouse from the ground up.\u0026lt;/p\u0026gt;\n\u0026lt;p data-path-to-node=\u0026quot;4\u0026quot;\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;As a Front-End CAD Engineer, you will be the backbone of our chip design ecosystem. You won’t just be using tools; you’ll be architecting the methodologies, automation scripts, and design flows that enable our hardware teams to push the limits of silicon performance. Your work directly impacts the productivity of the design team and the time-to-market for our next-generation processors.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;br\u0026gt;Key Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Develop, maintain, and optimize RTL generation tools, building automated IPs and SoC schemes\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Create robust applications using Python and Tcl to automate models build, regression and analysis tools and other assisting tools for all disciplines in front-end flows\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Evaluate and integrate Electronic Design Automation (EDA) tools from vendors like Cadence, Synopsys, and Mentor Graphics\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Define the methodologies of usage and integrate AI tools in this fast-growing field impacting all VLSI development flows\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;br\u0026gt;\u0026lt;/span\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;8,0,0\u0026quot;\u0026gt;Bachelor’s degree in Electrical Engineering or a related technical field\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;8,1,0\u0026quot;\u0026gt;5+ years of hands-on professional experience in relevant industries\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;8,1,0\u0026quot;\u0026gt;Proven experience in\u0026amp;nbsp;\u0026lt;strong\u0026gt;Python\u0026lt;/strong\u0026gt; and \u0026lt;strong\u0026gt;Tcl\u0026lt;/strong\u0026gt; within a Linux/Unix environment\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;8,1,0\u0026quot;\u0026gt;Knowledge and experience in Verilog and/or System Verilog\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;8,1,0\u0026quot;\u0026gt;Very good communication skills\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Preferred Experience\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of the VLSI design cycle, familiarity with clock domain crossing, simulation, debugging, synthesis and timing analysis\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience with industry-standard tools for lint, synthesis, simulation\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with version control systems (Git) and compute cluster management (LSF/SGE)\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184339005,"name":"Silicon Engineering CCE2","child_ids":[],"parent_id":null}],"offices":[{"id":4052111005,"name":"Haifa","location":"Israel","child_ids":[],"parent_id":4008937005},{"id":4056876005,"name":"Tel Aviv","location":"Israel","child_ids":[],"parent_id":4008937005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4674501005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4425414005,"location":{"name":"Israel"},"metadata":[{"id":12122734005,"name":"Country","value":"Israel","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Tel Aviv","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":"Compute Connectivity Engineering 2","value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Layout Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4674501005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2375","title":"Senior/ Staff Package Design Engineer","company_name":"Astera Labs","first_published":"2026-03-18T12:56:50-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is establishing a strategic R\u0026amp;amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical \u0026#39;data bottlenecks\u0026#39; enabling the future of AI at scale. As we expand our presence in Israel, we\u0026#39;re seeking a visionary\u0026amp;nbsp;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Package Design Engineer\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;strong\u0026gt;\u0026amp;nbsp;\u0026lt;/strong\u0026gt;to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, Driving the physical implementation strategy for chips that power the world\u0026#39;s largest AI clusters.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:160}\u0026quot;\u0026gt;As a Package Design Engineer, you will be a core technical contributor in the development of advanced IC packaging solutions for high-performance connectivity silicon. You will execute the package flow, design, and qualification from concept through production, working closely with silicon, signal integrity, power integrity, mechanical, manufacturing, and external OSAT partners. You will be responsible for implementing package technologies that meet aggressive electrical, thermal, mechanical, and cost targets, enabling Astera Labs’ products to operate reliably in the world’s most demanding AI and cloud environments.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,0,0\u0026quot;\u0026gt;Execute end-to-end IC package design, from early feasibility and detailed design through to qualification and high-volume manufacturing\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,1,0\u0026quot;\u0026gt;Implement package architecture and utilize advanced technologies (organic substrates, advanced laminate, interposers, multi-die/chiplet packaging, CoWoS - 2.5D/3D integration)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,2,0\u0026quot;\u0026gt;Drive signal integrity (SI), power integrity (PI), and thermal considerations at the package level for high-speed, high-power devices\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,3,0\u0026quot;\u0026gt;Perform package layout, substrate routing, bump/ball maps, stack-ups, materials selection, and apply mechanical constraints\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,4,0\u0026quot;\u0026gt;Collaborate closely with silicon design, SerDes, system, SI/PI, and reliability teams to optimize overall product performance\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,5,0\u0026quot;\u0026gt;Interface directly with OSATs, substrate vendors, and manufacturing partners to ensure design-for-manufacturability (DFM), yield, and cost targets are met\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,6,0\u0026quot;\u0026gt;Conduct package-related risk assessments, failure analysis, and corrective actions during bring-up and production ramp\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,7,0\u0026quot;\u0026gt;Support NPI, qualification, and product sustainment activities, including vendor technical reviews\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,0,0\u0026quot;\u0026gt;5+ years of hands-on IC package design experience for high-performance semiconductor products, with full technical ownership from concept through tape-out\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,1,0\u0026quot;\u0026gt;Expert proficiency in IC package design tools (Cadence APD / SiP or equivalent) and hands-on experience designing complex packages (BGA, FCBGA, FCCSP)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,2,0\u0026quot;\u0026gt;Strong package integration expertise, including stack-ups, ball/bump maps, constraints, SMT integration, and package BOM ownership\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,3,0\u0026quot;\u0026gt;Deep understanding of signal, power, and thermal integrity at the package level, with the ability to execute design tradeoffs based on analysis\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,4,0\u0026quot;\u0026gt;Proven manufacturing and release experience, including running DRC/LVS/DFM, OSAT engagement, and delivering production-ready package designs\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;11,0,0\u0026quot;\u0026gt;Experience with AI, networking, PCIe, CXL, or other high-speed data center interfaces\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;11,1,0\u0026quot;\u0026gt;Familiarity with package reliability standards and qualification (JEDEC, IPC, thermal cycling, HTOL, etc.)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;11,2,0\u0026quot;\u0026gt;Experience supporting chiplet-based architectures and heterogeneous integration\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;11,3,0\u0026quot;\u0026gt;Demonstrated track record of complete technical package ownership on high-volume products\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184233005,"name":"Compute Connectivity Engineering 2","child_ids":[],"parent_id":null}],"offices":[{"id":4052111005,"name":"Haifa","location":"Israel","child_ids":[],"parent_id":4008937005},{"id":4056876005,"name":"Tel Aviv","location":"Israel","child_ids":[],"parent_id":4008937005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4649866005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4414102005,"location":{"name":"Haifa District, Israel"},"metadata":[{"id":12122734005,"name":"Country","value":"Israel","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Tel Aviv","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":"Physical Design CCE2","value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Physical Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4649866005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2202","title":"Senior/ Staff Physical Design Engineer","company_name":"Astera Labs","first_published":"2026-01-15T19:49:44-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is establishing a strategic R\u0026amp;amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical \u0026#39;data bottlenecks\u0026#39; enabling the future of AI at scale. As we expand our presence in Israel, we\u0026#39;re seeking a visionary\u0026lt;strong\u0026gt;\u0026amp;nbsp;Physical Design Engineer\u0026lt;/strong\u0026gt; to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world\u0026#39;s largest AI clusters.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As a\u0026amp;nbsp;\u0026lt;strong\u0026gt;Physical Design Engineer\u0026lt;/strong\u0026gt;, you will be a key architect of our silicon\u0026#39;s physical reality. You won\u0026#39;t just execute a flow—you will help establish our local execution culture and technical standards, owning the transformation of complex logic into high-performance silicon. You will drive the physical implementation journey from synthesis through signoff, ensuring our connectivity solutions meet the extreme performance, power, and area targets required for next-generation AI infrastructure. If you thrive on solving complex challenges in deep-submicron processes and want to shape the backend methodology for AI infrastructure connectivity, this is your opportunity.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Physical Implementation \u0026amp;amp; Execution\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Be part of the founding Backend team in Israel, playing a critical role in establishing local execution culture and technical standards\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Take full responsibility for physical implementation journey including Synthesis, Floorplanning, Place \u0026amp;amp; Route, and Clock-Tree Synthesis (CTS)\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Own macro-level implementation with deep hands-on experience in floorplanning and complex routing\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Signoff \u0026amp;amp; Design Integrity\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Drive final stages of design integrity, owning Timing signoff (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR)\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Ensure first-pass silicon success through rigorous signoff flows and analysis\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Apply Logic Equivalence Checking (LEC) and other verification techniques to guarantee design correctness\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Methodology Development \u0026amp;amp; Cross-Functional Collaboration\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Participate in defining and refining Backend methodologies with autonomy to improve workflows and tool automation\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Work closely with Architecture, Design, and DFT teams to navigate challenges of advanced process nodes and high-speed connectivity\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Leverage scripting and automation to make engineering environment faster and more robust\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering or related technical field\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;3+ years of hands-on experience in Physical Design at semiconductor companies\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Proven expertise in the full RTL2GDS flow with deep hands-on experience in macro-level implementation, floorplanning, and complex routing\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience working with advanced process technologies (7nm and below)\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Solid experience with signoff tools and flows including STA, Logic Equivalence Checking (LEC), DRC, and EMIR analysis\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Proficiency in TCL or Python scripting to drive EDA tool flows and automate repetitive tasks\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience with full-chip level implementation and integration\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Knowledge of Power and Noise analysis (SI/PI) to optimize high-performance silicon\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Familiarity with Design-for-Test (DFT) requirements and their impact on physical layout\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience with industry-standard EDA tools (Synopsys Fusion Compiler/ICC2, Cadence Innovus)\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Background in high-speed interface designs or connectivity protocols\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184376005,"name":"Physical Design CCE2","child_ids":[],"parent_id":null}],"offices":[{"id":4056876005,"name":"Tel Aviv","location":"Israel","child_ids":[],"parent_id":4008937005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4734437005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4449204005,"location":{"name":"Tel Aviv-Yafo, Tel Aviv District, Israel"},"metadata":[{"id":12122734005,"name":"Country","value":"Israel","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Tel Aviv","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"System Validation","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4734437005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":null,"title":"Senior System Validation Engineer","company_name":"Astera Labs","first_published":"2026-09-16T03:50:31-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;strong data-olk-copy-source=\u0026quot;MessageBody\u0026quot;\u0026gt;Senior System Validation Engineer\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with\u0026amp;nbsp;hyperscalers\u0026amp;nbsp;and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet,\u0026amp;nbsp;NVLink, PCIe®, and\u0026amp;nbsp;UALink™ technologies with the company’s COSMOS software suite to enable scalable, high-performance AI infrastructure. Discover more at\u0026amp;nbsp;\u0026lt;a id=\u0026quot;OWA1d3a285d-f092-710c-9443-4856a949c8ea\u0026quot; href=\u0026quot;https://nam02.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.asteralabs.com%2F\u0026amp;amp;data=05%7C02%7CGili.Neuman%40asteralabs.com%7C9c22a8a76b544a0127ed08df12f3fa29%7Cf47c88fd08a94016b4883f361c03ff2e%7C0%7C0%7C639250511223132752%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C\u0026amp;amp;sdata=E5o%2F2Jk1hYGW7AkhtrbaiF%2FbthbTmKer1cJS8vWE9eQ%3D\u0026amp;amp;reserved=0\u0026quot; data-auth=\u0026quot;NotApplicable\u0026quot; data-linkindex=\u0026quot;0\u0026quot;\u0026gt;\u0026lt;u\u0026gt;www.asteralabs.com\u0026lt;/u\u0026gt;\u0026lt;/a\u0026gt;.\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;strong\u0026gt;Overview:\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;Astera Labs is seeking a motivated Senior System Validation Engineer to join our growing post-silicon validation team in Israel and support next-generation connectivity products for AI and data-center\u0026amp;nbsp;applications.\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;In this role, you will perform system-level post-silicon validation, characterization, and debug across silicon, hardware, firmware, and software. You will support silicon bring-up and PVT/corner testing, develop and execute functional and system validation tests,\u0026amp;nbsp;analyze\u0026amp;nbsp;results, and work with cross-functional teams to identify and resolve complex system issues.\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;This is a highly hands-on lab position. The primary location is\u0026amp;nbsp;\u0026lt;strong\u0026gt;Haifa\u0026lt;/strong\u0026gt;, with temporary support at the\u0026amp;nbsp;\u0026lt;strong\u0026gt;Ramat Gan\u0026lt;/strong\u0026gt;\u0026amp;nbsp;lab as needed.\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities:\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Develop and execute post-silicon functional and system validation from silicon bring-up through production readiness.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Run PVT, silicon corner, stress, characterization, and qualification testing across a wide range of operating conditions.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Develop validation tests to verify functionality, performance, stability, power, and operating margins.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Debug issues across silicon, hardware, firmware, drivers, and system software.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Validate high-speed interfaces such as PCIe, CXL, Ethernet/SerDes, and DDR, as well as common system interfaces.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Develop Python scripts and automation to improve validation coverage, regression, and test efficiency.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Analyze\u0026amp;nbsp;validation data, identify issues and trends, and drive problems to root cause and closure.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Work closely with hardware, architecture, firmware, software, design, and DV teams to investigate and resolve issues.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Support the transition of new silicon from initial bring-up to a qualified, production-ready product.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Operate system platforms and laboratory equipment to support validation and debug.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Document test results, issues, root cause, and recommendations and communicate findings clearly.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications:\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, Computer Science, or a related field.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;6+ years of experience in post-silicon, system, hardware, or product validation.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Hands-on experience with SoC/silicon bring-up, functional validation, and system-level debug.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Experience developing and executing validation plans, test cases, and characterization experiments.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Strong Python scripting and test automation skills.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Strong hardware debugging, analytical, and problem-solving skills with the ability to work independently.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Experience debugging issues across hardware, firmware, and software.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Experience validating high-speed interfaces such as PCIe, Ethernet, SerDes, CXL, or DDR.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Hands-on experience working in a hardware or system validation laboratory.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Strong communication and cross-functional collaboration skills.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications:\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Experience with PVT validation, silicon corner testing, characterization, qualification, and margin analysis.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Experience with server, storage, networking, or AI infrastructure products.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Familiarity with PCIe/CXL architecture and high-speed SerDes technologies.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Experience with oscilloscopes,\u0026amp;nbsp;BERTs, protocol\u0026amp;nbsp;analyzers, traffic generators, or similar lab equipment.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Working knowledge of Python, firmware, Linux, and system-level software debugging.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Experience developing automated validation and regression environments.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Familiarity with Git and software development practices.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Experience with pre-silicon validation, emulation, or hardware prototyping.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Experience with system performance, throughput, latency, power, and stability testing.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184348005,"name":"System Validation CCE2","child_ids":[],"parent_id":null}],"offices":[{"id":4052111005,"name":"Haifa","location":"Israel","child_ids":[],"parent_id":4008937005},{"id":4056876005,"name":"Tel Aviv","location":"Israel","child_ids":[],"parent_id":4008937005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4723176005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4449037005,"location":{"name":"Vancouver, British Columbia, Canada"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Product Management","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4723176005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":null,"title":"Senior Tools Development Engineer – COSMOS Platform Software","company_name":"Astera Labs","first_published":"2026-08-11T18:59:22-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p8i6j01 paragraph\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;PDq2pG_selectionAnchorContainer\u0026quot; data-start=\u0026quot;834\u0026quot; data-end=\u0026quot;1357\u0026quot;\u0026gt;We are looking for a \u0026lt;strong data-start=\u0026quot;855\u0026quot; data-end=\u0026quot;892\u0026quot;\u0026gt;Senior Tools Development Engineer\u0026lt;/strong\u0026gt; to help shape the future of \u0026lt;strong data-start=\u0026quot;921\u0026quot; data-end=\u0026quot;931\u0026quot;\u0026gt;COSMOS\u0026lt;/strong\u0026gt;, Astera Labs\u0026#39; unified platform software. In this role, you\u0026#39;ll build the tools that customers and engineers rely on every day to configure, monitor, debug, and validate Astera Labs products. You\u0026#39;ll work at the intersection of software, hardware, and systems engineering—creating intuitive applications, command-line utilities, automation frameworks, and infrastructure that improve developer productivity and customer success.\u0026lt;/p\u0026gt;\n\u0026lt;p data-start=\u0026quot;1359\u0026quot; data-end=\u0026quot;1538\u0026quot;\u0026gt;If you enjoy building high-quality software, solving complex engineering problems, and developing tools that bridge applications, systems, and silicon, we\u0026#39;d love to hear from you.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p8i6j01 paragraph\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p8i6j01 paragraph\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;COSMOS\u0026lt;/strong\u0026gt;, Astera Labs\u0026#39; unified platform software. In this role, you\u0026#39;ll build the tools that customers and engineers rely on every day to configure, monitor, debug, and validate Astera Labs products. You\u0026#39;ll work at the intersection of software, hardware, and systems engineering—creating intuitive applications, automation frameworks, and infrastructure that improve developer productivity and customer success.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;If you enjoy building high-quality software, solving complex engineering problems, and working across multiple programming languages and technologies, we\u0026#39;d love to talk to you.\u0026lt;/p\u0026gt;\n\u0026lt;h2\u0026gt;What You\u0026#39;ll Do\u0026lt;/h2\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Design, develop, and maintain \u0026lt;strong\u0026gt;COSMOS Explorer\u0026lt;/strong\u0026gt; (GUI) and \u0026lt;strong\u0026gt;COSMOS CLI\u0026lt;/strong\u0026gt;, the primary software interfaces for configuring, monitoring, and debugging Astera Labs products.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop desktop applications, command-line utilities, and automation tools using \u0026lt;strong\u0026gt;C#, C, C++, and Python\u0026lt;/strong\u0026gt;.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Build software that communicates directly with Astera Labs silicon to enable telemetry, diagnostics, validation, and product configuration.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Design reusable frameworks and utilities that improve engineering productivity and simplify product bring-up and debug.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Create automated testing and validation tools that improve software quality, reduce manual effort, and accelerate product releases.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Leverage modern AI-assisted development tools to improve developer productivity, automate repetitive tasks, and accelerate test creation where appropriate.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Debug complex software and system-level issues spanning applications, firmware, drivers, and hardware platforms.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Write clean, maintainable, and well-documented code while participating in peer code reviews.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate closely with firmware, hardware, validation, and product engineering teams to define new platform capabilities.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Help shape the evolution of the COSMOS software platform through technical leadership and continuous improvement.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;hr\u0026gt;\n\u0026lt;h2\u0026gt;Basic Qualifications\u0026lt;/h2\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor\u0026#39;s or Master\u0026#39;s degree in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;5+ years of professional software development experience.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong programming experience in several of the following:\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;C#\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;C\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;C++\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Python\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience developing modern object-oriented software applications.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong debugging and problem-solving skills.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent written and verbal communication skills.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ability to thrive in a fast-paced, collaborative engineering environment.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;hr\u0026gt;\n\u0026lt;h2\u0026gt;Preferred Qualifications\u0026lt;/h2\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience developing desktop applications using technologies such as:\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Avalonia\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;WPF\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;MAUI\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;WinUI\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Qt\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience building software tools, SDKs, utilities, or developer productivity applications.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience designing automation frameworks and test infrastructure.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with Git, CI/CD workflows, and modern software engineering practices.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience working with Windows and Linux environments.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with AI-assisted software development tools such as GitHub Copilot, ChatGPT, Cursor, Claude Code, or similar productivity tools.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;hr\u0026gt;\n\u0026lt;h2\u0026gt;Nice to Have\u0026lt;/h2\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience communicating with hardware devices over PCIe, Ethernet, USB, I²C, SPI, or similar interfaces.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with lab equipment such as oscilloscopes, protocol analyzers, or traffic generators.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with server architecture, storage systems, networking equipment, or AI infrastructure.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Exposure to firmware, embedded software, device drivers, or silicon validation.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of PCIe®, CXL®, Ethernet, or other high-speed interconnect technologies.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p class=\u0026quot;p8i6j01 paragraph\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;The base pay range for this role is between $165,000 and $210,000. Your actual base pay will depend on factors such as your background, qualifications, and experience.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4000702005,"name":"Product Applications","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4003931005,"name":"Vancouver","location":"Canada","child_ids":[],"parent_id":4004709005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4735007005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4455066005,"location":{"name":"Bengaluru, Karnataka, India"},"metadata":[{"id":12122734005,"name":"Country","value":"India","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Bengaluru","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Digital Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4735007005,"updated_at":"2026-10-05T10:37:32-04:00","requisition_id":null,"title":"Silicon Design Architect","company_name":"Astera Labs","first_published":"2026-09-22T05:46:03-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;h2\u0026gt;\u0026lt;span style=\u0026quot;text-decoration: underline;\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Silicon Digital Architect - I\u0026lt;/strong\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span style=\u0026quot;text-decoration: underline;\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;P / Subsystem\u0026lt;/strong\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/h2\u0026gt;\n\u0026lt;h2\u0026gt;\u0026amp;nbsp;\u0026lt;/h2\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Experience- \u0026lt;/strong\u0026gt;\u0026lt;strong\u0026gt;20+ years\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Job Summary\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;We are looking for an experienced \u0026lt;strong\u0026gt;IP/Subsystem Architect\u0026lt;/strong\u0026gt; to define the architecture and technical direction of complex semiconductor IPs and subsystems. The candidate will own architecture definition from requirements through implementation, working closely with SoC, RTL, verification, physical design, firmware, and system teams.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Define architecture for complex \u0026lt;strong\u0026gt;IP blocks and SoC subsystems\u0026lt;/strong\u0026gt; based on product and system requirements.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Translate system requirements into architecture, specifications, interfaces, and performance targets.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Define microarchitecture, data paths, control paths, interfaces, clocking, reset, power, and error-handling mechanisms.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Evaluate architectural trade-offs across \u0026lt;strong\u0026gt;performance, power, area, latency, bandwidth, scalability, and complexity\u0026lt;/strong\u0026gt;.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Define interfaces and protocols such as \u0026lt;strong\u0026gt;PCIe, UALink, AXI, APB, CHI, or other high-speed/interconnect protocols\u0026lt;/strong\u0026gt;.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop architecture specifications, block diagrams, interface specifications, and technical documentation.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work closely with RTL, verification, physical design, DFT, firmware, and system architecture teams.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Identify architectural risks and drive resolution of complex technical issues.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Review RTL and verification strategies to ensure implementation aligns with architectural intent.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Provide technical leadership and mentorship to senior/principal engineers.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive architecture reviews and communicate technical decisions to engineering leadership.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Skills\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong background in \u0026lt;strong\u0026gt;IP architecture and microarchitecture\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Background in ASIC/SoC architecture and microarchitecture is a big plus.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of digital design, computer architecture, memory systems, interconnects, and SoC design.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with high-speed interfaces and/or coherent interconnects.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of \u0026lt;strong\u0026gt;performance modeling, bandwidth, latency, and system-level trade-offs\u0026lt;/strong\u0026gt;.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent technical communication and problem-solving skills.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience with \u0026lt;strong\u0026gt;PCIe, UALink, CXL, Ethernet, CCIX, CHI\u0026lt;/strong\u0026gt;, or similar technologies.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with AI/accelerator, networking, compute, or high-performance SoC architectures.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience taking IP/subsystems from architecture through silicon production.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184256005,"name":"Design Engineering CCE2","child_ids":[],"parent_id":null}],"offices":[{"id":4049113005,"name":"Bengaluru","location":"India","child_ids":[],"parent_id":4052109005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4701820005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4438688005,"location":{"name":"Tel Aviv-Yafo, Tel Aviv District, Israel"},"metadata":[{"id":12122734005,"name":"Country","value":"Israel","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Tel Aviv","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Program Management","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4701820005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2608","title":"Silicon Technical Program Manager ","company_name":"Astera Labs","first_published":"2026-06-02T14:13:13-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is establishing a strategic R\u0026amp;amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical \u0026#39;data bottlenecks\u0026#39; enabling the future of AI at scale. As we expand our presence in Israel, we\u0026#39;re seeking a visionary \u0026lt;strong\u0026gt;Silicon Technical Program Manager\u0026amp;nbsp;\u0026amp;nbsp;\u0026lt;/strong\u0026gt;to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, leading the physical implementation strategy for chips that power the world\u0026#39;s largest AI clusters.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p data-path-to-node=\u0026quot;3\u0026quot;\u0026gt;As an\u0026amp;nbsp;Technical Program Manager, you will be the key architect of our silicon’s operational reality. You won’t just track timelines - you will help establish our local execution culture and technical standards, owning the cross-functional journey of transforming complex logic into high-performance silicon.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul type=\u0026quot;disc\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;x_MsoNormal\u0026quot;\u0026gt;Drive and manage ASIC development and subsystems from concept through to production in collaboration with internal teams and external vendors.\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_MsoNormal\u0026quot;\u0026gt;Provide hands-on program management throughout the full development cycle of silicon and firmware, including concept, design, development, fabrication, validation, and production release.\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_MsoNormal\u0026quot;\u0026gt;Work closely with the software, hardware, and architecture teams to align with product requirements and ensure all constraints are met.\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_MsoNormal\u0026quot;\u0026gt;Lead process improvements across multiple teams and functions to drive better collaboration and efficiency.\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_MsoNormal\u0026quot;\u0026gt;Independently manage complex projects with minimal supervision, ensuring timelines and milestones are met.\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_MsoNormal\u0026quot;\u0026gt;Deliver high-quality ASIC solutions products while collaborating with product management and architecture teams.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul type=\u0026quot;disc\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;x_MsoNormal\u0026quot;\u0026gt;\u0026lt;span data-olk-copy-source=\u0026quot;MessageBody\u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Computer Science, Electrical Engineering, or a related technical field\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_MsoNormal\u0026quot;\u0026gt;8+ years of experience in ASIC development and 3+ years in Program or Product Management or Technical/Engineering management\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_MsoNormal\u0026quot;\u0026gt;Proven leadership skills, with the ability to manage projects from technical details to the big picture\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_MsoNormal\u0026quot;\u0026gt;Experience in managing ASIC design flow, RTL, synthesis, functional verification, and physical layout\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_MsoNormal\u0026quot;\u0026gt;Experience in pre-silicon testing (Emulation, FPGA) and post-silicon validation is preferred\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_MsoNormal\u0026quot;\u0026gt;Excel in interpersonal communication, relationship building, and collaboration within cross-functional teams\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_MsoNormal\u0026quot;\u0026gt;Excellent organizational and leadership skills, and are capable of multitasking in a fast-paced environment\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul type=\u0026quot;disc\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;x_MsoNormal\u0026quot;\u0026gt;\u0026lt;span data-olk-copy-source=\u0026quot;MessageBody\u0026quot;\u0026gt;Familiarity with Networking technologies and concepts\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_MsoNormal\u0026quot;\u0026gt;Excellent strategic planning and communication skills, with a self-motivated focus on execution\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4043426005,"name":"Program Management","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4056876005,"name":"Tel Aviv","location":"Israel","child_ids":[],"parent_id":4008937005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4730791005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4452912005,"location":{"name":"Shanghai Shi, China"},"metadata":[{"id":12122734005,"name":"Country","value":"China","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Shanghai","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Recruiting","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4730791005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":null,"title":"Site HR China","company_name":"Astera Labs","first_published":"2026-09-08T01:08:55-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Job Summary:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;The Site Human Resources Manager will oversee and manage all HR activities at the designated sites. This includes providing strategic HR support, ensuring compliance with labor laws, managing employee relations, administering compensation and benefits programs, and facilitating recruitment and training efforts. The Site HR Manager will work closely with site leadership and employees to foster a positive work environment and ensure that HR operations align with company goals and objectives.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Site HR Administration:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Maintain accurate employee records, ensure proper documentation, and track certifications, licenses, and other compliance-related activities.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Manage site employee database attendance, leave of absence, and scheduling requests.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ensure compliance with local, state, and federal labor laws and regulations.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work with site leadership to maintain a safe and healthy work environment, ensuring adherence to health and safety regulations.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support wellness initiatives to promote employee well-being and work-life balance.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Promote and sustain a positive site culture in alignment with company values.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Plan and organize site events or initiatives to improve employee morale and foster team spirit.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Oversee the administration of compensation and benefits programs for all employees at the site.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ensure that employees understand their benefits options and provide guidance on payroll, benefits, and other compensation-related inquiries.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support any HR-related projects, initiatives, or company-wide programs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Partner with HR counterparts to drive global initiatives\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Recruitment \u0026amp;amp; Onboarding:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Oversee the recruitment process, including job postings, strategy, interviewing, and hiring for all site positions.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ensure smooth and efficient onboarding of new employees, including training on company policies, benefits, and site-specific procedures.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Employee Relations:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Serve as the first point of contact for employees regarding HR-related issues, concerns, and grievances.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Foster positive employee relations and ensure a high level of employee engagement.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Mediate disputes and resolve conflicts in a fair and consistent manner.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;HR Reporting \u0026amp;amp; Analytics:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Track and report on key HR metrics, such as attrition, absenteeism, training completion, and employee satisfaction.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Provide regular updates to leadership on HR-related activities, challenges, and opportunities.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Qualifications\u0026lt;/strong\u0026gt;:\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Education: Masters degree in Human Resources, Business Administration, or related field.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience: Minimum 10 years of experience in Human Resources, ideally with some experience in a multinational/US organisations\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Skills\u0026lt;/strong\u0026gt;:\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong knowledge of labor laws and HR best practices.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent interpersonal, communication, and conflict resolution skills.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ability to work independently and manage multiple priorities.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency in HRIS systems, Microsoft Office Suite, and other HR-related tools.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Working Conditions:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;May require occasional travel to other company sites or locations.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Must be flexible to work on-site and available during business hours, with occasional after-hours support as needed.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184292005,"name":"HRBP APAC","child_ids":[],"parent_id":null}],"offices":[{"id":4002878005,"name":"Shanghai","location":"Shanghai, China","child_ids":[],"parent_id":4002875005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4706987005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4441178005,"location":{"name":"Bengaluru, Karnataka, India"},"metadata":[{"id":12122734005,"name":"Country","value":"India","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Bengaluru","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":"Design Engineering CCE2","value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Digital Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4706987005,"updated_at":"2026-10-06T13:26:35-04:00","requisition_id":"2652","title":"SoC Design Director","company_name":"Astera Labs","first_published":"2026-06-29T00:00:10-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Job Title: SoC Design Manager\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;About the Role\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;We are seeking an experienced and highly motivated SoC Design Manager to lead a team of engineers responsible for the design and development of next-generation System-on-Chip (SoC) solutions. The ideal candidate will possess strong technical expertise in digital design, excellent leadership skills, and a proven track record of delivering complex SoC projects from architecture through silicon.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Roles \u0026amp;amp; Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Technology Background\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;9\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience of working on complex, large SoCs on latest technology nodes under tight schedules. Exposure to chiplets is desirable.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;9\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Expertise around handling chip level design challenges around clocking, resets, power domains/distribution is a must\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;9\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience of working with DFT, PD, DV teams to solve critical technical challenges of cross-domain nature\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;9\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience of working on PCIE, UCIE, UALink, Ethernet products is highly desirable.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;9\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Must have working knowledge of embedded processors and firmware execution to enable key SoC level features\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;SoC Design \u0026amp;amp; Development\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;10\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Own the design and development of SoC subsystems from specification through RTL implementation.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;10\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Review architecture and microarchitecture specifications and translate them into efficient design solutions.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;10\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Oversee RTL coding, integration, and design reviews to ensure quality and compliance with design standards.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;10\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Drive design closure while meeting performance, power, area, and schedule targets.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Project Execution\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;11\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Define project plans, resource allocation, and execution timelines.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;11\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Track deliverables and ensure milestones are met on schedule.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;11\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Identify technical and program risks and implement mitigation plans.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;11\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Provide regular status updates to leadership and key stakeholders.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Cross-Functional Collaboration\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;12\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Work closely with Architecture, Verification, DFT, Physical Design, Firmware, and Software teams throughout the development cycle.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;12\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Support verification planning and debug activities to ensure robust design quality.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;12\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Collaborate with implementation teams to address synthesis, timing, power, and integration challenges.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Quality \u0026amp;amp; Process Improvement\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;13\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Establish and enforce design methodologies, coding guidelines, and best practices.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;13\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Drive continuous improvement in design processes, productivity, and quality metrics.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;13\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Ensure designs meet functional, performance, and reliability requirements.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Silicon Bring-Up \u0026amp;amp; Product Support\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;14\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Support post-silicon validation, debug, and product qualification activities.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;14\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Assist in root-cause analysis and resolution of silicon issues when required.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;14\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Provide technical leadership for future product enhancements and next-generation designs.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Team Leadership \u0026amp;amp; Management\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;14\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Lead, mentor, and manage a team of SoC/RTL design engineers.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;14\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Drive team performance, career development, and succession planning.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;14\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Participate in hiring and onboarding of new team members.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;14\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;7\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Foster a collaborative and high-performance engineering culture.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Required Qualifications\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Bachelor\u0026#39;s or Master\u0026#39;s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;15+ years of experience in ASIC/SoC design and development.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;5+ years of experience leading engineering teams or technical projects.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Strong expertise in RTL design using Verilog/SystemVerilog.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience with SoC integration, interconnects, memory subsystems, and industry-standard protocols such as AXI, AHB, APB, PCIe, \u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;USB\u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;UALink\u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;, Ethernet, or DDR.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; 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data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559682\u0026amp;quot;:6,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Knowledge of low-power design techniques and clock/reset architectures.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559682\u0026amp;quot;:6,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience with scripting languages such as Python, Perl, or Tcl.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559682\u0026amp;quot;:6,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Prior experience delivering multiple successful tape-outs.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559682\u0026amp;quot;:6,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience managing globally distributed engineering teams.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184256005,"name":"Design Engineering CCE2","child_ids":[],"parent_id":null}],"offices":[{"id":4049113005,"name":"Bengaluru","location":"India","child_ids":[],"parent_id":4052109005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4703985005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4439735005,"location":{"name":"Bengaluru, Karnataka, India"},"metadata":[{"id":12122734005,"name":"Country","value":"India","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Bengaluru","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":"Design Verification CCE2","value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Design Verification","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4703985005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2629","title":"Soc Design Verification Director ","company_name":"Astera Labs","first_published":"2026-06-24T08:27:38-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;h2\u0026gt;Job Title: Director of SoC Design Verification\u0026lt;/h2\u0026gt;\n\u0026lt;h3\u0026gt;Overview\u0026lt;/h3\u0026gt;\n\u0026lt;p\u0026gt;We are seeking a seasoned Director of SoC Design Verification with \u0026lt;strong\u0026gt;20+ years of experience\u0026lt;/strong\u0026gt; to lead verification for our next-generation System-on-Chip products. This is a hands-on leadership role where you will define the SoC-level verification strategy, oversee execution across multiple IPs and subsystems, and ensure first-pass silicon success for complex designs in compute, networking, and storage domains.\u0026lt;/p\u0026gt;\n\u0026lt;h3\u0026gt;Key Responsibilities\u0026lt;/h3\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Own and drive the end-to-end SoC verification methodology, ensuring seamless integration of IP-level verification into system-level environments.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead, mentor, and grow a diverse team of engineers, fostering technical excellence, innovation, and collaboration.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Guide verification of complex SoC subsystems including \u0026lt;strong\u0026gt;HSIO, peripherals, interconnects, memory controllers, coherency fabrics, and system-level protocols\u0026lt;/strong\u0026gt;.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Champion advanced methodologies (UVM, formal verification, emulation, AI-augmented flows) to accelerate coverage closure and improve efficiency.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate closely with RTL design, architecture, firmware, and validation teams to debug, refine, and optimize SoC-level verification processes.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Represent verification in executive reviews, customer engagements, and industry forums.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Shape workforce transformation by building hybrid skill sets and preparing the team for AI-driven verification challenges.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h3\u0026gt;Qualifications\u0026lt;/h3\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s degree in Electrical or Computer Engineering (Master’s preferred).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;20+ years of experience\u0026lt;/strong\u0026gt; in design verification, with a proven track record of leading teams and delivering complex SoC/silicon products.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep expertise in SoC-level verification, including interconnect fabrics, coherency protocols, HSIO, and peripheral subsystems.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong background in UVM-based test plan development, assertions, coverage analysis, and abstraction layer design.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Demonstrated ability to manage priorities, engage with stakeholders, and drive organizational success.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h3\u0026gt;Required Experience\u0026lt;/h3\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Hands-on expertise with SoC-level verification environments, including integration of multiple IPs, \u0026lt;strong\u0026gt;HSIO, and peripherals\u0026lt;/strong\u0026gt;.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep experience in UVM-based test plan development, sequence generation, and coverage analysis.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong background in writing assertions, cover properties, and analyzing coverage data at both IP and SoC levels.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience in developing scalable verification infrastructures to simplify and accelerate SoC-level deployments.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h3\u0026gt;Preferred Experience\u0026lt;/h3\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Expertise in verifying complex SoC subsystems such as NoC-based interconnects, coherency fabrics, HSIO, and memory hierarchies.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with buffering, queuing, QoS, and system-level performance analysis.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with emulation, FPGA prototyping, and hybrid verification flows.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of AI-driven verification methodologies and workforce transformation strategies.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Experience with AI/ML accelerators, networking, automotive, data center, or high-performance computing SoCs.\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Familiarity with low-power verification methodologies and power-aware verification.\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Why Join Us?\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Opportunity to lead cutting-edge SoC development programs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Influence verification strategy across next-generation products.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Build and grow a world-class verification organization.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work with highly talented engineering teams on innovative technologies.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4049113005,"name":"Bengaluru","location":"India","child_ids":[],"parent_id":4052109005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4706724005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4441066005,"location":{"name":"Research Triangle Park, North Carolina, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Research Triangle Park, North Carolina","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"CTO Organization","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4706724005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2649","title":"Sr. Principal Business Manager – Data Center \u0026 AI Infrastructure","company_name":"Astera Labs","first_published":"2026-06-26T12:06:06-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;h2 class=\u0026quot;wnfdnth _1ibi0s33y _1ibi0s34u\u0026quot; data-pm-slice=\u0026quot;1 1 []\u0026quot;\u0026gt;Role Overview\u0026lt;/h2\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Are you passionate about driving business growth for next-generation data infrastructure, working hand-in-hand with hyperscalers and AI platform providers? Do you thrive at the intersection of customer engagement, commercial strategy, and cutting-edge technologies like Open Rack, rack-scale systems, and PCIe scale-up architectures? At Astera Labs, you\u0026#39;ll help shape how the world\u0026#39;s largest AI platforms are connected — translating complex infrastructure trends into successful business outcomes.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;As a Sr. Principal Business Manager, you will partner closely with customers, sales, product marketing, and engineering to accelerate revenue growth and execute strategic deals in the rapidly evolving AI and cloud infrastructure market. This is a high-visibility role for a hyper-growth, purpose-built connectivity company enabling rack-scale AI — requiring strong leadership, deep commercial acumen, and the ability to convert design wins into durable revenue.\u0026lt;/p\u0026gt;\n\u0026lt;h2 class=\u0026quot;wnfdnth _1ibi0s33y _1ibi0s34u\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/h2\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdnte\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Drive Strategic Deal Pipeline\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Lead engagement with hyperscale and AI customers to secure design wins and drive conversion to contracts and purchase orders\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Focus on opportunities involving Open Rack deployments, rack-scale architectures, and PCIe-based scale-up systems\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Partner with sales to accelerate pipeline execution for critical, high-impact deals\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdnte\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Own Commercial Strategy \u0026amp;amp; Pricing\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Define and approve pricing frameworks and commercial terms across key accounts\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Align pricing strategies with market dynamics in AI infrastructure, rack-scale compute, and interconnect technologies\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Collaborate with product marketing to ensure consistency across the product portfolio\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdnte\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Enable Customer \u0026amp;amp; Segment Strategies\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Develop playbooks for hyperscalers, AI cloud providers, and OEM segments\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Incorporate insights across Open Compute / Open Rack ecosystems, rack-scale system design trends, and PCIe scale-up and high-speed interconnect adoption\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Support negotiation strategy, solution positioning, and competitive differentiation\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdnte\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntd _1ibi0s33w\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Support Business Scaling \u0026amp;amp; Operations\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Drive process improvements to support rapid growth in AI and data center markets\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Partner cross-functionally to improve operational efficiency, tools, and organizational clarity\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h2 class=\u0026quot;wnfdnth _1ibi0s33y _1ibi0s34u\u0026quot;\u0026gt;Basic Qualifications\u0026lt;/h2\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Engineering, Computer Science, Business, or a related field\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;12+ years of experience in product marketing, business management, sales, operations, or related roles in the semiconductor or data center ecosystem\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Strong track record of leading complex deal negotiations and securing strategic customer agreements with hyperscalers, cloud providers, or OEMs\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Deep understanding of PCIe and familiarity with Ethernet, UALink, UCIe, and system-level architectures\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Demonstrated experience with AI / cloud infrastructure platforms, rack-scale system architectures, and scale-up vs. scale-out compute models\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Exceptional communication and stakeholder management skills, with the ability to translate customer needs into compelling business and technical solutions\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h2 class=\u0026quot;wnfdnth _1ibi0s33y _1ibi0s34u\u0026quot;\u0026gt;Preferred Qualifications\u0026lt;/h2\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;MBA or advanced degree in Engineering, Computer Science, or Business\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Direct experience supporting Open Compute / Open Rack ecosystems and engaging with hyperscale procurement and engineering teams\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Familiarity with high-speed connectivity technologies (PCIe Gen 6/Gen 7, retimers, switches) and emerging AI fabric standards\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Experience defining pricing frameworks and commercial models for high-growth semiconductor or systems products\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;Proven ability to operate effectively in a fast-paced, hyper-growth environment and influence executive stakeholders\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4141010005,"name":"Platform Architecture","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4065362005,"name":"Research Triangle Park, North Carolina","location":"North Carolina","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4727115005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4451021005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Field Applications Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4727115005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2026-406","title":"(Sr.) Principal Engineer - Field Applications ","company_name":"Astera Labs","first_published":"2026-08-24T20:46:52-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As a (Sr.) Principal Engineer - Field Applications Engineering, you will serve as a trusted technical partner to customers deploying Astera Labs’ high-speed connectivity solutions. You will lead the continuation of critical customer support for Ethernet and PCIe products, translating system requirements into reliable, production-ready designs and accelerating issue resolution across complex AI infrastructure platforms.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Based onsite in San Jose, you will work closely with customers and cross-functional teams across sales, product management, design engineering, validation, and operations. Your expertise in high-speed interfaces, physical-layer behavior, and system-level integration will help customers bring next-generation rack-scale AI architectures to market with confidence.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Customer Technical Leadership\u0026lt;/strong\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Lead technical engagements with strategic customers from architecture definition through deployment and production support.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Own customer escalations, establish clear action plans, and drive issues to timely closure with measurable outcomes.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Present design recommendations, bring-up results, and technical tradeoffs to customer engineering and leadership teams.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Ethernet and PCIe Product Support\u0026lt;/strong\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Develop and execute system-level debug plans for Ethernet and PCIe connectivity issues, including link training, interoperability, compliance, and performance.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Analyze physical-layer behavior, signal-integrity symptoms, error logs, lab data, and system telemetry to isolate root causes.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Partner with engineering teams to reproduce field issues, influence product improvements, and communicate effective workarounds or corrective actions.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional Enablement\u0026lt;/strong\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with sales and product management to capture customer requirements and shape application strategies for emerging AI infrastructure designs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Create technical collateral, reference architectures, application notes, and enablement materials for customers and internal teams.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Mentor Field Applications Engineers and contribute to scalable processes for customer onboarding, issue tracking, and product adoption.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;8–20 years of experience in field applications engineering, system engineering, product engineering, or a related domain.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep hands-on experience with Ethernet\u0026amp;nbsp;and/or PCIe systems, high-speed SerDes, link training, interoperability, and compliance.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of physical-layer concepts, signal integrity, board-level bring-up, lab instrumentation, and system-level debug.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Demonstrated ability to lead complex customer escalations, debug, and communicate technical concepts clearly to diverse audiences.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ability to work onsite in San Jose and travel to customer and partner locations as needed.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Master’s degree in Electrical Engineering, Computer Engineering, or a related field.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with PCIe Gen 5/6/7, high-speed Ethernet, retimers, redrivers, signal-conditioning and scale-up, scale-out solutions.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with server, accelerator, switch, NIC, storage, or other data-center platform architectures.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience developing reference designs, validation plans, interoperability strategies, or customer-facing technical documentation.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven record of influencing cross-functional teams and mentoring technical professionals in a fast-moving, high-growth environment.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea\u0026quot; data-pm-slice=\u0026quot;1 1 []\u0026quot;\u0026gt;Salary range is $205,000 to $260,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p8i6j01 paragraph\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4134751005,"name":"Field Applications","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4723516005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4449218005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Product Applications Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4723516005,"updated_at":"2026-10-08T01:03:39-04:00","requisition_id":null,"title":"Sr. Principal Product Applications Engineer – Custom Solutions","company_name":"Astera Labs","first_published":"2026-08-14T17:07:50-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;h2\u0026gt;\u0026amp;nbsp;\u0026lt;/h2\u0026gt;\n\u0026lt;p\u0026gt;As our Custom Solutions business continues to grow, we\u0026#39;re seeking experienced engineers who thrive at the intersection of customer engagement, system architecture, and advanced silicon development.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;The Opportunity\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is seeking a Sr Principal Product Applications Engineer to serve as the technical bridge between our customers and engineering organization.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;In this highly customer-facing role, you will work directly with hyperscalers, AI labs, and infrastructure partners to support custom silicon programs from early architecture discussions through production deployment. You\u0026#39;ll partner with Product Management, Architecture, ASIC Design, Firmware, Validation, and Software Engineering to ensure customer requirements are translated into successful products while helping customers deploy next-generation AI infrastructure.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This is not a traditional pre-sales Field Applications Engineer role, nor is it an internal validation position. You will combine deep technical expertise with strong customer engagement, helping solve complex system-level challenges while influencing future silicon development.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Responsibilities:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Serve as the primary technical interface for strategic customer programs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop trusted technical relationships with customer engineering teams and become a key advisor throughout the product lifecycle.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support customer engagements from architecture discussions through silicon bring-up, validation, production, and deployment.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead complex customer debug efforts involving hardware, firmware, software, and system-level integration.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Translate customer requirements, deployment challenges, and architecture feedback into actionable engineering requirements.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate closely with Product Management, Architecture, ASIC Design, Firmware, Validation, and Software Engineering to drive customer success.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Influence future silicon products by providing customer insights and technical feedback to engineering teams.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support customer design reviews, architecture discussions, technical training, and executive-level technical engagements.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop technical collateral, application notes, reference designs, troubleshooting guides, and customer documentation.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support technical escalations and drive issues to resolution across cross-functional engineering teams.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop automation and diagnostic tools using Python or C/C++ to improve engineering efficiency and customer support.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Travel to customer sites as needed to support key design wins and strategic engagements.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Qualifications:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;10+ years of experience in Product Applications Engineering, Systems Engineering, Customer Engineering, Field Applications Engineering, or a related customer-facing semiconductor role.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience supporting advanced semiconductor or custom silicon products from architecture through production.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of high-speed interconnect technologies, including Ethernet (through 800G), PCIe, PAM4, SerDes, DSPs, DAC, AEC, ACC, AOC, and related hardware technologies.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with silicon bring-up, post-silicon validation, and system-level debugging.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong Linux debugging and troubleshooting experience.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience writing Python or C/C++ scripts for automation, diagnostics, firmware validation, or lab workflows.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven experience working directly with hyperscalers, AI labs, and infrastructure partners. Excellent communication, presentation, and technical leadership skills.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience supporting AI infrastructure platforms or high-performance computing systems.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with custom ASIC development and customer-specific silicon solutions.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with firmware, embedded software, or FPGA validation.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Understanding of networking, storage, memory, or accelerator architectures.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience creating customer-facing technical documentation, training materials, and application notes.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience supporting executive customer reviews and technical design discussions.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h2\u0026gt;\u0026amp;nbsp;\u0026lt;/h2\u0026gt;\n\u0026lt;p class=\u0026quot;p8i6j01 paragraph\u0026quot;\u0026gt;The salary range is $205,000 to $260,000, depending on experience, level, and business needs. This role may be eligible for a discretionary bonus, incentives, and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4134751005,"name":"Field Applications","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4709339005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4442383005,"location":{"name":"Toronto, Ontario, Canada"},"metadata":[{"id":12122734005,"name":"Country","value":"Canada","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Toronto","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":"Program Management","value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Program Management","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4709339005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2670","title":"Sr. Principal Program Manager, ASIC Design","company_name":"Astera Labs","first_published":"2026-06-24T21:07:52-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As a \u0026lt;strong\u0026gt;Sr. Principal Program Manager, ASIC Design\u0026lt;/strong\u0026gt;\u0026amp;nbsp;at Astera Labs, you will own the cross-functional execution framework for advanced ASIC programs from early planning through tapeout. You will drive milestones, dependencies, execution reviews, decision-making forums, risk management, and tapeout readiness across multiple engineering teams.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;You will partner closely with architecture, RTL design, functional verification, emulation, DFT, synthesis, physical design, CAD, IP, product management, engineering leadership, and external partners.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This is a high-impact role for a technical program leader who can operate in a fast-moving environment, manage ambiguity, drive accountability, and establish scalable execution practices across complex silicon development programs.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Program Execution \u0026amp;amp; Planning\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Lead pre-silicon execution of complex ASIC and subsystem programs from concept through tapeout.\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Own program plans, schedules, milestones, dependencies, risk registers, dashboards, and executive-level status reporting.\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Drive pre-silicon and NPD phase-gate execution from kickoff through final GDS handoff, ensuring cross-functional readiness across architecture, RTL, verification, DFT, physical design, signoff, and tapeout.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional Alignment \u0026amp;amp; Coordination\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Drive cross-functional alignment across architecture, RTL design, verification, emulation, DFT, synthesis, physical design, CAD, IP integration, product management, and external partners.\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Track IP delivery, PDK updates, CAD/EDA flow readiness, tool dependencies, and foundry requirements.\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Partner with Post-Silicon PM and Validation teams to absorb feedback from post silicon bring up, including bug reports and Si issues.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Risk Management \u0026amp;amp; Decision-Making\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Identify execution risks, lead risk mitigation plans, and drive trade-off decisions across scope, schedule, resources, and quality.\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Communicate program health, risks, dependencies, and decisions clearly to engineering teams, senior leaders, executives, and external partners.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Process \u0026amp;amp; Operational Excellence\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Establish scalable program management practices, operating rhythms, decision forums, documentation standards, and communication mechanisms, lead constant improvement.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Bachelor\u0026#39;s or Master\u0026#39;s degree in Electrical Engineering, Computer Engineering, or a related technical field.\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;10+ years of experience in ASIC/SoC development or silicon program execution, including 3+ years in technical program management, engineering program management, or technical leadership.\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience managing pre-silicon ASIC development flows, including architecture planning, RTL design, functional verification, synthesis, DFT, physical design, timing closure, signoff, and tapeout.\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience with advanced process nodes and high-performance ASIC/SoC development.\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Strong understanding of ASIC development milestones from product requirements through final GDS handoff.\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Familiarity with EDA flows, CAD infrastructure, IP integration, PDK readiness, foundry requirements, and vendor dependency management.\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience with pre-silicon validation platforms such as simulation, emulation, FPGA prototyping, or hardware/software co-validation.\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience driving complex cross-functional programs with multiple engineering teams, technical dependencies, external vendors, and aggressive schedules.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Strong technical judgment with the ability to manage trade-offs across performance, power, area, cost, schedule, quality, and risk.\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Excellent communication, organizational, leadership, and stakeholder-management skills.\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Ability to influence without authority across global, cross-functional, and cross-cultural teams.\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Ability to operate independently in a fast-paced, ambiguous, high-growth environment.\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience with high-speed connectivity, SerDes, PHY, PCIe, CXL, Ethernet, networking, switching, or AI infrastructure silicon.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Salary range is CAD 195,000 to CAD 240,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4043426005,"name":"Program Management","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000119005,"name":"Toronto","location":"Canada","child_ids":[],"parent_id":4004709005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4703792005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4439627005,"location":{"name":"Tel Aviv-Yafo, Tel Aviv District, Israel"},"metadata":[{"id":12122734005,"name":"Country","value":"Israel","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Tel Aviv","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Physical Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4703792005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2627","title":"Staff DFT Engineer","company_name":"Astera Labs","first_published":"2026-06-08T03:07:07-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is establishing a strategic R\u0026amp;amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical \u0026#39;data bottlenecks\u0026#39; enabling the future of AI at scale. As we expand our presence in Israel, we\u0026#39;re seeking a visionary\u0026lt;strong\u0026gt; Staff DFT Engineer \u0026lt;/strong\u0026gt;to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world\u0026#39;s largest AI clusters.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As a\u0026amp;nbsp;\u0026lt;strong\u0026gt;Staff DFT Engineer\u0026lt;/strong\u0026gt;\u0026amp;nbsp;at Astera Labs, you will be at the intersection of architecture, design, and production. You won\u0026#39;t just run tools—you will be a foundational member of the team responsible for the entire lifecycle of our silicon\u0026#39;s reliability. From defining initial DFT architecture to supporting post-silicon bring-up, your work ensures that the backbone of AI infrastructure connectivity is flawless and scalable. If you thrive on solving complex challenges in deep-submicron processes and want to establish world-class DFT methodologies, this is your opportunity.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;strong data-olk-copy-source=\u0026quot;MessageBody\u0026quot;\u0026gt;DFT Architecture \u0026amp;amp; Strategy\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Own the DFT journey from high-level architecture definition and RTL design to backend implementation and post-production support\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop comprehensive Design-for-Testability (DFT) strategies for next-generation connectivity platforms, ensuring chips meet the highest quality standards\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;​DFT architectures including JTAG/iJTAG, MBIST, Scan, and ATPG methodologies\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;strong\u0026gt;Test Pattern Development \u0026amp;amp; Optimization\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Generate and optimize high-quality test and debug patterns for production\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Perform Static Timing Analysis (STA) for DFT modes and conduct gate-level simulations to ensure robust performance\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive test coverage and quality metrics to meet stringent manufacturing requirements\u0026lt;br\u0026gt;\u0026lt;br\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional Collaboration \u0026amp;amp; Methodology Innovation\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Act as a multidisciplinary bridge, collaborating closely with Architecture, Verification, and Backend teams to ensure seamless integration and optimal QoR\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Participate in developing and maintaining cutting-edge DFT implementation flows\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Automate and\u0026amp;nbsp;improve methodologies using advanced scripting and tools\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-olk-copy-source=\u0026quot;MessageBody\u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering or related technical field\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;8+ years of hands-on experience\u0026amp;nbsp;in DFT roles at semiconductor companies\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep expertise in DFT flows and architectures including JTAG/iJTAG, MBIST, Scan, and ATPG\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency with industry-standard EDA tools from Synopsys (TestMAX) or Mentor (Tessent)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of logic design, verification, debug, and Static Timing Analysis (STA)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Scripting proficiency in Tcl, Perl, Python, or Shell for automation and innovation\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-olk-copy-source=\u0026quot;MessageBody\u0026quot;\u0026gt;Master\u0026#39;s\u0026amp;nbsp;degree in Electrical Engineering or related field\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of high-speed interface protocols (PCIe, Ethernet, CXL, UALink) and their specific test requirements\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience in chip bring-up and mass production activities\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Background in advanced process technologies (7nm and below)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent communication skills with ability to work effectively in global team environments\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4008937005,"name":"Israel","location":"Israel","child_ids":[4052111005,4061058005,4056876005],"parent_id":null}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4703779005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4439618005,"location":{"name":"Tel Aviv-Yafo, Tel Aviv District, Israel"},"metadata":[{"id":12122734005,"name":"Country","value":"Israel","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Tel Aviv","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Physical Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4703779005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2625","title":"Staff Physical Design Engineer - SoC EMIR Engineer","company_name":"Astera Labs","first_published":"2026-06-07T07:55:28-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is establishing a strategic R\u0026amp;amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical \u0026#39;data bottlenecks\u0026#39; enabling the future of AI at scale. As we expand our presence in Israel, we\u0026#39;re seeking a highly skilled Physical Design Engineer specializing in SoC EMIR to join our local engineering powerhouse from the ground up.\u0026lt;/p\u0026gt;\n\u0026lt;p data-path-to-node=\u0026quot;4\u0026quot;\u0026gt;This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world\u0026#39;s largest AI clusters. As an EMIR Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon.\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;margin: 0in; font-family: Calibri; font-size: 11.0pt;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;You will be responsible for SoC EMIR Analysis to ensure our products meet aggressive voltage drop and reliability targets in advanced FinFET process nodes, directly impacting the performance and yield of chips operating in the world\u0026lt;/span\u0026gt;\u0026lt;span lang=\u0026quot;en-IL\u0026quot;\u0026gt;’\u0026lt;/span\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;s most demanding AI and cloud environments.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,0,0\u0026quot;\u0026gt;Take responsibility on IR drop analysis and signal/power electromigration (EM) of very complex chip\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,3,0\u0026quot;\u0026gt;Collaborate closely with Physical Design team to insure a full power integrity\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,4,0\u0026quot;\u0026gt;Partner with Package Design engineers to perform Chip-Package co-analysis (CPM)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,5,0\u0026quot;\u0026gt;Understand root-cause analysis for voltage drop violations and EM risks\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,0,0\u0026quot;\u0026gt;Bachelor\u0026#39;s or Master\u0026#39;s degree in Electrical Engineering or a related technical field\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,1,0\u0026quot;\u0026gt;7+ years of hands-on experience in EMIR/Power Integrity analysis for high-performance SoCs or high-speed connectivity products\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,2,0\u0026quot;\u0026gt;Strong proficiency in industry-standard EMIR tools (Ansys RedHawk/RedHawk-SC, or Cadence Voltus)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,3,0\u0026quot;\u0026gt;Deep understanding of EM/IR challenges in advanced FinFET nodes (7nm, 5nm, 3nm)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,4,0\u0026quot;\u0026gt;Deep understanding of Place \u0026amp;amp; Route flows, power grid synthesis, extraction (RC), and standard cell architecture\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,4,0\u0026quot;\u0026gt;Deep understanding of EM and trade-offs between signal EM and power grid (PG) EM\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Preferred Experience\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;11,3,0\u0026quot;\u0026gt;Familiarity with thermal analysis tools and their interaction with electrical performance\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;11,4,0\u0026quot;\u0026gt;Experience working with sign-off criteria and margins for high-volume production chips\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;11,4,0\u0026quot;\u0026gt;Good understanding of timing and P\u0026amp;amp;R\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;11,4,0\u0026quot;\u0026gt;Basic understanding of packaging, top metal layers, MIM capacitor usage, and power distribution\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;11,4,0\u0026quot;\u0026gt;Ability to write TCL scripts for STA and Fusion Compiler (FC)\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4056876005,"name":"Tel Aviv","location":"Israel","child_ids":[],"parent_id":4008937005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4715773005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4445298005,"location":{"name":"Tel Aviv-Yafo, Tel Aviv District, Israel"},"metadata":[{"id":12122734005,"name":"Country","value":"Israel","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Haifa","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Digital Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4715773005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":null,"title":"Staff / Principal ASIC Design Engineer","company_name":"Astera Labs","first_published":"2026-07-16T05:38:47-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is establishing a strategic R\u0026amp;amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical \u0026#39;data bottlenecks\u0026#39; enabling the future of AI at scale. As we expand our presence in Israel, we\u0026#39;re seeking a talented\u0026lt;strong\u0026gt; \u0026lt;span class=\u0026quot;TextRun Underlined SCXW209305118 BCX0\u0026quot; lang=\u0026quot;EN-US\u0026quot; data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;NormalTextRun SCXW209305118 BCX0\u0026quot;\u0026gt;Staff / Principal ASIC Design Engineer\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026amp;nbsp;\u0026lt;/strong\u0026gt;to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful product ownership in a new site, designing the digital blocks that sit at the heart of our most ambitious connectivity projects.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As a\u0026lt;strong\u0026gt; \u0026lt;span class=\u0026quot;TextRun Underlined SCXW209305118 BCX0\u0026quot; lang=\u0026quot;EN-US\u0026quot; data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;NormalTextRun SCXW209305118 BCX0\u0026quot;\u0026gt;Staff / Principal ASIC Design Engineer\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;, you won\u0026#39;t just build chips—you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world\u0026#39;s largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving challenging problems in deep-submicron processes and want to contribute to the digital design foundation for AI infrastructure connectivity, this is your opportunity.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Design Ownership \u0026amp;amp; Implementation\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Serve as the point of contact for your logic blocks, interacting with Architecture, Verification, and Backend teams\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Quality Assurance \u0026amp;amp; Design Optimization\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Utilize industry-leading EDA tools (Lint, CDC, Synthesis, Timing, Power) and in-house quality assurance tools to ensure designs are robust, scalable, and power-efficient\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Apply design techniques to meet PPA (Power, Performance, Area) targets\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Contribute to design quality through verification and validation activities\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Methodology Innovation \u0026amp;amp; Collaboration\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Participate in design methodology improvements and tool automation initiatives\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Leverage AI assistance tools and contribute to in-house automation development to make engineering workflows faster and smarter\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Collaborate effectively across teams to ensure seamless integration\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering or related technical field\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;5+ years of experience in logic design at semiconductor companies\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Knowledge and experience in Verilog and/or SystemVerilog\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Excellent communication skills with ability to work effectively across teams\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Understanding of digital design principles and RTL coding best practices\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Master\u0026#39;s degree in Electrical Engineering or related field\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Knowledge of DDR and PCIe protocols and implementation\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Understanding of power management techniques for low-power design\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Familiarity with Clock Domain Crossing, simulation, debugging, synthesis, and timing analysis\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Proficiency in scripting languages such as Python or Perl\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience with high-speed serial interface designs or connectivity protocols\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184256005,"name":"Design Engineering CCE2","child_ids":[],"parent_id":null}],"offices":[{"id":4052111005,"name":"Haifa","location":"Israel","child_ids":[],"parent_id":4008937005},{"id":4056876005,"name":"Tel Aviv","location":"Israel","child_ids":[],"parent_id":4008937005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4674527005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4425429005,"location":{"name":"Tel Aviv-Yafo, Tel Aviv District, Israel"},"metadata":[{"id":12122734005,"name":"Country","value":"Israel","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Haifa","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":"Physical Design CCE2","value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Physical Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4674527005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2379","title":"Staff/ Principal Chip Top Physical Design  Engineer","company_name":"Astera Labs","first_published":"2026-03-18T12:56:17-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is establishing a strategic R\u0026amp;amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical \u0026#39;data bottlenecks\u0026#39; enabling the future of AI at scale. As we expand our presence in Israel, we\u0026#39;re seeking a highly skilled \u0026lt;strong\u0026gt;Chip Top Physical Design Engineer\u0026lt;/strong\u0026gt; focusing on implementation to join our local engineering powerhouse from the ground up.\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;br\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;If you thrive on solving complex, unnamed challenges in deep-submicron processes, your place is with us.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559738\u0026amp;quot;:240,\u0026amp;quot;335559739\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As a Physical Design Engineer, you will be a key hands-on member of our PD Team in the Israel R\u0026amp;amp;D center. You will execute the physical design of the SoC Top level for chips that drive the world’s largest AI clusters. You will be deeply involved in all PD disciplines of the chip, driving the tape-out (T.O.) GDS to meet strict signoff criteria (Timing, LVS, EMIR, DRC, PV, etc.), ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,0,0\u0026quot;\u0026gt;Execute SoC Top-level physical design and actively drive full-chip convergence\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,1,0\u0026quot;\u0026gt;Perform Top-Level physical implementation, including floor-planning, Place \u0026amp;amp; Route (P\u0026amp;amp;R), Clock Tree Synthesis (CTS), Power/Clock distribution, Power Integrity, and Timing/Physical signoff\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,2,0\u0026quot;\u0026gt;Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power, Performance, and Area (PPA). This involves participating in feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,3,0\u0026quot;\u0026gt;Resolve complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,4,0\u0026quot;\u0026gt;Collaborate closely with the Package team on Bump-map-to-Ballout design, taking all signal integrity aspects into consideration\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,0,0\u0026quot;\u0026gt;B.Sc. or M.Sc. in Electrical Engineering\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,1,0\u0026quot;\u0026gt;5+ years of hands-on experience in Chip Top Physical Design/Backend at leading semiconductor companies, working on advanced process technologies (5nm, 3nm, and below)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,2,0\u0026quot;\u0026gt;Proven experience executing complex block or chip-level projects with a proactive, \u0026quot;can-do\u0026quot; approach and excellent communication skills\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,3,0\u0026quot;\u0026gt;Deep hands-on expertise in RTL2GDS flows, including P\u0026amp;amp;R, STA, Physical Verification (DRC/LVS), Formal Verification, low-power implementation (UPF/CPF), and EMIR\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,4,0\u0026quot;\u0026gt;Mastery of industry-standard EDA tools (Synopsys Fusion Compiler/ICC2 or Cadence Innovus)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,5,0\u0026quot;\u0026gt;Practical experience handling both complex macro/subsystem-level designs and Full-Chip integration\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p data-path-to-node=\u0026quot;10\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;11,0,0\u0026quot;\u0026gt;Deep understanding of Power \u0026amp;amp; Noise analysis (EM/IR)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;11,1,0\u0026quot;\u0026gt;Experience with DFT (Design for Test) integration into the physical design flow\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;11,2,0\u0026quot;\u0026gt;Background in high-speed interfaces or data center protocols\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184376005,"name":"Physical Design CCE2","child_ids":[],"parent_id":null}],"offices":[{"id":4008937005,"name":"Israel","location":"Israel","child_ids":[4052111005,4061058005,4056876005],"parent_id":null}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4701334005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4438398005,"location":{"name":"Tel Aviv-Yafo, Tel Aviv District, Israel"},"metadata":[{"id":12122734005,"name":"Country","value":"Israel","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Tel Aviv","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Design Verification","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4701334005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2602","title":"Staff/ Principal Design Verification Engineer ","company_name":"Astera Labs","first_published":"2026-06-01T05:43:59-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is establishing a strategic R\u0026amp;amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical \u0026#39;data bottlenecks\u0026#39; enabling the future of AI at scale. As we expand our presence in Israel, we\u0026#39;re seeking a talented \u0026lt;strong\u0026gt;Staff/ Principal Design Verification Engineer\u0026lt;/strong\u0026gt;\u0026amp;nbsp;to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, developing the verification environments that ensure our next-generation AI silicon performs flawlessly.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As a \u0026lt;strong\u0026gt;Staff/ Principal Design Verification Engineer\u0026lt;/strong\u0026gt;, you will be a vital contributor to the quality and reliability of our Israel R\u0026amp;amp;D center. You will work on the front lines of functional verification, developing testbenches and environments that validate high-performance digital blocks, subsystems, and full-chip designs. You will tackle complex verification challenges that ensure our connectivity solutions meet the rigorous demands of the world\u0026#39;s largest AI clusters. If you thrive on solving technical puzzles and want to play a key role in delivering cutting-edge AI infrastructure connectivity, this is your opportunity.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Verification Environment Development\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Contribute to the design and development of ASIC verification environments, focusing on unit-level and subsystem functional blocks\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Develop and maintain SystemVerilog/UVM-based components including traffic generators, monitors, and checkers to ensure robust testing\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Execute detailed verification plans for challenging digital designs, ensuring all functional requirements are met and verified\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Coverage \u0026amp;amp; Quality Assurance\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Implement functional coverage models and analyze results to identify gaps in the verification process\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Drive designs toward 100% verification closure through comprehensive test development\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Contribute to verification methodology improvements and best practices\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Debug \u0026amp;amp; Cross-Functional Collaboration\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Work closely with design engineers to identify, root-cause, and resolve complex hardware bugs early in the development cycle\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Apply analytical skills and debugging techniques to solve intricate verification challenges\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Collaborate effectively in a fast-paced, team-oriented R\u0026amp;amp;D environment\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering or related technical field\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;5+ years of proven experience in ASIC verification within the semiconductor industry\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Hands-on experience developing components within complex verification environments using SystemVerilog\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Strong working knowledge of standard verification methodologies, specifically UVM\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Sharp analytical mind with passion for debugging and technical problem-solving\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Excellent communication skills with ability to thrive in collaborative R\u0026amp;amp;D environments\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Master\u0026#39;s degree in Electrical Engineering or related field\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Familiarity with Formal Verification or Emulation flows\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Basic proficiency in scripting languages such as Python or Tcl to automate verification tasks\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Exposure to industry-standard protocols such as AMBA, PCIe, Ethernet, or CXL\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience with assertion-based verification and constrained-random testing\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Background in connectivity or networking silicon verification\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4056876005,"name":"Tel Aviv","location":"Israel","child_ids":[],"parent_id":4008937005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4703778005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4439617005,"location":{"name":"Tel Aviv-Yafo, Tel Aviv District, Israel"},"metadata":[{"id":12122734005,"name":"Country","value":"Israel","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Tel Aviv","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Physical Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4703778005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2624","title":"Staff/ Principal Physical Design Engineer - SoC EMIR Expert","company_name":"Astera Labs","first_published":"2026-06-07T07:55:07-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is establishing a strategic R\u0026amp;amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical \u0026#39;data bottlenecks\u0026#39; enabling the future of AI at scale. As we expand our presence in Israel, we\u0026#39;re seeking a highly skilled Physical Design Engineer specializing in SoC EMIR to join our local engineering powerhouse from the ground up.\u0026lt;/p\u0026gt;\n\u0026lt;p data-path-to-node=\u0026quot;4\u0026quot;\u0026gt;This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world\u0026#39;s largest AI clusters. As an EMIR Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon.\u0026lt;/p\u0026gt;\n\u0026lt;p data-path-to-node=\u0026quot;5\u0026quot;\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;margin: 0in; font-family: Calibri; font-size: 11.0pt;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;You will be responsible for SoC EMIR Analysis to ensure our products meet aggressive voltage drop and reliability targets in advanced FinFET process nodes, directly impacting the performance and yield of chips operating in the world\u0026lt;/span\u0026gt;\u0026lt;span lang=\u0026quot;en-IL\u0026quot;\u0026gt;’\u0026lt;/span\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;s most demanding AI and cloud environments.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,0,0\u0026quot;\u0026gt;Take responsibility on IR drop analysis and signal/power electromigration (EM) of very complex chip\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,3,0\u0026quot;\u0026gt;Collaborate closely with Physical Design team to insure a full power integrity\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,4,0\u0026quot;\u0026gt;Be responsible\u0026amp;nbsp;on IR architecture for timing convergence\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,4,0\u0026quot;\u0026gt;Partner with Package Design engineers to perform Chip-Package co-analysis (CPM)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,5,0\u0026quot;\u0026gt;Understand root-cause analysis for voltage drop violations and EM risks\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,5,0\u0026quot;\u0026gt;Be responsible and go-to person for any IR related issues\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,0,0\u0026quot;\u0026gt;Bachelor\u0026#39;s or Master\u0026#39;s degree in Electrical Engineering or a related technical field\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,1,0\u0026quot;\u0026gt;10+ years of hands-on experience in EMIR/Power Integrity analysis for high-performance SoCs or high-speed connectivity products\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,2,0\u0026quot;\u0026gt;Strong proficiency in industry-standard EMIR tools (Ansys RedHawk/RedHawk-SC, or Cadence Voltus)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,3,0\u0026quot;\u0026gt;Deep understanding of EM/IR challenges in advanced FinFET nodes (7nm, 5nm, 3nm)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,4,0\u0026quot;\u0026gt;Deep understanding of Place \u0026amp;amp; Route flows, power grid synthesis, extraction (RC), and standard cell architecture\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,4,0\u0026quot;\u0026gt;Ability to define and own EMIR methodologies\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,4,0\u0026quot;\u0026gt;Capability to identify issues early in the project lifecycle (preferably with experience in sub-N5 TSMC technologies)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,4,0\u0026quot;\u0026gt;Deep understanding of EM and trade-offs between signal EM and power grid (PG) EM\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,4,0\u0026quot;\u0026gt;Thermal analysis, self-heat and Statistical EM proficiency\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Preferred Experience\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;11,3,0\u0026quot;\u0026gt;Familiarity with thermal analysis tools and their interaction with electrical performance\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;11,4,0\u0026quot;\u0026gt;Experience working with sign-off criteria and margins for high-volume production chips\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;11,4,0\u0026quot;\u0026gt;Good understanding of timing and P\u0026amp;amp;R\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;11,4,0\u0026quot;\u0026gt;Good understanding of packaging, top metal layers, MIM capacitor usage, and power distribution\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;11,4,0\u0026quot;\u0026gt;Understanding of ESD (including full CDM closure) and latch-up\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;11,4,0\u0026quot;\u0026gt;Strong Reliability knowledge\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;11,4,0\u0026quot;\u0026gt;Ability to write TCL scripts for STA and Fusion Compiler (FC)\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4052111005,"name":"Haifa","location":"Israel","child_ids":[],"parent_id":4008937005},{"id":4056876005,"name":"Tel Aviv","location":"Israel","child_ids":[],"parent_id":4008937005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4674520005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4425426005,"location":{"name":"Tel Aviv-Yafo, Tel Aviv District, Israel"},"metadata":[{"id":12122734005,"name":"Country","value":"Israel","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Tel Aviv","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":"Compute Connectivity Engineering 2","value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Physical Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4674520005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2378","title":"Staff/ Principal Physical Design STA Engineer ","company_name":"Astera Labs","first_published":"2026-03-18T12:58:06-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is establishing a strategic R\u0026amp;amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical \u0026#39;data bottlenecks\u0026#39; enabling the future of AI at scale. As we expand our presence in Israel, we\u0026#39;re seeking a highly skilled \u0026lt;strong\u0026gt;Static Timing Analysis (STA) Engineer \u0026lt;/strong\u0026gt;to join our local engineering powerhouse from the ground up.\u0026lt;/p\u0026gt;\n\u0026lt;p data-path-to-node=\u0026quot;4\u0026quot;\u0026gt;This is a unique opportunity to take on meaningful technical ownership in a new site, executing the sign-off methodology for chips that power the world\u0026#39;s most advanced AI clusters. As an STA Engineer, you will be deeply involved in the STA activities from chip partition and time budgeting through to final sign-off. You will bridge the gap between Architecture, Design, DFT, and Physical Design to ensure our high-performance silicon meets the aggressive timing targets required for next-generation connectivity.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;6,0,0\u0026quot;\u0026gt;Execute the STA flow and sign-off methodologies, ensuring our products meet rigorous timing criteria for the most demanding data center environments\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;6,1,0\u0026quot;\u0026gt;Collaborate closely with Architecture, Design, DFT, and Backend teams, participating in timing reviews and working with block owners to navigate the path to sign-off convergence\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;6,2,0\u0026quot;\u0026gt;Develop, optimize, and manage complex SDC constraints, ensuring they are accurate and robust across multi-scenario environments\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;6,3,0\u0026quot;\u0026gt;Analyze and resolve challenges related to cross-chip clock distribution networks and apply sophisticated margining techniques to ensure robust silicon across all process corners\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;6,4,0\u0026quot;\u0026gt;Participate in design methodology improvements and tool automation, utilizing both industry-standard EDA tools and custom scripts to make our sign-off process faster and more efficient\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;8,0,0\u0026quot;\u0026gt;B.Sc. in Electrical Engineering or Computer Engineering\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;8,1,0\u0026quot;\u0026gt;6+ years of hands-on experience in Static Timing Analysis (STA) at semiconductor companies, specifically working on advanced process technologies. \u0026lt;em data-path-to-node=\u0026quot;8,1,0\u0026quot; data-index-in-node=\u0026quot;147\u0026quot;\u0026gt;(Note: Adjust years of experience based on the exact level you are targeting)\u0026lt;/em\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;8,2,0\u0026quot;\u0026gt;Deep expertise in multi-scenario STA, as well as timing and SDC constraint development and verification at the block and subsystem levels\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;8,3,0\u0026quot;\u0026gt;Solid understanding of advanced margining methodologies, including OCV, AOCV, and POCV, from synthesis through to final sign-off\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;8,4,0\u0026quot;\u0026gt;Solid knowledge of physical design flows (Synthesis, P\u0026amp;amp;R, Physical Verification) and how they intersect with timing closure\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Preferred Experience\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;10,0,0\u0026quot;\u0026gt;Experience developing and validating constraints using industry-standard tools like Timing Constraints Manager (Synopsys) or TimeVision (Ausdia)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;10,1,0\u0026quot;\u0026gt;Proven track record of executing STA on complex Macro-level designs and supporting Full-Chip timing integration\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;10,2,0\u0026quot;\u0026gt;Strong background in scripting (Tcl, Python, Perl) and automation to enhance timing closure efficiency\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184233005,"name":"Compute Connectivity Engineering 2","child_ids":[],"parent_id":null}],"offices":[{"id":4008937005,"name":"Israel","location":"Israel","child_ids":[4052111005,4061058005,4056876005],"parent_id":null}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4663875005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4420491005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":"Physical Design CCE1","value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Physical Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4663875005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2297","title":"STA Physical Design Engineer, Senior Principal","company_name":"Astera Labs","first_published":"2026-02-23T20:49:02-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;As an Astera Labs \u0026lt;strong\u0026gt;STA Physical Design Engineer, Senior Principa\u0026lt;/strong\u0026gt;l you\u0026amp;nbsp;will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs\u0026#39; portfolio of connectivity ASICs used in the world\u0026#39;s leading cloud service providers, server and network OEMs. This role requires RTL to GDS ownership across design stages (Synthesis/PnR/\u0026lt;strong\u0026gt;STA/Signoff)\u0026lt;/strong\u0026gt;, deep technical expertise, and close collaboration with RTL and verification teams to ensure robust full-chip signoff. This role is fully on-site and in-person.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Independently drive PnR activities from RTL to GDS, ensuring robust signoff across complex SoCs or sub-systems.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Identify RTL issues early and work with frontend team on resolution.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience with various custom clocking techniques.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with high-speed designs with serdes/ddr IPs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Good understanding of PnR tool and signoff flows like Extraction, \u0026lt;strong\u0026gt;STA,\u0026lt;/strong\u0026gt; Formality, EM-IR and DRC/LVS etc\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience with \u0026lt;strong\u0026gt;ECO flow using PT DMSA and hyperscale models for bigger chips\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;A good understanding of \u0026lt;strong\u0026gt;SDC constraints,\u0026lt;/strong\u0026gt; be able to interact with design team on constraints refinement.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work with top level owners on defining and managing I/O timing budgets across hierarchical designs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of different ways to build hierarchical design (black-box model, ETM or abstract model etc).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Partner closely with design, implementation, and verification teams to drive block/top convergence, providing sign-off level expertise and guidance.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s in Electrical Engineering or Computer Science required; Master’s preferred.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;≥10 years of experience in PnR and sign-off for complex SoCs in Server, Storage, or Networking applications.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Expertise in PnR, Extraction, Timing closure, EM-IR, Formality and DRC/LVS at both block and full-chip level.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows in advanced nodes (7nm or below).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency with Cadence and/or Synopsys physical design/STA toolchains.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong scripting ability (Tcl, Python, Perl).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ability to work independently with strong prioritization and a professional, customer-focused mindset.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with high-speed SERDES and Ethernet PHY timing challenges.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of ECO methodologies, DFT tools, and test coverage analysis.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience working with IP vendors for both RTL and hard-macro integration.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;SystemVerilog/Verilog familiarity.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;p\u0026gt;The base salary range is USD 207,000.00 USD – USD 230,000.00. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. \u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184375005,"name":"Physical Design CCE1","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4724684005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4449204005,"location":{"name":"Haifa District, Israel"},"metadata":[{"id":12122734005,"name":"Country","value":"Israel","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Tel Aviv","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"System Validation","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4724684005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":null,"title":"System Validation Engineer","company_name":"Astera Labs","first_published":"2026-08-17T04:43:59-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;div class=\u0026quot;x_elementToProof\u0026quot; data-olk-copy-source=\u0026quot;MessageBody\u0026quot;\u0026gt;We are looking for a\u0026amp;nbsp;\u0026lt;strong\u0026gt;Post-Silicon Validation Engineer\u0026lt;/strong\u0026gt;\u0026amp;nbsp;with strong hands-on experience in PCIe link bring-up, physical-layer debug, and silicon validation. Engineer will work closely with Design, Architecture, Firmware, Software, Engineering teams.\u0026lt;/div\u0026gt;\n\u0026lt;div class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;ul data-spread=\u0026quot;false\u0026quot;\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Perform hands-on\u0026lt;strong\u0026gt;\u0026amp;nbsp;post-silicon validation\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Debug PCIe link issues including\u0026amp;nbsp;\u0026lt;strong\u0026gt;link training, LTSSM, equalization, recovery, resets, and link stability\u0026lt;/strong\u0026gt;.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Analyze PCIe state-machine traces, protocol traces, registers, logs, eye diagrams, and lab measurements.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive complex issues from initial failure through\u0026amp;nbsp;\u0026lt;strong\u0026gt;root-cause analysis and final resolution\u0026lt;/strong\u0026gt;.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work closely with silicon, firmware, software, architecture, and signal-integrity engineers to isolate issues across HW/FW/SW boundaries.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Validate PCIe functionality across different generations, platforms, configurations, and operating conditions.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop and execute PCIe validation plans, stress tests, corner-case scenarios, and interoperability tests.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Develop\u0026amp;nbsp; automation to improve validation coverage, debug efficiency, and regression testing.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;div class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Required Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;ul data-spread=\u0026quot;false\u0026quot;\u0026gt;\n\u0026lt;li\u0026gt;BS/MS in\u0026amp;nbsp;\u0026lt;strong\u0026gt;Electrical Engineering, Computer Engineering, Computer Science\u0026lt;/strong\u0026gt;, or equivalent experience.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;5+ years of engineering experience\u0026lt;/strong\u0026gt;\u0026amp;nbsp;in silicon validation, post-silicon debug, or high-speed interface development.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong hands-on knowledge of\u0026amp;nbsp;\u0026lt;strong\u0026gt;PCIe architecture and protocol\u0026lt;/strong\u0026gt;.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Experience working with PCIe analyzers, state traces, registers, logs, eye diagrams, and/or signal-integrity measurements.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong problem-solving skills and ability to independently drive issues to root cause.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience working across\u0026amp;nbsp;\u0026lt;strong\u0026gt;hardware, firmware, and software\u0026lt;/strong\u0026gt;\u0026amp;nbsp;boundaries.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Good scripting/programming skills, preferably\u0026amp;nbsp;\u0026lt;strong\u0026gt;Python\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Good Linux knowledge and experience with Linux PCIe debug tools.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong communication and collaboration skills.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;div class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;ul data-spread=\u0026quot;false\u0026quot;\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;Experience with\u0026amp;nbsp;\u0026lt;strong\u0026gt;PCIe Gen4/Gen5/Gen6/Gen7\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience with PCIe PHY, SerDes, equalization, lane margining, or signal integrity.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with PCIe compliance and interoperability testing.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience debugging intermittent, marginal, thermal-sensitive, or corner-case PCIe failures.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;Experience with PCIe switches,\u0026amp;nbsp; or networking/accelerator platforms.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Practical experience using AI/ML tools for engineering debug and automation.\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184348005,"name":"System Validation CCE2","child_ids":[],"parent_id":null}],"offices":[{"id":4052111005,"name":"Haifa","location":"Israel","child_ids":[],"parent_id":4008937005},{"id":4056876005,"name":"Tel Aviv","location":"Israel","child_ids":[],"parent_id":4008937005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4679263005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4427813005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"System Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4679263005,"updated_at":"2026-09-30T14:30:05-04:00","requisition_id":"2430","title":"System Validation Engineer - All Levels (AI Fabric Switches)","company_name":"Astera Labs","first_published":"2026-07-06T00:34:17-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;System Validation Engineer\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335559738\u0026amp;quot;:360,\u0026amp;quot;335559739\u0026amp;quot;:80}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 2\u0026quot;\u0026gt;Role Overview\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335559738\u0026amp;quot;:160,\u0026amp;quot;335559739\u0026amp;quot;:80}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot; data-ccp-parastyle-defn=\u0026quot;{\u0026amp;quot;ObjectId\u0026amp;quot;:\u0026amp;quot;276295ed-5df2-5456-988c-5fdbab071054|1\u0026amp;quot;,\u0026amp;quot;ClassId\u0026amp;quot;:1073872969,\u0026amp;quot;Properties\u0026amp;quot;:[201342446,\u0026amp;quot;1\u0026amp;quot;,201342447,\u0026amp;quot;5\u0026amp;quot;,201342448,\u0026amp;quot;1\u0026amp;quot;,201342449,\u0026amp;quot;1\u0026amp;quot;,469777841,\u0026amp;quot;Aptos\u0026amp;quot;,469777842,\u0026amp;quot;Arial\u0026amp;quot;,469777843,\u0026amp;quot;Aptos\u0026amp;quot;,469777844,\u0026amp;quot;Aptos\u0026amp;quot;,201341986,\u0026amp;quot;1\u0026amp;quot;,469769226,\u0026amp;quot;Aptos,Arial\u0026amp;quot;,268442635,\u0026amp;quot;24\u0026amp;quot;,335559739,\u0026amp;quot;180\u0026amp;quot;,335559738,\u0026amp;quot;180\u0026amp;quot;,469775450,\u0026amp;quot;First Paragraph\u0026amp;quot;,201340122,\u0026amp;quot;2\u0026amp;quot;,134234082,\u0026amp;quot;true\u0026amp;quot;,134233614,\u0026amp;quot;true\u0026amp;quot;,469778129,\u0026amp;quot;FirstParagraph\u0026amp;quot;,335572020,\u0026amp;quot;1\u0026amp;quot;,469775498,\u0026amp;quot;Body Text\u0026amp;quot;,469778324,\u0026amp;quot;Body Text\u0026amp;quot;]}\u0026quot;\u0026gt;Astera Labs is seeking System Validation Engineers to lead post-silicon bring-up and system validation for high-performance PCIe fabric switch products used in AI and cloud data centers. As part of the AI Fabric Engineering group, you will design and execute validation plans, automate data-centric test flows, drive root-cause investigations across silicon, firmware, hardware, and systems, and work directly with customers to validate real-world performance and interoperability.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:180,\u0026amp;quot;335559739\u0026amp;quot;:180}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Body Text\u0026quot;\u0026gt;Based in San Jose, you will collaborate with cross-functional teams to certify products against demanding system requirements and prepare new silicon and platforms for customer integration and launch. This is an opportunity to help shape validation strategy, automation infrastructure, and debug methodologies for purpose-built connectivity solutions enabling rack-scale AI infrastructure.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:180,\u0026amp;quot;335559739\u0026amp;quot;:180}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 2\u0026quot;\u0026gt;Success Looks Like\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335559738\u0026amp;quot;:160,\u0026amp;quot;335559739\u0026amp;quot;:80}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot; data-ccp-parastyle-defn=\u0026quot;{\u0026amp;quot;ObjectId\u0026amp;quot;:\u0026amp;quot;eafb41c0-47a4-52dc-ac6b-3b5a7536b560|1\u0026amp;quot;,\u0026amp;quot;ClassId\u0026amp;quot;:1073872969,\u0026amp;quot;Properties\u0026amp;quot;:[201342446,\u0026amp;quot;1\u0026amp;quot;,201342447,\u0026amp;quot;5\u0026amp;quot;,201342448,\u0026amp;quot;1\u0026amp;quot;,201342449,\u0026amp;quot;1\u0026amp;quot;,469777841,\u0026amp;quot;Aptos\u0026amp;quot;,469777842,\u0026amp;quot;Arial\u0026amp;quot;,469777843,\u0026amp;quot;Aptos\u0026amp;quot;,469777844,\u0026amp;quot;Aptos\u0026amp;quot;,201341986,\u0026amp;quot;1\u0026amp;quot;,469769226,\u0026amp;quot;Aptos,Arial\u0026amp;quot;,268442635,\u0026amp;quot;24\u0026amp;quot;,335559739,\u0026amp;quot;36\u0026amp;quot;,335559738,\u0026amp;quot;36\u0026amp;quot;,469775450,\u0026amp;quot;Compact\u0026amp;quot;,201340122,\u0026amp;quot;2\u0026amp;quot;,134234082,\u0026amp;quot;true\u0026amp;quot;,134233614,\u0026amp;quot;true\u0026amp;quot;,469778129,\u0026amp;quot;Compact\u0026amp;quot;,335572020,\u0026amp;quot;1\u0026amp;quot;,469778324,\u0026amp;quot;Body Text\u0026amp;quot;]}\u0026quot;\u0026gt; New silicon and platforms are brought up on schedule with reproducible validation results.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; Automated test suites reduce manual effort and provide clear pass/fail, compliance, and performance metrics.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; System issues are resolved rapidly through data-backed root-cause analysis, with strong technical communication and customer satisfaction during integration.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 2\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Validation Planning \u0026amp;amp; Strategy\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; Create comprehensive validation plans for AI fabric switch products covering functionality, performance, reliability, stress, and interoperability.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; Translate customer and system requirements into measurable test objectives, coverage goals, and product certification criteria.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; Contribute to PCIe compliance testing strategies and adapt consortium test cases for execution from x86 and ARM platforms.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Produce clear, data-driven validation reports, status updates, and specification-compliance assessments for internal stakeholders and customers.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Silicon \u0026amp;amp; System Bring-Up\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; Lead silicon and platform bring-up activities, verifying boot and runtime behavior on x86 and ARM systems.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; Ensure timely readiness for customer engagements, product demonstrations, and product launches.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; Debug complex issues across PCIe, NVMe, Ethernet, firmware, hardware, and system layers using protocol analyzers, logic analyzers, in-circuit debuggers, and CPU-based tool suites.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Design experiments to isolate unexpected behavior and drive root-cause resolution across silicon, firmware, hardware, software, and platform configuration.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Test Automation \u0026amp;amp; Infrastructure\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; Develop robust, repeatable Python automation for IC and board testing, with emphasis on execution efficiency, test orchestration, data collection, analysis, and automated reporting.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; Build scalable validation infrastructure that supports repeatable experiments, clear pass/fail criteria, performance characterization, and regression coverage.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Improve validation workflows and debug tools to reduce manual effort and accelerate issue resolution.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Customer \u0026amp;amp; Cross-Functional Collaboration\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; Collaborate directly with customers to capture system requirements, reproduce customer scenarios, and demonstrate product capabilities.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; Drive cross-functional root-cause analysis with silicon, firmware, hardware, software, product, and applications teams; document findings and corrective actions.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; Communicate risks, results, and recommendations clearly while managing multiple projects in a dynamic, customer-focused environment.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 2\u0026quot;\u0026gt;Basic Qualifications\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335559738\u0026amp;quot;:160,\u0026amp;quot;335559739\u0026amp;quot;:80}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; 2–12 years of experience supporting or developing complex SoC or silicon products for server, storage, networking, or AI infrastructure applications.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; Working understanding of x86 and ARM architectures and UEFI/Linux boot sequences.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; Solid understanding of high-speed signaling principles and hands-on experience with high-speed protocols such as PCIe, NVMe, or Ethernet.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; Proven experience with silicon and system bring-up, validation, and debug in laboratory and customer system environments.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; Strong Python automation skills for bench control, test orchestration, data analysis, and reporting.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; Experience with laboratory equipment including protocol analyzers, logic analyzers, in-circuit debuggers, and CPU-based tool suites.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; Strong prioritization, planning, communication, and independent execution skills, with a customer-focused mindset.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 2\u0026quot;\u0026gt;Preferred Qualifications\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335559738\u0026amp;quot;:160,\u0026amp;quot;335559739\u0026amp;quot;:80}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; Working knowledge of C or C++ for embedded firmware, device drivers, or low-level system software.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; Familiarity with PCIe/ CXL compliance standards and experience adapting consortium tests for platform execution.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; Advanced understanding of memory architectures, high-speed signaling, system boot flows, and AI server or accelerator platforms.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; Familiarity with schematic capture and PCB layout tools such as Cadence Allegro or Altium.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; Track record of influencing cross-functional teams and navigating complex matrixed organizations.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; Entrepreneurial, open-minded, and action-oriented approach, with the ability to think and act with the customer in mind.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Salary range is $148,500 to $255,000 depending on experience, level, and business \u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot;\u0026gt;need\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot;\u0026gt;. This role may be eligible for discretionary \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot;\u0026gt;bonus\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot;\u0026gt;, \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot;\u0026gt;incentives\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot;\u0026gt; and benefits.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025528005,"name":"Software Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4602995005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4391890005,"location":{"name":"Haifa District, Israel"},"metadata":[{"id":12122734005,"name":"Country","value":"Israel","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Haifa","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":"System Validation SCE","value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Firmware Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4602995005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"1924","title":"System Validation Engineer - Haifa","company_name":"Astera Labs","first_published":"2025-08-28T21:25:30-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is establishing a strategic R\u0026amp;amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical \u0026#39;data bottlenecks\u0026#39; enabling the future of AI at scale. As we expand our presence in Israel, we\u0026#39;re seeking a visionary\u0026lt;strong\u0026gt; System Validation Engineer \u0026lt;/strong\u0026gt;to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world\u0026#39;s largest AI clusters.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Job Description\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;The mission of this role is to perform system validation for Astera Lab’s highly advanced devices, that includes defining strategy, develop tools, innovate, be creative to make sure devices are performing as they should in all aspects, logical, performance, durability, stress and more.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;You will be part of the site located at Israel (Haifa – Matam), surrounded with highly experienced and professional engineers who will escort, mentor and support you on your journey at Astera Labs Israel.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic qualifications\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong academic and technical background in electrical or computer engineering\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;3-5 years experience validating and/or developing complex SoC/silicon products for Networking and/or Server \u0026amp;amp; Storage applications\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and work with minimal guidance and supervision.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Entrepreneurial, open-mind behavior and can-do attitude. Think and act with the customer in mind!\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required experience.\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Hands-on, thorough knowledge of high-speed protocols like Ethernet CXL, PCIe, NVMe,.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Silicon/System bring-up, validation, and debug experience, including customer’s systems.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;A Python coding experience\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with validation techniques C, C++\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with lab equipment as protocol analyzers, chambers, in-circuit debuggers, and CPU-based tool suites.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with lab testing automation techniques\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred experience\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with devices trees and related debugging techniques.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with board system design\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;C\\C++ for embedded FW and device drivers\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Basic understanding of x86/ARM architecture, UEFI/Linux boot sequence\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with CXL compliance standards and ability to follow and be involved in compliance consortiums to adapt the tests to be run from X86/ARM based platforms.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience working with DRAM memory vendors on DDR4 or DDR5 to identify issues and working on SoC HW/FW to improve memory calibration and tuning sequences.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of memory subsystem compliance from a data integrity and RAS is a plus.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of schematic capture and PCB layout tools from Cadence, Altium, etc.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is a young light-footed company, allowing our engineers to fully exploit their creativity and innovative thinking to enable you to grow up your engineering capabilities to the maximum!\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184349005,"name":"System Validation SCE","child_ids":[],"parent_id":null}],"offices":[{"id":4052111005,"name":"Haifa","location":"Israel","child_ids":[],"parent_id":4008937005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4742857005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4458823005,"location":{"name":"Haifa District, Israel"},"metadata":[{"id":12122734005,"name":"Country","value":"Israel","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Tel Aviv","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"System Validation","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4742857005,"updated_at":"2026-10-11T04:28:38-04:00","requisition_id":null,"title":"System Validation manager ","company_name":"Astera Labs","first_published":"2026-10-11T04:28:38-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;div class=\u0026quot;x_elementToProof\u0026quot; data-olk-copy-source=\u0026quot;MessageBody\u0026quot;\u0026gt;Astera Labs is seeking a dynamic and technical Manager, System Validation Engineering to lead our post-silicon and system validation teams in Haifa.\u0026lt;/div\u0026gt;\n\u0026lt;p class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;In this leadership role, you will direct engineering teams responsible for validating high-performance PCIe and connectivity fabric switch products built for rack-scale AI and cloud data centers.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;You will combine hands-on technical oversight with strong people management, guiding engineers through validation strategy, automated test execution, deep root-cause investigations, and direct customer integration support. This is a critical leadership position to shape our validation methodologies, scale automation infrastructure, and ensure the flawless execution and launch of purpose-built connectivity silicon.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;Success Looks Like\u0026lt;/p\u0026gt;\n\u0026lt;ul data-path-to-node=\u0026quot;9\u0026quot;\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;Execution \u0026amp;amp; On-Time Delivery: New silicon, platforms, and AI fabric switch solutions are brought up and certified on schedule with rigorous, reproducible validation results.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;Team Leadership \u0026amp;amp; Scale: Engineering talent is mentored, engaged, and effectively deployed across multiple projects, fostering a culture of technical excellence, accountability, and innovation.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;Automation \u0026amp;amp; Efficiency: Test suites and infrastructure are scaled to maximize test coverage, minimize manual effort, and drive down test cycle times.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;Customer Trust \u0026amp;amp; Resolution: Complex cross-functional system issues are resolved rapidly through data-backed root-cause analysis, resulting in high customer satisfaction during integration and deployment.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;Leadership \u0026amp;amp; Team Management\u0026lt;/p\u0026gt;\n\u0026lt;ul data-path-to-node=\u0026quot;13\u0026quot;\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;Lead, mentor, and grow a team of high-performing System Validation Engineers at Haifa\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;Drive resource planning, project scheduling, engineer capacity tracking, and milestone execution across multiple complex silicon programs.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;Foster strong cross-functional alignment with Silicon Design, Firmware, Software, Hardware, Product, and Applications teams.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;Attract, hire, and develop top engineering talent while championing technical growth and career development.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;Validation Strategy \u0026amp;amp; Planning\u0026lt;/p\u0026gt;\n\u0026lt;ul data-path-to-node=\u0026quot;15\u0026quot;\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;Oversee the creation of comprehensive validation plans for AI fabric switch products covering functionality, performance, reliability, stress, and interoperability.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;Translate complex customer and system requirements into measurable test objectives, coverage goals, and product certification criteria.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;Establish clear, data-driven reporting metrics, status dashboards, and specification-compliance assessments for executive leadership and key customers.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Guide technical execution for silicon and platform bring-up activities, verifying boot and runtime behavior on x86 and ARM systems.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;Oversee complex debugging across PCIe, NVMe, Ethernet, firmware, hardware, and system layers using advanced lab equipment and CPU-based tool suites.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;Drive systematic root-cause problem solving, guiding engineers through structured experiment design to isolate and resolve complex silicon, firmware, and board-level issues.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;Scale validation infrastructure supporting test orchestration, advanced data collection, statistical analysis, and automated report generation.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;Continually optimize validation workflows and lab debug tools to accelerate issue resolution and improve regression coverage.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;Basic Qualifications\u0026lt;/p\u0026gt;\n\u0026lt;ul data-path-to-node=\u0026quot;24\u0026quot;\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;Bachelor’s degree in Electrical Engineering, Computer Science\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;8+ years of total experience in silicon product development, post-silicon validation, or system engineering for server, storage, networking, or AI infrastructure applications, including 4+ years of technical leadership or people management experience.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;Demonstrated experience leading engineering teams, managing project schedules, and driving execution in a fast-paced environment.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;Proven track record with complex silicon and system bring-up, validation, and laboratory debug methodologies.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;Strong Python automation background for test orchestration, bench control, and data analysis.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;Exceptional communication, stakeholder management, and cross-functional leadership skills.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184348005,"name":"System Validation CCE2","child_ids":[],"parent_id":null}],"offices":[{"id":4052111005,"name":"Haifa","location":"Israel","child_ids":[],"parent_id":4008937005},{"id":4056876005,"name":"Tel Aviv","location":"Israel","child_ids":[],"parent_id":4008937005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4735378005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4455251005,"location":{"name":"Ho Chi Minh City, Vietnam"},"metadata":[{"id":12122734005,"name":"Country","value":"Vietnam","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Ho Chi Minh","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Analog Layout","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4735378005,"updated_at":"2026-09-28T22:35:13-04:00","requisition_id":null,"title":"Tech Lead, Analog Mixed Signal Layout ","company_name":"Astera Labs","first_published":"2026-09-28T22:35:13-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;About the Role\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;We are seeking an experienced AMS (Analog Mixed-Signal) Layout Engineer to join our high-performance design team working on next-generation transceiver IPs targeting the TSMC 3nm technology node.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;In this role, you will be responsible for the layout of advanced analog and mixed-signal circuits, ensuring performance, matching, and manufacturability for high-speed transceiver applications in cutting-edge process nodes.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Key Responsibilities\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Perform full-custom layout of high-speed SerDes design such as RX Front-ends, TX Drivers, PLLs, CDRs, bias circuits, ADCs/DACs.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Handle layout of high-frequency components with emphasis on parasitic minimization, shielding, and routing symmetry.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Floorplan and assemble top-level analog/mixed-signal and perform layout integration.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Work closely with circuit designers to understand schematic intent, matching, symmetry, and parasitic sensitivity.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Ensure high-quality layout practices to meet DRC, LVS, ERC, and EM/IR signoff in advanced FinFET processes (High-end process nodes).\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Perform layout-versus-schematic (LVS), design rule checks (DRC), and parasitic extraction (PEX) using industry-standard tools (Cadence Virtuoso XL, Calibre ...), .\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Support post-layout simulation by extracting and delivering clean parasitic netlists (RC).\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Collaborate with physical design and digital implementation teams on analog-digital boundary integration.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Required Qualifications\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Bachelor’s or Master’s degree in Electrical Engineering, Microelectronics, or related field.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· 7+ years of experience in custom analog or mixed-signal layout in deep-submicron or FinFET processes.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Strong experience with:\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;o High-speed SerDes designs, PLLs, ADCs/DACs, power management units.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;o Handling sensitive matching and noise isolation constraints (e.g., differential pair matching, guard rings).\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;o Tools like Virtuoso Layout Editor, Calibre, PVS, StarRC, Quantus, or similar.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Strong understanding of semiconductor physics, CMOS fabrication processes, and advanced process nodes (e.g., 7nm and below).\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· In-depth knowledge of layout techniques for minimizing parasitics, noise, and ensuring robust circuit operation.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Experience with layout debugging and tapeout release process.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Pay and Benefits\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Competitive salary.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Performance bonus each year.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Long Term Incentive (LTI)\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Flexible working time.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Health check each year.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Insurance for engineer and family.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Lunch Allowance.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Company trips\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184652005,"name":"Analog Layout \u0026 Design (VNM_Analog Layout \u0026 Design)","child_ids":[],"parent_id":null}],"offices":[{"id":4053944005,"name":"Ho Chi Minh City","location":"Vietnam","child_ids":[],"parent_id":4053943005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4719812005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4447363005,"location":{"name":"Bengaluru, Karnataka, India"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":null,"value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4719812005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2696","title":"Tech Lead ASIC Design Engineer","company_name":"Astera Labs","first_published":"2026-07-30T11:45:27-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Job Description: Lead Digital Design Engineer\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Location:\u0026lt;/strong\u0026gt; Bengaluru, India (Hybrid)\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;About Astera Labs\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is a global leader in purpose-built semiconductor connectivity solutions for AI and cloud infrastructure. Our intelligent connectivity platform enables hyperscalers and system OEMs to maximize the performance and scalability of accelerated computing through industry-leading technologies such as Compute Express Link (CXL), PCI Express (PCIe), and Ethernet.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As AI and cloud workloads continue to evolve, Astera Labs is developing innovative silicon solutions that enable the next generation of high-performance computing. We are looking for a talented \u0026lt;strong\u0026gt;Lead Digital Design Engineer\u0026lt;/strong\u0026gt; to join our Silicon Engineering team and contribute to the development of cutting-edge connectivity products.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Position Summary\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As a \u0026lt;strong\u0026gt;Lead Digital Design Engineer\u0026lt;/strong\u0026gt;, you will be responsible for the design and implementation of complex digital IPs and SoC subsystems for next-generation AI infrastructure products. You will drive RTL development from architecture through implementation, collaborate closely with cross-functional teams, and provide technical leadership to ensure high-quality, first-pass silicon.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This role requires strong expertise in RTL design, SoC integration, and high-speed interfaces, along with the ability to mentor engineers and lead technical execution.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Lead the architecture, microarchitecture, RTL design, and implementation of complex digital IPs and SoC subsystems for high-performance connectivity products.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive end-to-end ownership of design modules from specification through RTL development, integration, and silicon bring-up.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Design high-quality, synthesizable RTL using Verilog/System Verilog, ensuring optimal performance, power, area (PPA), and scalability.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop complex data paths, control logic, finite state machines, arbitration mechanisms, and protocol engines.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Design and implement solutions for high-speed interfaces and protocols, including CXL, PCIe, Ethernet, and AXI-based interconnects.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with Architecture teams to define microarchitecture and review functional specifications.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Partner closely with Design Verification teams to develop verification strategies, debug design issues, and achieve functional closure.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work with Physical Design teams to resolve timing, power, congestion, and implementation challenges through RTL optimization.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support synthesis, lint, CDC/RDC, STA, DFT, and design sign-off activities.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Participate in design reviews and ensure compliance with RTL coding guidelines and design best practices.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive debug and resolution of RTL, integration, and post-silicon issues in collaboration with firmware, validation, and system engineering teams.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor\u0026#39;s or Master\u0026#39;s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;6–12 years of experience in digital design for complex semiconductor products.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong expertise in Verilog/System Verilog RTL design.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with complete ASIC design cycles from microarchitecture through RTL implementation and silicon bring-up.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of digital design fundamentals, computer architecture, and SoC integration.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with synthesis, lint, CDC/RDC, STA, and RTL sign-off methodologies.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent debugging and analytical skills.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Technical Skills\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Experience in one or more of the following:\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Compute Express Link (CXL)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;PCI Express (PCIe)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ethernet MAC/PCS\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;High-speed networking or connectivity IP\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;AXI-based SoC architecture\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;DMA engines\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Packet processing pipelines\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Cache coherency protocols\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Memory controllers\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;High-speed interconnects\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Tools \u0026amp;amp; Methodologies\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Verilog/System Verilog\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Synopsys Design Compiler\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Cadence Genus\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;SpyGlass (Lint/CDC/RDC)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Static Timing Analysis (STA)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Git or other version control systems\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Python, Tcl, Perl, or Shell scripting\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience designing connectivity, networking, storage, or AI accelerator silicon.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven track record of delivering successful ASIC or SoC tape-outs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with high-speed protocols and data center technologies.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience working in cross-functional global engineering teams.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Exposure to low-power design methodologies and Design for Test (DFT) is a plus.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Why Join Astera Labs?\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is redefining connectivity for AI and cloud infrastructure. As a Lead Digital Design Engineer, you\u0026#39;ll work on industry-leading technologies that power next-generation data centers and accelerated computing platforms. You\u0026#39;ll collaborate with world-class engineers, solve complex design challenges, and play a key role in delivering innovative semiconductor solutions that shape the future of AI.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184255005,"name":"Design Engineering CCE1","child_ids":[],"parent_id":null}],"offices":[{"id":4049113005,"name":"Bengaluru","location":"India","child_ids":[],"parent_id":4052109005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4738463005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4456732005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Digital Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4738463005,"updated_at":"2026-09-30T11:03:32-04:00","requisition_id":"2026-457","title":"Tech Lead, Digital Design Engineer","company_name":"Astera Labs","first_published":"2026-09-30T11:03:32-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p8i6j01 paragraph\u0026quot;\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;h2 class=\u0026quot;wnfdntj _1ibi0s35e _1ibi0s36a\u0026quot; data-pm-slice=\u0026quot;1 1 []\u0026quot;\u0026gt;Role Overview\u0026lt;/h2\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Astera Labs is seeking a Tech Lead Engineer to drive front-end digital design for high-performance switch ASICs that enable rack-scale AI infrastructure. In CCE2, you will translate microarchitecture into robust RTL and lead block-level execution across synthesis, timing, verification, DFT, and physical implementation.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;This is an opportunity to own critical connectivity technology from architecture through GDS while partnering across design, verification, physical design, and systems teams. You will help advance scalable fabric solutions built around UALink, UCI, PCIe Gen 6/7, ESUN, and Ethernet as Astera Labs continues to deliver purpose-built connectivity for demanding AI workloads.\u0026lt;/p\u0026gt;\n\u0026lt;h2 class=\u0026quot;wnfdntj _1ibi0s35e _1ibi0s36a\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/h2\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdntg\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntf _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Digital Architecture and RTL Design\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdntg\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntf _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Define microarchitecture and implement synthesizable RTL for complex switch ASIC blocks.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntf _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Develop front-end design solutions for high-performance networking and server connectivity applications.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntf _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Integrate and configure reusable IP while ensuring clean interfaces, performance, and maintainability.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntf _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Design Implementation and Signoff\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdntg\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntf _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Drive block-level execution through synthesis, timing closure, gate-level simulation, DFT, and GDS delivery.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntf _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Analyze design tradeoffs across performance, power, area, and schedule, and resolve implementation issues with cross-functional partners.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntf _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Apply Synopsys and/or Cadence digital design flows to deliver production-quality silicon.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntf _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Verification, Bring-Up, and Technical Leadership\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdntg\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntf _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Partner with design verification engineers to define plans, debug failures, and improve coverage using UVM-based methodologies.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntf _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Support silicon bring-up, lab debug, and root-cause analysis for complex connectivity issues.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntf _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Provide technical leadership, prioritize multiple workstreams, and communicate risks and progress clearly to stakeholders.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h2 class=\u0026quot;wnfdntj _1ibi0s35e _1ibi0s36a\u0026quot;\u0026gt;Basic Qualifications\u0026lt;/h2\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdntg\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntf _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Bachelor’s degree in Electrical Engineering or a related field.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntf _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;5–8 years of experience developing or supporting complex SoC or silicon products for switch ASIC, networking, server, or storage applications.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntf _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Hands-on experience with high-speed protocols, including UALink, UCI, PCIe Gen 6/7, ESUN, and Ethernet.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntf _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Proven front-end digital design experience spanning architecture, RTL, simulation, synthesis, timing closure, gate-level simulation, and DFT.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntf _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Experience owning blocks from architecture through GDS and working with Synopsys and/or Cadence design tools and flows.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntf _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Authorized to work in the United States.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h2 class=\u0026quot;wnfdntj _1ibi0s35e _1ibi0s36a\u0026quot;\u0026gt;Preferred Qualifications\u0026lt;/h2\u0026gt;\n\u0026lt;ul class=\u0026quot;wnfdntg\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntf _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Master’s degree in Electrical Engineering or a related field.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntf _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Experience developing or supporting PCIe or Ethernet switch products.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntf _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Familiarity with UVM-based design verification and coverage-driven debug.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntf _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Silicon bring-up and debug experience in small-geometry CMOS technologies at 28nm or below.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;wnfdntf _1ibi0s35c\u0026quot;\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Scripting experience with Python or comparable programming languages, along with a collaborative, customer-focused approach.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p class=\u0026quot;wnfdntv _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg\u0026quot;\u0026gt;Salary range is $175,500 to $195,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p8i6j01 paragraph\u0026quot;\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184256005,"name":"Design Engineering CCE2","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4738460005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4456731005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Digital Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4738460005,"updated_at":"2026-09-30T11:04:56-04:00","requisition_id":"2026-456","title":"Tech Lead, Digital Design Engineer","company_name":"Astera Labs","first_published":"2026-09-28T17:43:37-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;/span\u0026gt;\u0026lt;a href=\u0026quot;http://www.asteralabs.com/\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-charstyle=\u0026quot;Hyperlink\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/a\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Job Description\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;We are looking for \u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Senior Digital Design Engineers \u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;with experience developing micro-architecture and implementation of the front-end circuit design, including RTL, synthesis, IP integration, and block-level verification for high performance network controllers. The candidate must have good knowledge of communication/interface protocols such as PCI-Express (Gen-3 and above), Ualink, Esun, Ethernet etc.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Basic Qualifications:\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE is required, and a Master’s degree is preferred.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;+3 years’ experience supporting or developing complex SoC/silicon products for Switch ASIC, Networking applications and/or Server, Storage.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Authorized to work in the US and start immediately.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Required Experience:\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Hands-on, thorough knowledge of high-speed protocols like PCIe, Ualink, Esun, Ethernet, etc.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Proven front end design skill – architecture, RTL, simulations, synthesis, timing closure, GLS, DFT etc.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Block level ownership from architecture to GDS.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience with Synopsys and/or Cadence digital design tools/flows\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; 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data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Development/support for PCIe or Ethernet Switch products.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184256005,"name":"Design Engineering CCE2","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4737856005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4456400005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Design Verification","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4737856005,"updated_at":"2026-10-08T07:16:18-04:00","requisition_id":"2026-450","title":"Tech Lead Engineer, Design Verification","company_name":"Astera Labs","first_published":"2026-09-28T17:12:00-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 2\u0026quot;\u0026gt;Role Overview\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335559738\u0026amp;quot;:160,\u0026amp;quot;335559739\u0026amp;quot;:80}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot; data-ccp-parastyle-defn=\u0026quot;{\u0026amp;quot;ObjectId\u0026amp;quot;:\u0026amp;quot;276295ed-5df2-5456-988c-5fdbab071054|1\u0026amp;quot;,\u0026amp;quot;ClassId\u0026amp;quot;:1073872969,\u0026amp;quot;Properties\u0026amp;quot;:[201342446,\u0026amp;quot;1\u0026amp;quot;,201342447,\u0026amp;quot;5\u0026amp;quot;,201342448,\u0026amp;quot;1\u0026amp;quot;,201342449,\u0026amp;quot;1\u0026amp;quot;,469777841,\u0026amp;quot;Aptos\u0026amp;quot;,469777842,\u0026amp;quot;Arial\u0026amp;quot;,469777843,\u0026amp;quot;Aptos\u0026amp;quot;,469777844,\u0026amp;quot;Aptos\u0026amp;quot;,201341986,\u0026amp;quot;1\u0026amp;quot;,469769226,\u0026amp;quot;Aptos,Arial\u0026amp;quot;,268442635,\u0026amp;quot;24\u0026amp;quot;,335559739,\u0026amp;quot;180\u0026amp;quot;,335559738,\u0026amp;quot;180\u0026amp;quot;,469775450,\u0026amp;quot;First Paragraph\u0026amp;quot;,201340122,\u0026amp;quot;2\u0026amp;quot;,134234082,\u0026amp;quot;true\u0026amp;quot;,134233614,\u0026amp;quot;true\u0026amp;quot;,469778129,\u0026amp;quot;FirstParagraph\u0026amp;quot;,335572020,\u0026amp;quot;1\u0026amp;quot;,469775498,\u0026amp;quot;Body Text\u0026amp;quot;,469778324,\u0026amp;quot;Body Text\u0026amp;quot;]}\u0026quot;\u0026gt;As a Tech Lead Engineer, Design Verification, you will define and deliver robust verification for next-generation connectivity silicon that enables rack-scale AI infrastructure. You will partner closely with RTL, architecture, firmware, and post-silicon teams to build verification strategies that prove complex switching behavior across high-bandwidth protocols and demanding system environments.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:180,\u0026amp;quot;335559739\u0026amp;quot;:180}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Body Text\u0026quot;\u0026gt;Within CCE2, you will lead meaningful verification challenges from planning and testbench architecture through coverage closure and silicon learning. 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data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;0\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Develop block- and subsystem-level verification plans from specifications, architecture, and design requirements.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Define test scenarios, coverage models, checkers, assertions, and scoreboards for complex switching functionality.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Review designs and verification plans with architecture and RTL teams to \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;identify\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; corner cases early.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Lead verification planning and execution for assigned features, tracking risks, milestones, and quality metrics.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Environment Development and Execution\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;0\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Build and enhance reusable UVM-based \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;SystemVerilog\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; testbenches, agents, sequences, monitors, and reference models.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Create directed, constrained-random, and power-on-reset scenarios spanning PCIe Gen 6/Gen 7, \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;UALink\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;, and UCIe behavior.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Debug simulation failures using waveform analysis, logs, assertions, and cross-functional collaboration.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Partner with RTL and firmware teams to refine interfaces, improve observability, and resolve functional issues.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Coverage, Quality, and Silicon Readiness\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;0\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Drive functional and code coverage analysis, \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;identify\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; verification gaps, and close coverage to agreed milestones.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Develop regression strategies and automation to improve test quality, turnaround time, and failure triage.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Partner with design and post-silicon teams on \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;issue\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; isolation, root-cause analysis, and silicon bring-up readiness.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Communicate \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;verification\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; status, risks, and recommendations to technical stakeholders and project leadership.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 2\u0026quot;\u0026gt;Basic Qualifications\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335559738\u0026amp;quot;:160,\u0026amp;quot;335559739\u0026amp;quot;:80}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Bachelor’s degree in Electrical Engineering\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;, Computer Engineering, or \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;a related\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; technical field.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;5–8 years of experience in design verification for complex ASICs or SoCs.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Hands-on experience with \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;SystemVerilog\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; and UVM-based verification environments.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Experience developing verification plans, testbenches, assertions, scoreboards, and functional coverage models.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;7\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Familiarity with simulation, waveform-debug, regression, and coverage tools.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;8\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Strong technical leadership, debugging, communication, and collaboration skills in a fast-paced product development environment.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;heading 2\u0026quot;\u0026gt;Preferred Qualifications\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134245418\u0026amp;quot;:true,\u0026amp;quot;134245529\u0026amp;quot;:true,\u0026amp;quot;335559738\u0026amp;quot;:160,\u0026amp;quot;335559739\u0026amp;quot;:80}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;9\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Master’s degree in Electrical Engineering\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;, Computer Engineering, or \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;a related\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; field.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;10\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Experience verifying PCIe, \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;UALink\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;, UCIe, or other high-speed connectivity and switching protocols.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;11\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Knowledge of protocol checkers, formal verification, emulation, or hardware acceleration methodologies.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;12\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Experience with Python, PowerShell, or \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Tcl\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; for \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;verification\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt; automation and regression infrastructure.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335551671\u0026amp;quot;:0,\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;13\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;Compact\u0026quot;\u0026gt;Understanding of AI or data-center system architectures, including accelerator, memory, and fabric connectivity.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:36,\u0026amp;quot;335559739\u0026amp;quot;:36}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot;\u0026gt;Salary range is $175,500 to $195,000 depending on experience, level, and business \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot;\u0026gt;need\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot;\u0026gt;. This role may be eligible for discretionary \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot;\u0026gt;bonus\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot;\u0026gt;, \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot;\u0026gt;incentives\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-parastyle=\u0026quot;First Paragraph\u0026quot;\u0026gt; and benefits.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184260005,"name":"Design Verification CCE2","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4720768005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4447836005,"location":{"name":"Bengaluru, Karnataka, India"},"metadata":[{"id":12122734005,"name":"Country","value":"India","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Bengaluru","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Formal Verification","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4720768005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":null,"title":"Tech Lead, Formal Verification","company_name":"Astera Labs","first_published":"2026-08-03T14:23:59-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;We are looking for a Tech Lead, Formal Verification Engineer with 5–10 years of experience to lead formal verification efforts for complex IP and SoC designs. The ideal candidate will have deep expertise in assertion-based verification, property checking, formal proof methodologies, and advanced verification tools. This role requires close collaboration with Architecture, RTL Design, and Design Verification teams to ensure first-pass silicon success for Astera Labs\u0026#39; next-generation connectivity and AI infrastructure products.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Develop comprehensive formal verification plans from architecture and design specifications by identifying critical design properties, protocol requirements, and micro-architectural invariants.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop and execute formal verification environments, assertions, properties, and checkers.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive proof convergence through advanced abstraction and complexity reduction techniques.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with RTL designers, architects, and verification teams to understand design intent and verification requirements.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Evaluate, deploy, and scale formal verification methodologies, flows, and tools across projects.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Improve verification productivity through reusable methodologies, automation, and best practices.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ensure comprehensive design correctness and provide technical leadership and mentorship across multiple projects.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive bug triage, root-cause analysis, and resolution in collaboration with cross-functional teams.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support project planning by estimating verification effort, tracking execution progress, identifying risks, and driving mitigation plans.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Participate in design reviews and contribute to verification sign-off strategies and quality metrics.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Promote assertion-driven design practices and formal verification adoption across engineering teams.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Qualifications\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s or\u0026amp;nbsp;Master’s\u0026amp;nbsp;degree in Electronics, Electrical Engineering, Computer Engineering, or a related field.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;5-10 experience in semiconductor verification, including significant formal verification experience.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Expert knowledge of SystemVerilog, SVA,Verification planning \u0026amp;amp; closure and ABV verification techniques.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience with one or more formal verification tools – JG, VCF preferably.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience verifying complex protocols, control logic, and SoC or subsystem-level designs.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong scripting skills in Python, Perl, Tcl, or Shell.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent analytical, debugging, and problem-solving capabilities\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience leading technical efforts or mentoring team members.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong communication and cross-functional collaboration skills.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience with industry-standard formal verification tools such as JasperGold, VC Formal, or equivalent solutions.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience verifying high-speed protocols and interfaces including PCIe®, UALink™, CXL®, Ethernet, SerDes, or related technologies.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of NoC architectures, cache coherency protocols, memory subsystems, and interconnect fabrics.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with formal bug hunting, proof-based verification, and coverage-driven verification methodologies.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Prior experience leading technical teams and mentoring engineers.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Exposure to simulation, emulation, and the broader verification lifecycle is a plus.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Track record of contributing to successful silicon tape-outs.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184232005,"name":"Compute Connectivity Engineering 1","child_ids":[],"parent_id":null}],"offices":[{"id":4049113005,"name":"Bengaluru","location":"India","child_ids":[],"parent_id":4052109005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4720848005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4447883005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Packaging Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4720848005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2026-109","title":"Tech Lead Optical Test Engineer ","company_name":"Astera Labs","first_published":"2026-08-03T18:18:25-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Job Summary\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;We are seeking a motivated and hands-on \u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Tech Lead – Optical Test Engineer\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; to contribute to the development and deployment of optical test solutions for silicon photonics devices and optical modules. This role will support definition of test methodologies, drive key portions of test development, and lead technical efforts within a broader test organization.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;The ideal candidate has solid experience in optical testing, strong problem-solving skills, and the ability to collaborate across teams to enable efficient characterization, validation, and production testing.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Define and implement optical test architectures and test flows across optical wafer probe test, package level test \u0026amp;amp; characterization and optical module validation.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Execute characterization and qualification testing of CPO components and assemblies.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Perform high-speed optical measurements including insertion loss, return loss, extinction ratio, eye diagram analysis, BER testing, and optical modulation amplitude (OMA).\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Characterize optical performance parameters such as wavelength accuracy, channel spacing, spectral linearity, and crosstalk for WDM-based CPO architectures.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Design and build optical test stations incorporating fiber alignment systems, optical switches, tunable lasers, optical spectrum analyzers, high-speed oscilloscopes, and BER testers.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Develop test automation software, automated test scripts \u0026amp;amp; frameworks using Python, LabVIEW, MATLAB, or similar platforms.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Implement high-throughput test solutions suitable for wafer-scale and production-level testing.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Analyze large-scale optical test data to identify trends, failure modes, and yield-limiting factors.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Generate statistical reports (Cpk, GR\u0026amp;amp;R, SPC) to monitor process stability and test repeatability.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Collaborate with design and process engineering teams to provide feedback for performance optimization.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Create and maintain test documentation, SOPs, and knowledge base articles.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Interface with external suppliers and foundries on silicon photonics wafer-level test requirements.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Participate in design reviews to ensure testability and provide DFT (Design for Test) recommendations.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Required Qualifications\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;M.S. or Ph.D. in Electrical Engineering, Optical Engineering, Physics, Photonics, or a related discipline.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;5–7+ years of experience in optical testing, photonic device characterization, or optical transceiver development.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Strong understanding of silicon photonics devices (modulators, photodetectors, multiplexers, grating couplers, edge couplers).\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Hands-on experience with optical test equipment: OSA, OMA, tunable lasers, polarization controllers, power meters, high-speed real-time oscilloscopes, BERT/pattern generators.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Proficiency in high-speed optical link testing (100G/lane and above, PAM4, NRZ).\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Programming skills in Python, MATLAB, LabVIEW, or C/C++ for test automation.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;7\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Knowledge of optical communication standards (IEEE 802.3, OIF-CEI, CMIS).\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;6\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;8\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Familiarity with statistical analysis methods and data visualization tools.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Preferred Qualifications\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience specifically with co-packaged optics or on-board optics architectures.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience with wafer-level optical probing and testing tool hardware \u0026amp;amp; software as well as automated photonics test platforms.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;7\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience in transitioning test processes from lab/prototype to high-volume manufacturing (HVM).\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;p8i6j01 paragraph\u0026quot;\u0026gt;Salary range is $185,000 to $240,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184399005,"name":"Signal Connectivity Group","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4666076005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4421635005,"location":{"name":"Shanghai Shi, China"},"metadata":[{"id":12122734005,"name":"Country","value":"India","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Bangalore","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":"Compute Connectivity Engineering 2","value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Signal and Power Integrity","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4666076005,"updated_at":"2026-09-29T18:22:10-04:00","requisition_id":"2312-2","title":"Tech Lead PCB Layout Engineer","company_name":"Astera Labs","first_published":"2026-02-25T19:31:49-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;At Astera Labs, we seek a motivated and experienced \u0026lt;strong\u0026gt;Tech Lead PCB Layout Engineer \u0026lt;/strong\u0026gt;to work on our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role, you will design complicated PCB layout across multiple fields including high-speed interfaces, power, high-density interconnect, etc. This position will be onsite.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong academic/technical background in electrical engineering or similar degree; Bachelor’s is required;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;10+ years of experience designing top-tier complex PCB (40,000+ pins, 30+ layer count) across high-speed differential pairs, RF, high-power, high-density interconnect (HDI), etc.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Capable of full PCB design process from feasibility study, to DFM and Gerber release.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Have a proven track record with achieving layout design for signal integrity, power integrity, DFT, and DFM.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Cross-functional design mentality with the electrical design community to develop systems.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Self-starting, professional, and hands-on work ethic that can execute intense design work in a dynamic environment.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven track record solving problems independently, preferably as a tech lead.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Prefer previous work experience with oversee customers and proficient in speaking/written English.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Proficient in PCB designs with PCIe Gen5/6, Ethernet 112G/224G PAM4, and DDR4/5 applications.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficient in advanced PCB technologies such as micro-vias, blind vias, any layer HDI, back-drilling, and sequential lamination, step gold finger, etc.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Master EDA tools including Cadence Allegro, Polar SI9000, CAM350 or similar DFM inspection tools, and AutoCAD.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficient in PCB design rules, constraint manager, checklist, etc.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Possess decent speaking and written English skills.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiar with PCB manufacture and PCB assembly process and capable of handling PCB/PCBA EQ.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Your base salary will be determined based on your experience and the pay of employees in similar positions.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184651005,"name":"Advanced Hardware Engineering (CHN_Hardware Engineering_AHE)","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4727004005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4450975005,"location":{"name":"Hyderabad, Telangana, India"},"metadata":[{"id":12122734005,"name":"Country","value":"India","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Hyderabad","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"System Validation","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4727004005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":null,"title":"Tech Lead, STA","company_name":"Astera Labs","first_published":"2026-09-15T12:40:17-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;h3\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;u\u0026gt;Tech Lead STA Engineer\u0026lt;/u\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/h3\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Location - Hyderabad\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Experience - 6-14 years\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is hiring a \u0026lt;strong\u0026gt;Principal Engineer, Static Timing Analysis\u0026lt;/strong\u0026gt; to own top-level timing closure and signoff for our next-generation connectivity silicon powering rack-scale AI infrastructure. In this role, you\u0026#39;ll drive full-chip STA strategy across advanced process nodes, partner with physical design, RTL, DFT, and CAD teams, and ensure first-pass timing success on some of the most complex SoCs in the industry.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This is a high-impact technical leadership role at a hyper-growth company purpose-built for AI connectivity. Your work directly enables the PCIe, CXL, UALink, and Ethernet platforms that hyperscalers depend on — and you\u0026#39;ll have the ownership, influence, and tooling to do the best work of your career.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Full-Chip STA Signoff \u0026amp;amp; Timing Closure\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Own end-to-end top-level STA signoff across multiple modes, corners, and operating conditions (MMMC) for complex AI connectivity SoCs\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive timing convergence on advanced process nodes (5nm/4nm/3nm and below) from early floorplan through tapeout\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Analyze and resolve setup, hold, recovery/removal, and clock-domain crossing (CDC) timing violations at the chip level\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Methodology \u0026amp;amp; Flow Development\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Define and evolve STA methodology, constraints (SDC) strategy, and signoff criteria across the organization\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop and automate flows using PrimeTime, PrimeTime SI, and related signoff tools for crosstalk, noise, and IR-aware timing\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Establish best practices for hierarchical STA, ETM/IPXACT model generation, and budgeting across blocks\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional Technical Leadership\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Partner with Physical Design, RTL, DFT, CAD, and Package teams to drive timing-aware design decisions from architecture through tapeout\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Review and sign off on block-level timing handoffs, ensuring consistency between block and top-level closure\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with low-power design teams on UPF/CPF, multi-voltage, and clock-gating timing implications\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Mentorship \u0026amp;amp; Technical Strategy\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Mentor STA engineers and review timing reports, ECOs, and signoff collateral\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive root-cause analysis of silicon timing issues and feed learnings back into methodology\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Influence tool selection, EDA vendor engagements, and STA roadmap for future products\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, Electronics Engineering, or related field\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;6+ years of hands-on experience in Static Timing Analysis on complex ASIC/SoC designs\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven track record of full-chip top-level STA signoff on at least one tapeout at advanced nodes (7nm or below)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep expertise with PrimeTime, PrimeTime SI, and SDC constraint development\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of clocking architectures, CDC, OCV/AOCV/POCV, crosstalk, and IR-aware timing\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency in scripting (Tcl, Python, Perl) for STA flow automation and report analysis\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Master\u0026#39;s degree in Electrical Engineering or related field\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with high-speed connectivity SoCs (PCIe Gen 6/7, CXL, UALink, or Ethernet)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with hierarchical STA, ETM/ILM models, and timing budgeting across large partitions\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with low-power signoff (UPF/CPF), multi-voltage domains, and DVFS timing implications\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong cross-functional collaboration and mentorship skills in a fast-paced product environment\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184347005,"name":"System Validation CCE1","child_ids":[],"parent_id":null}],"offices":[{"id":4065038005,"name":"Hyderabad","location":"India","child_ids":[],"parent_id":4052109005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4728420005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4451708005,"location":{"name":"Bengaluru, Karnataka, India"},"metadata":[{"id":12122734005,"name":"Country","value":"India","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Bengaluru","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Design Verification","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4728420005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":null,"title":"Tech Lead– Verification Methodology/CAD","company_name":"Astera Labs","first_published":"2026-08-27T15:32:18-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;TechLead– Verification Methodology / CAD / Automation Engineer\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt; - \u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;6–12\u0026amp;nbsp;years\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Job Summary\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;We are looking for a\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Tech Lead – Verification Methodology/CAD/Automation Engineer\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026amp;nbsp;to drive verification infrastructure,\u0026amp;nbsp;methodology, automation, and productivity across IP and SoC verification teams.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;The candidate will build scalable verification frameworks, automate verification workflows, improve regression infrastructure, and partner with design verification teams to\u0026amp;nbsp;establish\u0026amp;nbsp;efficient and reusable methodologies.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;9\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Own and drive\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;verification\u0026amp;nbsp;methodology\u0026amp;nbsp;and infrastructure\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026amp;nbsp;across projects.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;9\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Develop scalable frameworks for simulation, regression, coverage, debug, and verification signoff.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;9\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Build and\u0026amp;nbsp;maintain\u0026amp;nbsp;verification\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;CAD/automation flows\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;9\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Develop automation scripts and tools using\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Python,\u0026amp;nbsp;Tcl, Perl, Shell\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;, and/or C++.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; 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data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;9\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Develop infrastructure for large-scale\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;UVM/SystemVerilog\u0026amp;nbsp;verification environments\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; 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data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;9\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;8\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Integrate simulation, lint, CDC/RDC, formal, coverage, and other verification tools into common workflows.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;9\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;9\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Develop dashboards and metrics for\u0026amp;nbsp;verification\u0026amp;nbsp;quality, coverage, regression health, and project status.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;9\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;10\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Debug infrastructure and tool-flow issues and provide rapid support to verification teams.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;9\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;11\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Establish reusable verification components, scripts, libraries, and\u0026amp;nbsp;methodology\u0026amp;nbsp;guidelines.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;9\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;12\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Drive adoption of best practices across multiple verification teams.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;9\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;13\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Evaluate new verification technologies and tools and recommend improvements.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;9\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;14\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Work closely with EDA vendors to troubleshoot tool issues and improve flows.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;9\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;15\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Support migration and integration of new EDA tool versions and methodologies.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;9\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;16\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Develop documentation and training for verification teams.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;9\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;17\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Mentor\u0026amp;nbsp;verification\u0026amp;nbsp;CAD/methodology\u0026amp;nbsp;engineers and provide technical leadership.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Required Technical Skills\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;10\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Strong experience in\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;verification\u0026amp;nbsp;methodology, CAD, and automation\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;10\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Strong programming/scripting skills in\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Python,\u0026amp;nbsp;Tcl, Perl, Shell\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;, and preferably C/C++.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;10\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Strong understanding of\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;SystemVerilog/UVM\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;10\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience with simulation tools such as\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;VCS,\u0026amp;nbsp;Xcelium, Questa\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;, or equivalent.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;10\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience building and\u0026amp;nbsp;maintaining\u0026amp;nbsp;regression infrastructure.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;10\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Strong knowledge of coverage collection and analysis.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;10\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;7\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Understanding of verification flows including:\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;10\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Simulation\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;10\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;UVM\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;10\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Lint\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;10\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;CDC/RDC\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;10\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Formal\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;10\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Code/functional coverage\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;10\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;7\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Regression\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;10\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;8\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Debug\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;10\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;8\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Strong Linux/Unix environment experience.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;10\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;9\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Excellent automation and problem-solving skills.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Preferred Experience\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;11\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience with large-scale\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;SoC/IP verification environments\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;11\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience integrating multiple EDA tools into a unified verification flow.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;11\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience with CI/CD infrastructure such as\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Jenkins, GitLab CI, or equivalent\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;11\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience with distributed/parallel regression infrastructure.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;11\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience with cloud-based or scalable\u0026amp;nbsp;compute\u0026amp;nbsp;environments.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;11\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Knowledge of databases, dashboards, APIs, or web-based verification infrastructure is an advantage.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;11\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;7\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience working with EDA vendors and managing tool-flow issues.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Leadership Expectations\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;12\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Act as the technical owner for\u0026amp;nbsp;verification\u0026amp;nbsp;methodology\u0026amp;nbsp;and automation.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;12\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Identify\u0026amp;nbsp;opportunities to improve\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;verification\u0026amp;nbsp;productivity, quality, and turnaround time\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;12\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Define and enforce\u0026amp;nbsp;verification\u0026amp;nbsp;methodology\u0026amp;nbsp;standards.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;12\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Mentor engineers and drive adoption of common frameworks.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;12\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Work across multiple projects and teams to solve infrastructure challenges.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;12\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Strong ability to balance immediate project requirements with long-term\u0026amp;nbsp;methodology\u0026amp;nbsp;improvements.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Education\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;B.E./B.Tech/M.E./M.Tech\u0026amp;nbsp;in\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Electronics, Electrical\u0026amp;nbsp;Engineering, Computer Science, Computer Engineering, VLSI\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;, or\u0026amp;nbsp;a related\u0026amp;nbsp;discipline.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184260005,"name":"Design Verification CCE2","child_ids":[],"parent_id":null}],"offices":[{"id":4049113005,"name":"Bengaluru","location":"India","child_ids":[],"parent_id":4052109005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4632063005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4405844005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Program Management","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4632063005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2139","title":"Technical Chief of Staff for ASIC Engineering","company_name":"Astera Labs","first_published":"2025-11-19T19:24:24-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Summary\u0026lt;/strong\u0026gt;\u0026lt;br\u0026gt;We are seeking a technically strong Chief of Staff to the Head of Engineering who will also lead Engineering Program Management across Silicon Engineering. This role is a force-multiplier for Engineering leadership — driving org scale, decision velocity, and execution rigor. The ideal candidate brings deep technical fluency, structured problem-solving, and the ability to drive outcomes through influence rather than hierarchy. The role is fully in person in San Jose.\u0026lt;br\u0026gt;\u0026lt;br\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Responsibilities — What You Will Own\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;1) Chief of Staff to Head of Engineering\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;padding-left: 40px;\u0026quot;\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Drive operational cadence: engineering all hands, staff meetings, agenda/material prep, tech talks, university engagements, action follow-through, and leadership syncs.\u0026amp;nbsp;\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Frame and resolve high-leverage decisions — proactively surface blockers (technical, operational, organizational) before they escalate.\u0026amp;nbsp;\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Manage escalations and organizational friction — diagnose root causes, coordinate resolution paths, and ensure durable fixes.\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Partner cross-functionally with Hardware, Product, and Quality teams to ensure clarity of communication, alignment on priorities, and disciplined follow-through on decisions.\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Support org design, headcount planning, and hiring prioritization for engineering teams.\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Maintain alignment across functions through clear messaging and communication, validate exitance and validation of processes\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Navigate org dynamics, build trust, and constructively challenge assumptions; maintain psychological safety.\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Support the head of engineering with administrative and org related activities\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;2) Lead ASIC Tape out Management \u0026amp;nbsp;(Silicon Programs)\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;padding-left: 40px;\u0026quot;\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Status management — collect and track status across functions contributing to ASIC tapeouts.\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Milestone tracking — maintain methodology checklists and boundary agreements to ensure schedule adherence.\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;IP and vendor tracking — own visibility into IP deliveries, version inventory, vendor issues, and escalation loops.\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Quality \u0026amp;amp; documentation — monitor quality KPIs, ensure engineering documentation completeness.\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Requirements tracking — ensure PRDs/features are captured, tracked, baselined.\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Resource monitoring — track compute, hardware, storage consumption and thresholds.\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Internal reporting — generate status reporting for Silicon Engineering leadership.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;br\u0026gt;\u0026lt;strong\u0026gt;3) Influence Without Authority\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;padding-left: 40px;\u0026quot;\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Drive cross-engineering outcomes through credibility, clarity, and follow-through — not hierarchy.\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Create order in ambiguous spaces; shape scope where it is undefined.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;padding-left: 40px;\u0026quot;\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;10+ years in semiconductor/SoC/ASIC or adjacent high-complexity engineering environment (e.g., CPU/IP/System companies).\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Proven success in Chief of Staff, Staff Program Manager, TPM Director, or similar technical leadership-enablement role. \u0026amp;nbsp;\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Strong technical acumen — able to understand engineering trade-offs and make decisions with limited information, challenge assumptions, and earn credibility with senior ICs.\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Demonstrated experience running program cadence for complex silicon programs (tapeout, IP integration, etc.).\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Proven ability to organize complex workflows and drive consistent follow-through.\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;High EQ and organizational awareness; can navigate tension and align diverse viewpoints.\u0026amp;nbsp;\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Exceptional written/verbal communication, structured thinking, and execution discipline.\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Prior experience in leading RTL2GDSII chip design is a huge plus.\u0026lt;br\u0026gt;\u0026lt;br\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;What Success Looks Like\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;padding-left: 40px;\u0026quot;\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Engineering leadership spends more time on strategic and technical decisions, less on coordination.\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Milestones hit with fewer escalations and clearer accountability.\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Status, risks, and decisions are crisp — never ad hoc or late.\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Teams feel supported, not policed — trust increases, friction decreases without compromising on accountability \u0026amp;nbsp;.\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Ambiguity decreases over time as clarity and execution rhythm scale with the org.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Salary range is $216,000 to $300,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"California","child_ids":[],"parent_id":4019546005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4707254005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4441276005,"location":{"name":"Toronto, Ontario, Canada"},"metadata":[{"id":12122734005,"name":"Country","value":"Canada","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Toronto","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":"Silicon Engineering SCE","value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Physical Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4707254005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2656","title":"Technical Lead Physical Design Engineer ","company_name":"Astera Labs","first_published":"2026-07-01T17:48:47-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;As an Astera Labs Technical Lead Physical Design Engineer you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs\u0026#39; portfolio of connectivity ASICs used in the world\u0026#39;s leading cloud service providers, server and network OEMs. This role requires end-to-end STA ownership across design stages, deep technical expertise, and close collaboration with RTL, physical design, and verification teams to ensure robust full-chip timing convergence. This role is fully on-site and in-person.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Drive timing closure from RTL through sign-off, ensuring robust timing across complex SoCs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop and validate SDC constraints, including MMMC setup, to enable accurate and efficient STA analysis.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Define and manage I/O timing budgets across hierarchical designs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Apply advanced sign-off methodologies at TSMC 7nm and below, including OCV/AOCV and PVT effects.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Leverage ETM libraries for hierarchical timing analysis and correlation, balancing runtime and accuracy.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Provide actionable timing feedback at both block and full-chip levels, including root cause analysis and ECO guidance.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Manage large-scale multi-corner/multi-mode STA runs with automation, partitioning, and efficient resource usage.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Generate and validate timing ECOs, partnering with physical design and RTL teams for quick closure.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Partner closely with design, implementation, and verification teams to drive timing convergence, providing sign-off level expertise and guidance.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s in Electrical Engineering or Computer Science required; Master’s preferred.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;≥5 years of experience in timing analysis and sign-off for complex SoCs in Server, Storage, or Networking applications.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Expertise in timing constraints, STA methodology, and timing closure at both block and full-chip level.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows in advanced nodes (7nm or below).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency with Cadence and/or Synopsys physical design/STA toolchains.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong scripting ability (Tcl, Python, Perl).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ability to work independently with strong prioritization and a professional, customer-focused mindset.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with high-speed SERDES and Ethernet PHY timing challenges.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of ECO methodologies, DFT tools, and test coverage analysis.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience working with IP vendors for both RTL and hard-macro integration.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;SystemVerilog/Verilog familiarity.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;The base salary range is $140,000 CAD – $180,000.00 CAD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. \u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000119005,"name":"Toronto","location":"Canada","child_ids":[],"parent_id":4004709005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4730505005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4452768005,"location":{"name":"Aachen, North Rhine-Westphalia, Germany"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":null,"value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":null,"value_type":"single_select"}],"id":4730505005,"updated_at":"2026-09-23T16:03:01-04:00","requisition_id":"2716","title":"Test Engineer","company_name":"Astera Labs","first_published":"2026-09-10T12:27:33-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot; data-olk-copy-source=\u0026quot;MessageBody\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Job Title:\u0026lt;/strong\u0026gt; Test Engineer\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Location\u0026lt;/strong\u0026gt;: Aachen, Germany\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Job Type:\u0026lt;/strong\u0026gt; Full-time\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;About the Role:\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;\u0026lt;span data-olk-copy-source=\u0026quot;MessageBody\u0026quot;\u0026gt;We are looking for a Test Engineer to join our high-tech assembly and test production facility. In this role, you will be responsible for validating that every device meets our rigorous performance and reliability standards before it reaches the customer. You will work closely with design and production teams to implement test solutions, troubleshoot failures, and optimize test coverage for high-volume manufacturing.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;Key Responsibilities:\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot; data-olk-copy-source=\u0026quot;MessageBody\u0026quot;\u0026gt;Test Execution \u0026amp;amp; Monitoring: Execute and monitor production test programs on Automated and Semi Auto Test Equipment\u0026amp;nbsp; to identify manufacturing defects.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;Troubleshooting \u0026amp;amp; Debugging: Perform basic hardware and software debugging to isolate the root cause of test failures, distinguishing between equipment malfunctions and actual product defects.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;Yield \u0026amp;amp; Data Analysis: Analyze test data and performance metrics to identify trends, monitor process stability, and support yield improvement initiatives.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;NPI Support: Assist in the bring-up and qualification of new products by helping to develop and validate test plans, scripts, and hardware interfaces.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;Maintenance \u0026amp;amp; Calibration: Ensure test systems and fixtures are properly calibrated and performing as intended to maintain accurate data collection.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;Documentation: Maintain detailed documentation for test procedures, bug tracking, and compliance reports in alignment with industry standards like ISO.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;\u0026amp;nbsp;Qualification:\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;Education: Bachelor’s degree in Electrical Engineering, Electronics, Computer Engineering, or a related technical field.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;Experience: 0–2 years of experience in electronics testing or manufacturing. Relevant internships or university projects involving measurement or lab instrumentation are highly preferred.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Technical Skills\u0026lt;/strong\u0026gt;:\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;Basic programming and scripting skills (e.g., Python, C/C++, or LabVIEW) for test automation.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;Familiarity with lab equipment such as oscilloscopes, digital multimeters, and signal generators.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;Understanding of digital logic, CMOS fundamentals, and semiconductor device physics.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;Soft Skills:\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;Strong analytical mindset with an interest in finding and solving complex \u0026quot;puzzle-like\u0026quot; hardware problems.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;Effective communication for reporting technical issues to cross-functional engineering teams.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot; data-olk-copy-source=\u0026quot;MessageBody\u0026quot;\u0026gt;What We Offer:\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;Hands-on experience with advanced semiconductor testing technology and ATE platforms.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;Structured career progression and mentorship from senior process engineers.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;Competitive compensation package and comprehensive benefits.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;font-family: Aptos; font-size: small;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4184399005,"name":"Signal Connectivity Group","child_ids":[],"parent_id":null}],"offices":[{"id":4056756005,"name":"Aachen","location":"Germany","child_ids":[],"parent_id":4056755005}],"ai_disclaimer":null,"include_ai_disclaimer":null,"ai_opt_out_request_url":null}],"meta":{"total":176}}