{"jobs":[{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4619972005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4399898005,"location":{"name":"Singapore, Singapore"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"IC Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Early Career","value_type":"single_select"}],"id":4619972005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2088","title":"Analog/Mixed-Signal Engineer - SerDes","company_name":"Astera Labs","first_published":"2026-05-04T21:12:39-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Job Description:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As an Analog/Mixed-Signal IC Design Engineer , you will be part of a key team designing sophisticated advanced node CMOS products. Your responsibilities will include developing and verifying circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs to meet performance targets. You will also work on analog and clocking blocks for connectivity applications, using industry-standard tools like Spectre and MATLAB. The company seeks a highly motivated designer for this role\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Pursuing a Master’s or PhD degree in EE is preferred\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Desired Experience:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience in designing high-speed mixed-signal circuits including ADC/DAC data converters, RX front-end, TX driver/serializer, low-jitter PLLs, TX/RX calibration, low-jitter CLK distribution are other high-speed analog circuits is a must\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Have a deep understanding of biasing, band-gaps, reference circuits, opamps, comparators and other analog circuits\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Solid track-record for implementation of analog circuits high-speed data transmission.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Design and tapeout experience in advanced CMOS nodes (ex. 20nm or newer) is a must\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Solid fundamentals in detailed transistor-level design, feedback/stability analysis, and noise/jitter analysis.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of TIA design and drivers for optical applications is highly desirable\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience in RFIC design for wireless or wireline communication systems is highly desirable.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong technical independent contributor with a proven ability to drive results.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent teamwork, presentation, and documentation skills.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ability to collaborate with global teams across multiple time zones and deliver under pressure with strict deadlines.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong experience in lab chip bring-up and debugging efforts.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Relevant research publications and/or patents in analog or RF IC design.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity in programming/scripting languages such as Python, Matlab, or C.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with PCB design.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with Verilog RTL or DSP design concepts.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of optical transceivers.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Expertise in ESD protection techniques and IC packaging methodologies.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4135671005,"name":"SerDes","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4052115005,"name":"Singapore City, Singapore","location":"Singapore","child_ids":[],"parent_id":4050465005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4605619005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4393047005,"location":{"name":"Irvine, CA or San Jose, CA"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"IC Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Internship","value_type":"single_select"}],"id":4605619005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"1951","title":"Analog/Mixed-Signal Engineer - SerDes (PhD Intern 2026)","company_name":"Astera Labs","first_published":"2025-09-04T18:28:37-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Job Description:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As an Analog/Mixed-Signal IC Design Engineer Intern, you will be part of a key team designing sophisticated advanced node CMOS products. Your responsibilities will include developing and verifying circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs to meet performance targets. You will also work on analog and clocking blocks for connectivity applications, using industry-standard tools like Spectre and MATLAB. The company seeks a highly motivated designer for this role\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Pursuing a Master’s or PhD degree in EE is preferred\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Desired Experience:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience in designing high-speed mixed-signal circuits including ADC/DAC data converters, RX front-end, TX driver/serializer, low-jitter PLLs, TX/RX calibration, low-jitter CLK distribution are other high-speed analog circuits is a must\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Have a deep understanding of biasing, band-gaps, reference circuits, opamps, comparators and other analog circuits\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Solid track-record for implementation of analog circuits high-speed data transmission.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Design and tapeout experience in advanced CMOS nodes (ex. 20nm or newer) is a must\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Solid fundamentals in detailed transistor-level design, feedback/stability analysis, and noise/jitter analysis.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of TIA design and drivers for optical applications is highly desirable\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience in RFIC design for wireless or wireline communication systems is highly desirable.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong technical independent contributor with a proven ability to drive results.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent teamwork, presentation, and documentation skills.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ability to collaborate with global teams across multiple time zones and deliver under pressure with strict deadlines.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong experience in lab chip bring-up and debugging efforts.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Relevant research publications and/or patents in analog or RF IC design.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity in programming/scripting languages such as Python, Matlab, or C.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with PCB design.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with Verilog RTL or DSP design concepts.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of optical transceivers.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Expertise in ESD protection techniques and IC packaging methodologies.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;The pay range for this role is $55-65/hour + $500 housing stipend + cash relocation bonus (dependent on location)\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4135671005,"name":"SerDes","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4050370005,"name":"Irvine","location":"Irvine, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4672401005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4424395005,"location":{"name":"India"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"IC Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4672401005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2360","title":"Analog/Mixed-Signal IC Design","company_name":"Astera Labs","first_published":"2026-03-12T04:21:15-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;div\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-olk-copy-source=\u0026quot;MessageBody\u0026quot;\u0026gt;Job Overview:\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;p\u0026gt;As an Analog Mixed-Signal IC Layout Lead Engineer, you will play a critical role in designing advanced node Bi-CMOS / CMOS products. You will be responsible for managing chip top-level layout and integration along with block level layout design and ensuring successful tapeout. You will work to build state-of-the art high speed circuits minimizing layout parasitics, while applying techniques to reduce skew and crosstalk. Meeting EM/IR compliance requirements is essential. You will ensure strict adherence to DRC, LVS, ANT, and density rules. Additionally, awareness of ESD and latch-up design practices is expected to ensure robust and reliable layout implementations. You will apply a solid foundation in device physics, along with demonstrating a strong three-dimensional understanding of device layout.\u0026lt;/p\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;p\u0026gt;You will collaborate with a dynamic, cross-functional team of analog designers and layout engineers across multiple time zones. We are looking for a highly motivated, team-oriented individual who thrives in a collaborative environment.\u0026lt;/p\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;ul type=\u0026quot;disc\u0026quot;\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s degree or advanced diploma in Electrical Engineering (EE)\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Experience:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;ul type=\u0026quot;disc\u0026quot;\u0026gt;\n\u0026lt;li\u0026gt;8+ years of experience in high-speed analog IC layout using Cadence Virtuoso\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Prior experience with BiCMOS layout is strongly preferred\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven experience handling at least one chip top-level through tapeout\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency in layout extraction and parasitic analysis for high-speed circuits\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Awareness of EMIR and antenna DRC rule-compliant layout practices\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with Cadence SKILL and TCL scripting is highly recommended\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4135671005,"name":"SerDes","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4049113005,"name":"Bengaluru","location":"Bengaluru, India","child_ids":[],"parent_id":4052109005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4666729005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4421887005,"location":{"name":"Singapore, Singapore"},"metadata":[{"id":12122734005,"name":"Country","value":"Singapore","value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Layout","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Early Career","value_type":"single_select"}],"id":4666729005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2322","title":"Analog / Mixed-Signal Layout Engineer","company_name":"Astera Labs","first_published":"2026-05-12T01:32:05-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;We are looking for a Analog / Mixed-Signal Layout Engineer\u0026lt;strong\u0026gt;\u0026amp;nbsp;\u0026lt;/strong\u0026gt;to join our ASIC team working on the forefront of high-performance compute and networking standards in advanced CMOS process nodes. The ideal candidate will have an impeccable hardware engineering background with an emphasis on VLSI and/or computer architecture. We are looking for experience in design, verification, and validation of real-world systems.\u0026amp;nbsp; Exposure to high-speed interfaces PCIE, DDR, HBM, Serdes technologies would be great to have. Above all, curiosity and ability to learn is a must. In this position you will be responsible for design and/or verification of blocks using leading edge methodology and tools.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic qualifications: \u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Pursuing BS or MS in EE/CS or related fields.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hardware engineering background with an emphasis in VLSI or Computer Architecture.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Exposure to Digital design or verification, VLSI design and circuits, Computer Architecture.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required experience\u0026lt;/strong\u0026gt;:\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Hands-on and knowledge of RTL design languages and tools including Verilog, System Verilog.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with verification methodologies like UVM, functional coverage, assertions.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with any of the scripting languages Python, Perl etc and hands-on experience in C/C++.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred experience: \u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Real-world design and/or verification in Verilog/System Verilog.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of high-speed interfaces like PCIe, DDR, HBM, Serdes.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with Synopsys EDA tools.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4135671005,"name":"SerDes","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4052115005,"name":"Singapore City, Singapore","location":"Singapore","child_ids":[],"parent_id":4050465005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4692326005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4433813005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose (HQ)","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Human Resources","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4692326005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2504","title":"Benefits Manager","company_name":"Astera Labs","first_published":"2026-05-04T21:07:12-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;Astera Labs is seeking a strategic and knowledgeable Benefits Manager to join our Human Resources team in San Jose, California. As we continue our hyper-growth trajectory as a leader in AI infrastructure connectivity, this role will be instrumental in designing, managing, and optimizing our global benefits programs that attract and retain world-class talent.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This is a high-impact position that goes beyond day-to-day benefits administration. You\u0026#39;ll serve as a strategic partner to HR leadership, analyzing market trends, ensuring compliance across multiple geographies, and driving initiatives that enhance\u0026amp;nbsp;the employee\u0026amp;nbsp;experience. The ideal candidate brings a global mindset, thrives in a fast-paced environment, and is passionate about building benefits programs that support our rapidly scaling workforce across the US, Canada, Asia, and EMEA.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Benefits Strategy \u0026amp;amp; Program Management\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Develop and execute a comprehensive global benefits strategy aligned with Astera Labs\u0026#39; growth objectives and talent acquisition goals\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Evaluate and benchmark benefits offerings against industry standards and competitors to ensure market competitiveness\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead annual benefits renewal processes, including vendor negotiations and plan design recommendations\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive innovation in benefits offerings to support employee wellbeing and position Astera Labs as an employer of choice\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Global Benefits Coordination\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Oversee end-to-end coordination of benefits programs across all operating regions, including the Canada, Asia, and EMEA, ensuring consistency, equity, and local compliance\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Serve as the primary point of contact for international benefits brokers, third-party administrators, and in-country HR partners\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Harmonize benefit plan designs across geographies while accommodating regional statutory requirements and cultural expectations\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Maintain a centralized benefits governance framework to ensure transparency, auditability, and scalability across all regions\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Retirement Plans (401k) Administration\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Manage the full lifecycle of the company\u0026#39;s 401(k) plan, including plan design, vendor management, compliance testing, and annual reporting (Form 5500)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Partner with the 401(k) plan administrator and investment advisors to ensure the plan remains competitive, compliant, and aligned with employee financial wellness goals\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Oversee employer match programs, vesting schedules, and plan amendments in coordination with Finance and Legal\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ensure compliance with ERISA, IRS regulations, and Department of Labor requirements; manage plan audits and non-discrimination testing\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop and deliver financial literacy and retirement readiness education to help employees maximize their retirement benefits\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Evaluate and expand retirement offerings for international employees, including country-specific pension and provident fund programs\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Paid Time Off (PTO) Program Management\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Design, administer, and continuously improve the company\u0026#39;s PTO programs, including vacation, sick leave, holidays, parental leave, and other leave of absence policies\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ensure PTO policies comply with federal, state, and local regulations across all jurisdictions where Astera Labs operates (including California-specific requirements)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Partner with Payroll and HRIS teams to ensure accurate PTO accrual, tracking, and reporting\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Benchmark PTO offerings against industry peers to maintain competitiveness and support talent attraction and retention\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop clear, accessible PTO communications and manager guides to promote consistent policy application across the organization\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Monitor PTO utilization trends and provide data-driven recommendations to HR leadership to support employee wellbeing and workforce planning\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Global Benefits Administration \u0026amp;amp; Compliance\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Manage day-to-day administration of health, welfare, retirement, and wellness programs across multiple countries\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ensure compliance with federal, state, and international regulations (ERISA, ACA, COBRA, HIPAA, and country-specific requirements)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Partner with external brokers, vendors, and legal counsel to navigate complex regulatory landscapes\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop and maintain benefits policies and procedures to support global scalability\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Analytics \u0026amp;amp; Communication\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Analyze benefits utilization data, cost trends, and employee feedback to inform strategic decisions and optimize program ROI\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop and deliver clear, engaging benefits communications and educational resources for employees\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead open enrollment planning and execution, ensuring a seamless employee experience\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Present benefits insights and recommendations to senior leadership\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional Partnership\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with Finance, Legal, and Payroll teams to ensure accurate benefits accounting and reporting\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Partner with Talent Acquisition to position benefits as a competitive advantage in recruiting top talent\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support M\u0026amp;amp;A activities and international expansion by assessing and integrating benefits programs\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor\u0026#39;s degree in Human Resources, Business Administration, or related field\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;10+ years of progressive experience in benefits administration and strategy\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong knowledge of US benefits regulations and compliance requirements (ERISA, ACA, COBRA, HIPAA)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Demonstrated experience managing 401(k) plans, including compliance testing, vendor oversight, and employee education\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience administering PTO programs across multiple states, with working knowledge of California leave laws\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience managing relationships with benefits brokers, carriers, and vendors\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency with HRIS and benefits administration platforms\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent analytical skills with the ability to translate data into actionable insights\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience coordinating global benefits across multiple countries, including international retirement and leave programs\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience in high-growth technology or semiconductor companies\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong project management skills with ability to manage multiple priorities simultaneously\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Exceptional communication and presentation skills with ability to influence stakeholders at all levels\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Compensation\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Salary range is \u0026lt;strong\u0026gt;$140,000 to $195,000\u0026lt;/strong\u0026gt; depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives, and benefits.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4000202005,"name":"HR","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4703738005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4439593005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose (HQ)","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Sales Operations","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Contract","value_type":"single_select"}],"id":4703738005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2623","title":"Category Sourcing Manager – Capital Equipment \u0026 IT (6-Month Contract)","company_name":"Astera Labs","first_published":"2026-06-05T19:22:12-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Role Overview\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Astera Labs is seeking a\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Contract Sourcing Manager\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026amp;nbsp;to support sourcing and procurement activities across\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;capital equipment, IT hardware, and corporate services\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;. This is a\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;6-month contract role\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026amp;nbsp;designed to provide hands-on execution support during a period of rapid growth and infrastructure scaling.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;This role will focus on\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;supplier sourcing, commercial negotiations, and procurement execution\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;, working closely with engineering, IT, facilities, and operations teams. The ideal candidate brings\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;6+ years of diverse sourcing experience\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;, with a strong emphasis on\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;hardware, capital equipment, and technical environments\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;This role is highly execution-oriented and requires the ability to independently manage sourcing initiatives, drive timelines, and deliver cost-effective and scalable supplier solutions.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;High-performing individuals may be considered for full-time conversion\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026amp;nbsp;based on business needs.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;13\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Lead sourcing and procurement activities across:\u0026amp;nbsp;\u0026lt;/span\u0026gt; \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;13\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;Capital equipment (lab, test, and infrastructure equipment) \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;13\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;IT hardware and related services \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;13\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;Select corporate services categories \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;13\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;Execute end-to-end sourcing processes including supplier identification, RFQs/RFPs, cost analysis, negotiation, and award \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;13\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;Partner with engineering and IT stakeholders to understand technical requirements and ensure supplier alignment \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;13\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;Manage supplier relationships, including onboarding, performance tracking, and issue resolution \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;13\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;Support purchase order execution, delivery tracking, and resolution of procurement-related issues \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;13\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;Drive cost savings, value engineering, and cycle-time improvements across sourcing activities \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;13\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;Ensure procurement compliance with internal policies, contracts, and systems (e.g., Coupa, Oracle, or similar) \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;13\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;Collaborate with global procurement teams to align on preferred vendors, strategies, and contracts \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;13\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;Provide insights into supply market dynamics, pricing trends, and sourcing risks\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Basic Qualifications\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;14\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Bachelor’s degree in Business, Supply Chain, Engineering, or related field\u0026lt;/span\u0026gt; \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;14\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;6+ years of sourcing, procurement, or supply chain experience\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt; \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;14\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;Demonstrated experience sourcing \u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;hardware, capital equipment, or technical products/services\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt; \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;14\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;Experience managing RFQs, negotiations, supplier selection, and contracting \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;14\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;Strong operational execution skills with ability to manage multiple priorities in a fast-paced environment \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;14\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;Familiarity with procurement systems (e.g., Coupa, Oracle, SAP, or similar)\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Preferred Qualifications\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;15\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience supporting semiconductor, hardware, or data center environments\u0026lt;/span\u0026gt; \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;15\u0026quot; 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data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;15\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;Ability to quickly ramp and operate independently in a high-growth environment\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Why Join Us?\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;16\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Opportunity to contribute to a high-growth company scaling AI infrastructure\u0026lt;/span\u0026gt; \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;16\u0026quot; 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By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Astera Labs is seeking an Senior Director OR Associate Vice President, Product Technical Lead (Chip Lead) to drive the end-to-end success of our next-generation UALink switching products in San Jose. This is an executive technical leadership role where you will connect architecture, design, validation, firmware, systems, and operations to ensure clarity, alignment, and predictable execution across the full product lifecycle.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;As the technical integrator for the product line, you will lead through influence and cross-functional authority, working on\u0026amp;nbsp;cutting-edge\u0026amp;nbsp;UALink, UCIe, and PCIe Gen6/Gen7 technologies that power the largest AI clusters in the world.\u0026amp;nbsp;You\u0026#39;ll\u0026amp;nbsp;be the central technical voice ensuring our switching products scale with Astera\u0026#39;s hyper-growth while delivering world-class silicon to\u0026amp;nbsp;customers\u0026amp;nbsp;enabling rack-scale AI and hyperscale data centers.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;Location - San Jose, CA OR Israel\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; 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data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Reduce ambiguity by translating product requirements into clear priorities, tradeoffs, and execution paths\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Own the Chip\u0026amp;nbsp;Tapeout\u0026amp;nbsp;and Chip signoff with full responsibility on Chip Quality.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Cross-Functional Technical Leadership\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; 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data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Partner with design verification teams to define coverage goals, regression strategies, and sign-off criteria\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Collaborate with DFT teams on test architecture, scan insertion, BIST, and manufacturing test strategies\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Work closely with physical design teams on timing closure, power optimization, and backend execution\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Process Excellence \u0026amp;amp; Organizational Development\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Establish and reinforce scalable processes, documentation, and handoffs that support company growth\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; 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data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Transform conflicts to foster a culture of ownership over ego, mentoring and elevating teams while strengthening technical judgment, accountability, and cross-functional collaboration\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Model steady, calm leadership, particularly in high-stakes or ambiguous situations\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Shape engineering culture and talent strategy to support Astera\u0026#39;s rapid growth trajectory\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Basic Qualifications\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, Computer Engineering, or related field\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;15+ years of experience across architecture, silicon design, validation, systems, or related domains\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Proven\u0026amp;nbsp;track record\u0026amp;nbsp;of developing large-scale chips (300mm²+) through successful\u0026amp;nbsp;tapeout\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Hands-on experience with 2.5D and 3D advanced packaging technologies and chiplet-based architectures\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Strong understanding of RTL design, design verification, DFT, and physical design flows\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience with high-speed serial interfaces such as PCIe, Ethernet, or switching architectures\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;7\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Demonstrated executive leadership of cross-functional technical programs with end-to-end product cycle ownership\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;8\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Strong communication\u0026amp;nbsp;and executive presence with the ability to influence at all levels of the organization\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Preferred Qualifications\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Master\u0026#39;s degree in Electrical Engineering or Computer Engineering\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience with\u0026amp;nbsp;UALink, UCIe, PCIe Gen5/Gen6/Gen7, or Ethernet switching architectures\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience with advanced process nodes (7nm, 5nm, or below)\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; 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data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Adaptability: Thrive in ambiguity and fast-changing environments\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; 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By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is seeking a Contract Recruiter to join our Talent Acquisition team in San Jose, California. As we continue to scale rapidly to meet the explosive demand for AI infrastructure connectivity solutions, this role will be instrumental in identifying and attracting top-tier talent across the organization.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;In this fast-paced, high-impact role, you will partner closely with hiring managers to understand their talent needs and execute full-cycle recruiting strategies. You\u0026#39;ll play a critical role in building the teams that are shaping the future of data center connectivity, working on requisitions spanning engineering, operations, and corporate functions. This is an exciting opportunity to join a hyper-growth company at the forefront of the AI revolution.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Full-Cycle Recruiting\u0026lt;/strong\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Manage end-to-end recruitment process from intake to offer acceptance across multiple requisitions\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Source, screen, and assess candidates using creative sourcing strategies and multiple channels\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deliver an exceptional candidate experience that reflects Astera Labs\u0026#39; culture and values\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Stakeholder Partnership\u0026lt;/strong\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Partner with hiring managers to understand role requirements, team dynamics, and hiring priorities\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Provide market insights, compensation benchmarking guidance, and talent landscape intelligence\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive weekly hiring syncs and maintain clear communication on pipeline progress\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Process \u0026amp;amp; Operations\u0026lt;/strong\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Maintain accurate and up-to-date candidate records in Greenhouse ATS\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ensure compliance with all hiring policies and procedures\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Contribute to process improvements and recruiting best practices\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor\u0026#39;s degree or equivalent experience\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;3+ years of full-cycle recruiting experience, preferably in the technology or semiconductor industry\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with applicant tracking systems (Greenhouse preferred)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong sourcing skills using LinkedIn Recruiter, Boolean search, and other channels\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent communication and interpersonal skills\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ability to manage multiple requisitions in a fast-paced environment\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience recruiting for engineering and technical roles in hardware, firmware, or semiconductor companies\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Background in high-growth startup or scale-up environments\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with AI infrastructure, data center, or connectivity technologies\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong organizational skills and attention to detail\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven ability to build relationships with hiring managers and candidates alike\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Salary range is $50 to $75/hour depending on experience, level, and business need.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4000202005,"name":"HR","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4703559005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4439515005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose (HQ)","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Quality Assurance","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4703559005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2620","title":" Data Analytics Engineer ","company_name":"Astera Labs","first_published":"2026-06-05T18:16:04-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Position Summary\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;We are seeking a Data Analytics Engineer with hands-on semiconductor test development experience to join our team. The ideal candidate will bridge the gap between test engineering, diagnostics, and data science, leveraging their semiconductor testing background to extract actionable insights from complex test data to optimize test processes, develop diagnostic tools/tests, and drive quality improvement initiatives.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Data Analytics \u0026amp;amp; Insights\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Analyze large-scale semiconductor test data from ATE (Automatic Test Equipment) systems\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop predictive models for yield prediction, failure analysis, and reducing quality excursions\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Create dashboards and visualization tools for quality monitoring\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Identify trends, patterns, and anomalies in production test data to improve product reliability\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Failure Investigation and Debug\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Analyze logs, test results, and system behavior to identify root cause or failure scope\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Reproduce issues in the lab environment and provide detailed debug information\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work with hardware, firmware, and ASIC teams to drive resolution\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Technical Development\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Create machine learning models for defect classification and outlier detection\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Automate reporting and data quality monitoring systems\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Use AI methodologies to enable advanced diagnostics of Astera silicon products\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop diagnostic tools and methods to enable faster root cause analysis and automation\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Customer Focus\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Provide customer support on device-related inquiries\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Generate reports relating to internal and external customer requests\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work with customer quality group to support internal and external customers\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Collaboration \u0026amp;amp; Communication\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Partner with test, product, and reliability engineering teams\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Present findings and recommendations to technical and non-technical stakeholders\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Document analytical methodologies and maintain code repositories\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Mentor junior team members on analytics best practices\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Education\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, Computer Engineering, Data Science, Statistics, or related field\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Master\u0026#39;s degree preferred\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;3-5 years of experience in semiconductor test engineering or test development\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;3+ years of hands-on data analytics experience\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of ATE platforms (Teradyne, Advantest, Credence, etc.)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with semiconductor manufacturing processes and test methodologies\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Technical Skills\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Programming:\u0026lt;/strong\u0026gt; Proficiency in Python, R, or similar languages for data analysis\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Data Tools:\u0026lt;/strong\u0026gt; SQL, pandas, numpy, scikit-learn\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Visualization:\u0026lt;/strong\u0026gt; Tableau, Power BI, matplotlib, plotly, or similar tools\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Test Systems:\u0026lt;/strong\u0026gt; Experience with test data formats (STDF), test executive software\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;The base salary range is $160,000 USD - $195,000 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4011733005,"name":"Quality","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4695156005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4435724005,"location":{"name":"Toronto, Ontario, Canada"},"metadata":[{"id":12122734005,"name":"Country","value":"Canada","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Toronto","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Digital Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4695156005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2547","title":"Director, Digital Compute \u0026 Power Optimization","company_name":"Astera Labs","first_published":"2026-05-29T20:47:32-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Job Description\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;We are looking for a hands-on Digital Design Engineering Manager to drive high-speed connectivity solutions. You will build and lead a team responsible for delivering the micro-architecture and implementation of front-end digital design, including RTL development, synthesis, IP integration, and block-level verification for high-performance ASICs.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335551550\u0026amp;quot;:1,\u0026amp;quot;335551620\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:0,\u0026amp;quot;335559737\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:160,\u0026amp;quot;335559740\u0026amp;quot;:278}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;The ideal candidate should have strong experience with low-power design techniques and a solid understanding of SerDes DSP design, including equalizer optimization for power and area efficiency.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335551550\u0026amp;quot;:1,\u0026amp;quot;335551620\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:0,\u0026amp;quot;335559737\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:160,\u0026amp;quot;335559740\u0026amp;quot;:278}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;The candidate must also have a good knowledge of communication and interface protocols such as CXL/PCIe (Gen 3 and above), Ethernet, or DDR.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335551550\u0026amp;quot;:1,\u0026amp;quot;335551620\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:0,\u0026amp;quot;335559737\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:160,\u0026amp;quot;335559740\u0026amp;quot;:278}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Basic qualifications:\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Strong academic and technical background in electrical engineering. A\u0026amp;nbsp;Bachelor’s\u0026amp;nbsp;degree in EE is\u0026amp;nbsp;required, and a\u0026amp;nbsp;Master’s\u0026amp;nbsp;degree is preferred.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;10+ years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;5+ years’ experience managing a team of RTL design engineers.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Entrepreneurial, open-mind\u0026amp;nbsp;behavior and can-do attitude. Think and act fast with the customer in mind!\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Authorized to work in Canada and start\u0026amp;nbsp;immediately.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Required experience:\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Hands-on, thorough knowledge of high-speed DPSs and SerDes\u0026amp;nbsp;equilizers.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Hands-on, thorough knowledge of high-speed protocols like CXL/PCIe, Ethernet, or DDR.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Proven front end design\u0026amp;nbsp;expertise\u0026amp;nbsp;– architecture, RTL, simulations, synthesis, timing closure, GLS, DFT etc.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience with Cadence and/or Synopsys digital design tools/flows\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience with scripting and automation, with a strong\u0026amp;nbsp;methodology\u0026amp;nbsp;background.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Good knowledge of design for test (DFT), stuck-at and transition scan test insertion\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Familiarity with UVM based design verification\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Silicon\u0026amp;nbsp;bring-up\u0026amp;nbsp;and\u0026amp;nbsp;debug\u0026amp;nbsp;expertise\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Small-geometry CMOS (≤28nm) design\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Preferred experience:\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Firmware development with C-language, scripting with Python or other equivalent programming languages.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Development/support for PCIe or Ethernet Switch products.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;The base salary range is CAD 200,000 – CAD 250,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.  \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000119005,"name":"Toronto","location":"Toronto, Canada","child_ids":[],"parent_id":4004709005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4702088005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4438853005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose (HQ)","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Engineering Operations","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4702088005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2609","title":"Director of Product Engineering","company_name":"Astera Labs","first_published":"2026-06-03T11:53:03-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is seeking a Director of Product Engineering to lead our product engineering organization in San Jose, CA. This is a critical leadership role responsible for driving next-generation high-speed, high-performance, and low-power semiconductor products from silicon bring-up through high-volume manufacturing in advanced process nodes.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As the AI infrastructure market accelerates at an unprecedented pace, Astera Labs needs a seasoned leader who can build and scale a world-class product engineering team while maintaining the technical depth to solve the hardest problems in high-speed connectivity. You will own the complete post-silicon product development lifecycle — from characterization and qualification through production ramp and sustaining — across our portfolio of purpose-built connectivity solutions enabling rack-scale AI.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This role demands a unique combination of hands-on technical expertise in high-speed signaling and ATE test fundamentals, coupled with the organizational leadership to build teams, establish best-known methods, and deliver products to production with uncompromising quality. You\u0026#39;ll partner closely with design, validation, operations, and customers to ensure Astera Labs\u0026#39; products set the industry standard for performance and reliability.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Team Leadership \u0026amp;amp; Organization Building\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Build, mentor, and lead a high-performing team of product engineers owning a diverse portfolio of connectivity products purpose-built for AI infrastructure\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Define team strategy, priorities, and execution roadmaps aligned with Astera Labs\u0026#39; aggressive product delivery timelines\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Establish scalable processes, best-known methods (BKMs), and operational excellence frameworks as the organization grows\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Make sound technical and organizational decisions in a fast-paced, dynamic environment with competing priorities\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;ATE Test Development \u0026amp;amp; Production Excellence\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Drive ATE test program development and optimization for wafer sort and final test solutions on the Advantest 93K platform\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Own device ATE test yields, test time reduction, and quality metrics with a detailed, data-driven mindset\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Establish consistent BKMs for rolling out new ATE test programs across product families\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Lead data analysis efforts using tools such as JMP or Spotfire to calculate limits, identify outliers, and drive continuous improvement\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Product Qualification \u0026amp;amp; Manufacturing\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Define and execute standards-based qualification programs at both product and package level\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Partner with OSATs to support high-volume manufacturing through the complete product lifecycle\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Ensure seamless production ramp and sustaining operations, delivering quality parts to Astera Labs\u0026#39; hyperscaler and enterprise customers\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Drive system-level debug involving test hardware, test programs, and DUT interactions across digital and analog domains\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional Technical Leadership\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Provide technical leadership in high-speed signaling including NRZ/PAM4 SerDes protocols (PCIe Gen 3+, Ethernet 25G+), and memory interfaces such as (LP)DDR5/4\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Partner with silicon design teams to feed back production learnings and drive DFT/DFM improvements\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Collaborate with silicon validation teams to ensure device performance meets production requirements\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Engage with customers and field teams on quality, reliability, and production-related technical matters\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering or Computer Engineering\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;8+ years of experience in post-silicon product development dealing with high-speed signals (product, test, or validation)\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;5+ years of managerial experience building and leading product engineering teams\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Hands-on experience with the Advantest 93K ATE platform including test program development for wafer sort and final test\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Strong technical foundation in high-speed SerDes protocols (PCIe, Ethernet, CXL) and/or memory interfaces (DDR5/LPDDR5)\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience defining and executing standards-based qualification at product and package level\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Demonstrated track record delivering semiconductor products to high-volume production with quality\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Strong data analysis skills and experience with statistical tools (JMP, Spotfire, or equivalent)\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Digital and analog circuit-level understanding for DUT characterization and debug\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Master\u0026#39;s degree in Electrical Engineering or Computer Engineering\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience working with silicon validation teams to correlate device performance with production requirements\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Firmware development experience in C/C++, scripting in Python, or equivalent programming skills\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience with advanced process nodes (5nm and below)\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Proven success partnering with OSATs in a fabless semiconductor operating model\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Prior experience in a high-growth company shipping products to hyperscaler customers\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;The salary range for this position is $187,200 to $260,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4612429005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4396467005,"location":{"name":"San Jose, CA"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Firmware Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4612429005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2039","title":"Director of System Validation Engineering","company_name":"Astera Labs","first_published":"2025-09-25T01:20:37-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;Astera Labs’ firmware and software are critical differentiators that have helped us win business across all CSPs and hyperscalers. We are seeking a \u0026lt;strong data-start=\u0026quot;898\u0026quot; data-end=\u0026quot;943\u0026quot;\u0026gt;Director of System Validation Engineering\u0026lt;/strong\u0026gt; to build and scale our system validation organization, ensuring our products meet the performance, reliability, and interoperability demands of next-generation AI and data center systems.\u0026lt;br\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Job Description\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Understand the performance and functionality requirements our ICs must deliver to enable customers developing Data Center systems using Astera Labs’ game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Own the development of a comprehensive validation plan and drive its execution. Devise test automation of ICs and board products in a data-centric manner, design experiments to root-cause unexpected behavior and report results and specification compliance.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Engage with key customers directly to understand their care-abouts and highlight the unique capabilities and performance of Astera Labs’ solutions.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong academic and technical background in electrical or computer engineering. At a minimum, a Bachelor’s is required, and a Master’s is preferred.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;≥12 years experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer/internal meetings in advance, and to work with minimal guidance and supervision.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Experience\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;≥3 Years experience leading a team in a “lead by example” manner—planning sprints, assigning tasks based on individuals’ strengths and career aspirations, providing constructive/encouraging feedback, maintaining a “dashboard” view of project status, chipping into shore up gaps in execution as needed.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;≥5 Years hands-on experience with Silicon/System bring-up, validation, and debug experience, including in customer systems.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Thorough knowledge of high-speed protocols like CXL, PCIe, NVMe, or Ethernet.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Good understanding of x86/ARM architecture, UEFI/Linux boot sequence.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;A strong background in developing bench automation techniques, especially using Python,\u0026amp;nbsp;with emphasis on\u0026amp;nbsp;execution efficiency, repeatability, data analysis and reporting.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with lab equipment including protocol analyzers, in-circuit debuggers, and CPU-based tool suites.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Experience\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Working knowledge of C or C++ for embedded FW and device drivers.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with PCIe compliance standards and the ability to follow and be involved in compliance and standard consortiums.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of simulation tools such as Keysight ADS, Mathworks QCD, etc. for IBIS-AMI analysis.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Working knowledge of SerDes architecture including Tx/Rx equalization, adaptation, clock recovery and SerDes link budgets.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with PAM4 SerDes is a huge bonus!\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025528005,"name":"Software Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4688393005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4432096005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Product Management","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4688393005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2483","title":"Director Product Marketing - Signal Connectivity Products","company_name":"Astera Labs","first_published":"2026-05-28T16:34:27-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is seeking a \u0026lt;strong\u0026gt;Director of Product Marketing to lead\u0026amp;nbsp;go-to-market strategy for our industry-leading connectivity solutions\u0026lt;/strong\u0026gt;. This is a high-impact leadership role at the intersection of technology and market strategy, where\u0026amp;nbsp;you\u0026#39;ll\u0026amp;nbsp;shape how the world\u0026#39;s largest\u0026amp;nbsp;hyperscalers\u0026amp;nbsp;and AI infrastructure builders understand and adopt our PCIe\u0026amp;nbsp;signal conditioning products.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As a senior leader on the product marketing team,\u0026amp;nbsp;you\u0026#39;ll\u0026amp;nbsp;drive positioning, messaging, and competitive strategy for products enabling the next generation of AI and cloud data centers.\u0026amp;nbsp;You\u0026#39;ll\u0026amp;nbsp;partner closely with engineering, sales, and executive leadership to translate deep technical capabilities into compelling value propositions that resonate with technical decision-makers. This role requires someone who can move fluidly between silicon-level technical discussions and strategic market conversations.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;With AI infrastructure demand accelerating and Astera Labs at the forefront of solving critical connectivity bottlenecks, this is an opportunity to shape the narrative for technologies like PCIe Gen 6/7 and\u0026amp;nbsp;UALink that are powering rack-scale AI systems worldwide.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Go-to-Market Strategy \u0026amp;amp; Execution\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Lead product positioning, messaging, and go-to-market strategy for PCIe signal conditioning product line\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Define and execute product launches that drive awareness, demand, and adoption with\u0026amp;nbsp;hyperscaler\u0026amp;nbsp;and enterprise customers\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop compelling content including presentations, white papers, datasheets, and technical collateral\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Revenue Impact\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Accountable for revenue delivery through new design wins, flawless execution of active programs, and driving long-term growth across strategic accounts\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive alignment between product positioning and business objectives, ensuring strategies translate into measurable revenue growth\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Market \u0026amp;amp; Competitive Intelligence\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Own competitive analysis and market intelligence for PCIe\u0026amp;nbsp;signal conditioning markets\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Identify\u0026amp;nbsp;market trends, customer needs, and emerging opportunities in AI infrastructure connectivity\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Translate market insights into actionable\u0026amp;nbsp;product\u0026amp;nbsp;and positioning recommendations\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional Leadership\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Partner with engineering to deeply understand product capabilities and roadmap\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Enable sales teams with training, tools, and competitive positioning to win strategic accounts\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with executive leadership to align product marketing initiatives with corporate strategy\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Team \u0026amp;amp; Stakeholder Management\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Build and mentor a high-performing product marketing team\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Serve as a technical spokesperson at industry events, customer meetings, and analyst briefings\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive alignment across marketing, product, and sales organizations\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s degree in electrical engineering, Computer Engineering, or related technical field\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;10+ years of experience in product marketing, product management, or technical marketing roles\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Demonstrated experience with PCIe technology or high-speed switching/interconnect products\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of semiconductor products and silicon development lifecycle\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Proven\u0026amp;nbsp;track record\u0026amp;nbsp;of leading successful product launches in the data center or infrastructure market\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience presenting to and influencing technical audiences including engineers and architects\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;MBA or\u0026amp;nbsp;master’s\u0026amp;nbsp;degree in\u0026amp;nbsp;a technical\u0026amp;nbsp;discipline\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience marketing to\u0026amp;nbsp;hyperscaler\u0026amp;nbsp;customers (AWS, Google, Microsoft, Meta, etc.)\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with emerging standards such as\u0026amp;nbsp;UALink, or PCIe Gen 6/7\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Background in AI/ML infrastructure or data center architecture\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience building and leading product marketing teams at high-growth technology companies\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong executive presence and public speaking skills for industry events and analyst engagements\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Salary range is $180,000 to $250,000 depending on experience, level, and business\u0026amp;nbsp;need. This role may be eligible for discretionary\u0026amp;nbsp;bonus,\u0026amp;nbsp;incentives\u0026amp;nbsp;and benefits.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4000198005,"name":"Product Management","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4692566005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4434109005,"location":{"name":"United States, Remote"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose (HQ)","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"CTO Organization","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4692566005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2507","title":"Distinguished Engineer – Server Firmware \u0026 System Architecture","company_name":"Astera Labs","first_published":"2026-05-19T19:37:41-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is at the epicenter of the AI infrastructure revolution, building the intelligent connectivity solutions that power the world\u0026#39;s most advanced data centers. As AI workloads scale to unprecedented levels, the demand for purpose-built, rack-scale platforms that seamlessly integrate high-speed connectivity, firmware intelligence, and composable architectures has never been greater — and neither has the opportunity to shape what comes next.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;The AI Platform Solutions Group is seeking a \u0026lt;strong\u0026gt;Distinguished Engineer\u0026lt;/strong\u0026gt; to serve as the technical visionary for next-generation AI infrastructure, spanning server firmware, high-speed connectivity, and rack-scale system design. In this role, you will define the end-to-end architecture for AI platforms that integrate cutting-edge technologies such as PCIe Gen5/6, composable rack architectures, and advanced interconnect solutions including Astera Labs\u0026#39; portfolio of retimers, switches, and fabric controllers.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This is a high-impact, high-visibility role where you will drive innovation across silicon integration, platform firmware, system performance, and rack-level orchestration — directly enabling hyperscale AI training and inference workloads. You will partner with silicon vendors, hyperscalers, OEMs, and ODMs while influencing industry standards and mentoring the next generation of platform architects. If you want to architect the future of AI infrastructure at a company that is defining the connectivity backbone of modern data centers, this is your role.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;AI Platform \u0026amp;amp; Rack-Scale Architecture\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Define the end-to-end architecture for AI platforms, from node-level design to rack-scale composable systems\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive adoption of PCIe-based fabrics for disaggregated compute, memory, and accelerator scalability\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Architect solutions for GPU/accelerator-dense systems optimized for AI training and inference workloads\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead integration of connectivity solutions — retimers, switches, and fabric controllers — aligned with Astera Labs\u0026#39; product ecosystem\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Firmware \u0026amp;amp; Platform Leadership\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Drive innovation in server BIOS/UEFI architecture, OpenBMC-based platform management, Redfish APIs for scalable infrastructure control, and lifecycle provisioning frameworks\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead system bring-up and ensure seamless firmware-hardware-software integration across complex AI platforms\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Define the technical vision and multi-year firmware roadmap for AI infrastructure platforms\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Performance \u0026amp;amp; Optimization\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Own end-to-end AI platform performance strategy including PCIe topology optimization, bandwidth scaling, latency reduction, and CPU performance tuning for AI orchestration workloads\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive memory performance optimization across DDR, NUMA, and emerging memory expansion technologies\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead performance tuning for multi-accelerator systems (GPU/ASIC/FPGA), high-throughput data pipelines, and distributed AI workloads\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Ecosystem \u0026amp;amp; Industry Leadership\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with silicon vendors (CPU, GPU, AI accelerators), connectivity ecosystem partners, OEMs, ODMs, and hyperscalers\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Influence industry standards across OpenBMC, Redfish, OCP, and related consortia\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Mentor senior engineers and grow deep technical bench strength across the organization\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Represent Astera Labs as a recognized thought leader in AI infrastructure and platform innovation\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor\u0026#39;s degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;15+ years of experience in system architecture, server firmware, or platform engineering\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep expertise in server BIOS/UEFI, OpenBMC and BMC firmware stacks, and Redfish or datacenter management frameworks\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong knowledge of PCIe architecture and performance optimization (Gen4/5/6)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with CPU, memory, and system-level performance tuning for high-performance computing or AI platforms\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong programming experience in C/C++ and low-level system software\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven track record of leading cross-functional, large-scale architecture initiatives\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Master\u0026#39;s degree or PhD in Computer Science, Electrical Engineering, or a related field\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with rack-scale composable infrastructure and disaggregated architectures\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Background in AI training clusters, accelerator-based systems, or hyperscale datacenter design\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Expertise in high-speed interconnect solutions such as retimers, switches, and fabric ICs\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with platform lifecycle management systems and fleet-level automation\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Contributions to industry standards bodies or open-source firmware ecosystems\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Demonstrated ability to define multi-year technical roadmaps and influence executive strategy\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4141010005,"name":"Platform Architecture","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4055745005,"name":"Remote - United States","location":"Remote-United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4692970005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4434305005,"location":{"name":"United States, Remote"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Remote","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"CTO Organization","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4692970005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2512","title":"Distinguished Engineer – System \u0026 Rack Hardware Architecture ","company_name":"Astera Labs","first_published":"2026-05-19T19:38:34-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is at the epicenter of the AI infrastructure revolution, building the intelligent connectivity solutions that power the world\u0026#39;s most advanced data centers. As AI workloads scale to unprecedented levels, the demand for purpose-built, rack-scale platforms that seamlessly integrate high-speed connectivity, firmware intelligence, and composable architectures has never been greater — and neither has the opportunity to shape what comes next.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;The AI Platform Solutions Group is seeking a \u0026lt;strong\u0026gt;Distinguished Engineer\u0026lt;/strong\u0026gt; to serve as the technical visionary for next-generation AI infrastructure, spanning server firmware, high-speed connectivity, and rack-scale system design. In this role, you will define the end-to-end architecture for AI platforms that integrate cutting-edge technologies such as PCIe Gen5/6, UAlink, CXL, composable rack architectures, and advanced interconnect solutions including Astera Labs\u0026#39; portfolio of retimers, switches, and fabric controllers.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This is a high-impact, high-visibility role where you will drive innovation across silicon integration, platform firmware, system performance, and rack-level orchestration — directly enabling hyperscale AI training and inference workloads. You will partner with silicon vendors, hyperscalers, OEMs, and ODMs while influencing industry standards and mentoring the next generation of platform architects. If you want to architect the future of AI infrastructure at a company that is defining the connectivity backbone of modern data centers, this is your role.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;AI Platform \u0026amp;amp; Rack-Scale Architecture\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Define the end-to-end architecture for AI platforms, from node-level design to rack-scale composable systems\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Drive adoption of PCIe/UAlink-based fabrics for disaggregated compute, memory, and accelerator scalability\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Architect solutions for GPU/accelerator-dense systems optimized for AI training and inference workloads\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Lead integration of connectivity solutions — retimers, switches, and fabric controllers — aligned with Astera Labs\u0026#39; product ecosystem\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;System Architecture \u0026amp;amp; Platform Leadership\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Lead system architecture and design for high-performance compute platforms optimized for AI and accelerator-driven workloads\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Design and integrate PCIe-based subsystems including GPU, accelerator, and high-speed I/O components leveraging PCIe Gen5/6 technologies\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Define and implement GPU-enabled server platforms for AI training, inference, and HPC workloads\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Architect and optimize high-speed Ethernet networking interfaces (25G/100G/400G+) within platform designs\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Define the technical vision and multi-year product roadmap for AI infrastructure platforms\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Platform Management \u0026amp;amp; Cross-Functional Leadership\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Define and implement platform management solutions including BMC integration, telemetry, health monitoring, and system-level diagnostics\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Collaborate with cross-functional teams spanning hardware, firmware, BIOS, and OS to ensure seamless platform integration\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Partner with silicon vendors, OEMs, and hyperscalers on custom platform development aligned with Astera Labs\u0026#39; connectivity ecosystem\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Drive performance optimization across PCIe topology, accelerator interconnects, and memory subsystems\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Own end-to-end AI platform performance strategy including PCIe topology optimization, bandwidth scaling, latency reduction, and CPU performance tuning for AI orchestration workloads\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Lead performance tuning for multi-accelerator systems (GPU/ASIC/FPGA), high-throughput data pipelines, and distributed AI workloads\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Ecosystem \u0026amp;amp; Industry Leadership\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Collaborate with silicon vendors (CPU, GPU, AI accelerators), connectivity ecosystem partners, OEMs, ODMs, and hyperscalers\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Influence industry standards across OpenBMC, Redfish, OCP, and related consortia\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Mentor senior engineers and grow deep technical bench strength across the organization\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Represent Astera Labs as a recognized thought leader in AI infrastructure and platform innovation\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;15+ years of experience in system architecture, server firmware, or platform engineering\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Deep expertise in server BIOS/UEFI, OpenBMC and BMC firmware stacks, and Redfish or datacenter management frameworks\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Strong knowledge of PCIe architecture and performance optimization (Gen4/5/6)\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience with CPU, memory, and system-level performance tuning for high-performance computing or AI platforms\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Strong programming experience in C/C++ and low-level system software\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Proven track record of leading cross-functional, large-scale architecture initiatives\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Master\u0026#39;s degree or PhD in Computer Science, Electrical Engineering, or a related field\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience with rack-scale composable infrastructure and disaggregated architectures\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Background in AI training clusters, accelerator-based systems, or hyperscale datacenter design\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Expertise in high-speed interconnect solutions such as retimers, switches, and fabric ICs\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience with platform lifecycle management systems and fleet-level automation\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Contributions to industry standards bodies or open-source firmware ecosystems\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Demonstrated ability to define multi-year technical roadmaps and influence executive strategy\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4141010005,"name":"Platform Architecture","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4055745005,"name":"Remote - United States","location":"Remote-United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4664853005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4420966005,"location":{"name":"San Jose, CA"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Design Verification","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4664853005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2309","title":"Distinguished Formal Verification","company_name":"Astera Labs","first_published":"2026-02-23T13:43:57-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;Astera Labs is seeking a \u0026lt;strong\u0026gt;Distinguished Engineer, Formal Verification\u0026lt;/strong\u0026gt; to join our world-class engineering team in San Jose, California. As a hyper-growth leader in AI infrastructure connectivity, we\u0026#39;re revolutionizing how data centers handle explosive AI workloads through cutting-edge PCIe Gen 6/7, CXL, Ethernet, UCIe, and UALink technologies. This is a rare opportunity to shape the formal verification strategy across our entire product portfolio while working on the most advanced connectivity solutions powering the AI revolution.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;In this highly strategic role, you\u0026#39;ll serve as Astera Labs\u0026#39; technical authority on formal verification, defining methodologies and best practices that ensure the highest quality standards across all our next-generation connectivity products. You\u0026#39;ll work at the intersection of innovation and reliability, leading efforts to catch critical corner-case bugs that traditional verification methods miss, while mentoring a global team of engineers and representing Astera Labs as a thought leader in the formal verification community. This position offers exceptional scope for impact—your work will directly enable the rack-scale AI infrastructure that\u0026#39;s transforming cloud computing and enterprise data centers worldwide.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Strategic Leadership \u0026amp;amp; Methodology Development\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Define and evolve formal verification strategy, methodologies, and best practices across all product lines for PCIe, CXL, Ethernet, UCIe, and UALink protocols\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Serve as technical authority on formal verification, providing expert guidance to engineering leadership on risk mitigation and design quality\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Represent Astera Labs in industry forums, standards bodies, and technical conferences as a thought leader in formal verification\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive cross-functional collaboration to influence technical direction across the organization\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Technical Execution \u0026amp;amp; Innovation\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Develop detailed formal verification test plans based on design specifications and collaborate with design teams to refine micro-architecture specifications\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Identify key logic components and critical micro-architectural properties essential for ensuring design correctness\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Implement formal verification models, abstractions, assertions, and utilize assertion-based model checking to detect corner-case bugs\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Apply complexity reduction techniques using industry-standard EDA tools to achieve proof convergence or sufficient depth\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop and maintain scripts to enhance FV productivity and streamline verification processes\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Team Development \u0026amp;amp; Cross-Functional Partnership\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Mentor Principal and Lead Engineers across global sites in advanced formal verification techniques\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Assist design teams with the implementation of assertions and formal verification testbenches for RTL at unit/block levels\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Participate in design reviews and collaborate with design teams to optimize design quality and performance, power, area (PPA) metrics based on formal analysis feedback\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Prepare and deliver customer meetings and executive presentations with minimal supervision\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;15+ years of experience in formal verification or 18+ years of experience in traditional design verification with significant formal verification specialization\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong proficiency in SystemVerilog/Verilog with deep understanding of hardware design verification\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Advanced scripting abilities with Python or Perl for automation and productivity enhancement\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven ability to manage and prioritize multiple high-impact tasks in a dynamic, fast-paced environment with minimal supervision\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong cross-functional collaboration skills with demonstrated ability to influence technical direction and drive consensus\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Entrepreneurial mindset with proactive, customer-focused attitude and ability to think and act quickly while maintaining high quality standards\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Master\u0026#39;s or PhD in Electrical Engineering, Computer Engineering, Computer Science, or Mathematics with focus on formal methods or verification\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience with formal verification tools such as Synopsys VCFormal and Cadence JasperGold\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with both bug hunting and static proof verification techniques\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with automating formal verification workflows within a CI/CD environment\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep knowledge of high-speed serial protocols: PCIe Gen 4/5/6/7, CXL, Ethernet (100G/400G/800G), UCIe, UALink\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Participation in industry standards bodies (PCI-SIG, CXL Consortium, IEEE, UCIe Consortium)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Patents or publications in formal verification or hardware verification methodologies\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Track record of recruiting, mentoring, and developing formal verification talent across distributed teams\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Salary range is $230,000 to $285,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4674947005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4425619005,"location":{"name":"Taipei, Taipei, Taiwan"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Sales","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4674947005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2388","title":"Executive Sales Representative","company_name":"Astera Labs","first_published":"2026-03-19T06:50:42-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;Regional Sales Executives will work closely with Field Sales Engineers (FAEs) and the sales management team to develop and execute an account strategy to effectively engage with leading cloud service providers on Astera Labs’ portfolio of connectivity products.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Develop a customer specific sales plan that identifies revenue generating opportunities and outlines steps to effectively develop relationships within key influencers in R\u0026amp;amp;D, Procurement, Executive level GM/CTO\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive sales efforts by teaming up with FAEs engaging with customers to provide roadmap updates, technology training, product sampling, technical support and gather customer forecasts\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Be a strong voice for your customers to communicate their product roadmap feedback, customer support issues and to drive a timely response from Astera Labs HQ\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Establish regular communication with your customer’s procurement, ODM ecosystem and other industry partners to be able to accurately forecast your region’s quarterly revenue and annual demand forecast\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s degree, preferred electrical/computer engineering and MBA.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;5+ years’ experience selling complex SoC/silicon products to Cloud Services Providers, Server or Network OEMs\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Demonstrated ability to prepare and execute customer account plans to win complex silicon design wins that contribute significant revenue growth\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Established relationships with some of our key target customers including Cloud Service Providers, Server, Storage \u0026amp;amp; Networking OEMs\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent communication and project management skills\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiar and at least 3+ years working experience with Taiwan Data Center ODMs like Quanta, Wistron, Wiwynn, Foxconn, and Inventec\u0026#39;s supply chain management\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Your base salary will be determined based on your experience and the pay of employees in similar positions\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4000197005,"name":"Sales","child_ids":[],"parent_id":null}],"offices":[{"id":4009035005,"name":"Taipei","location":"Taipei, Taiwan","child_ids":[],"parent_id":4002874005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4664075005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4420608005,"location":{"name":"Israel"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Physical Design/DFT","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4664075005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2305","title":"Expert IC Package Design Lead","company_name":"Astera Labs","first_published":"2026-02-22T03:09:38-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is establishing a strategic R\u0026amp;amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical \u0026#39;data bottlenecks\u0026#39; enabling the future of AI at scale. As we expand our presence in Israel, we\u0026#39;re seeking a visionary \u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Expert IC Package Design Lead\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;strong\u0026gt;\u0026amp;nbsp;\u0026lt;/strong\u0026gt;to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, leading the physical implementation strategy for chips that power the world\u0026#39;s largest AI clusters.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;As an \u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Expert IC Package Design Lead\u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;, you will be a core technical contributor in the development of advanced IC packaging solutions for high-performance connectivity silicon.\u0026amp;nbsp;\u0026lt;br\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;You will own package flow, architecture, design, and qualification from concept through production, working closely with silicon, signal integrity, power integrity, mechanical, manufacturing, and external OSAT partners.\u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;You will be responsible for defining package technologies that meet aggressive electrical, thermal, mechanical, and cost targets, enabling Astera Labs’ products to operate reliably in the world’s most demanding AI and cloud environments.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:160}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Own end-to-end IC package design, from early architecture and feasibility through detailed design, qualification, and high-volume manufacturing\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:160}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Define package architecture and technology selection (organic substrates, advanced laminate, interposers, multi-die/chiplet packaging, CoWoS - 2.5D/3D integration)\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:160}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Lead signal integrity (SI), power integrity (PI), and thermal considerations at the package level for high-speed, high-power devices\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:160}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Drive package layout, substrate routing, bump/ball maps, stack-ups, materials selection, and mechanical constraints\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:160}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Collaborate closely with silicon design, SerDes, system, SI/PI, and reliability teams to optimize overall product performance\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:160}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Interface with OSATs, substrate vendors, and manufacturing partners to ensure design-for-manufacturability (DFM), yield, and cost targets\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:160}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Lead package-related risk assessment, failure analysis, and corrective actions during bring-up and production ramp\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:160}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Support NPI, qualification, and product sustainment activities, including vendor audits and technical reviews\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:160}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;10+ years of hands-on IC BIG package design experience\u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt; for high-performance semiconductor products, with full ownership from concept through tape-out\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:160}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Expert proficiency in IC package design tools\u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt; (Cadence APD / SiP or equivalent) and experience designing complex packages (BGA, FCBGA, FCCSP)\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:160}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Strong package architecture \u0026amp;amp; integration expertise\u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;, including stack-ups, ball/bump maps, constraints, SMT integration, and package BOM ownership\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:160}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Deep understanding of signal, power, and thermal integrity\u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt; at the package level, with ability to drive design tradeoffs based on analysis\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:160}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Proven manufacturing and release experience\u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;, including DRC/LVS/DFM, OSAT engagement, and delivering production-ready package designs\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:160}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Experience with AI, networking, PCIe, CXL, or other high-speed data center interfaces\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:160}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Familiarity with package reliability standards and qualification (JEDEC, IPC, thermal cycling, HTOL, etc.)\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:160}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Experience supporting chiplet-based architectures and heterogeneous integration\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:160}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Prior technical leadership or package ownership on high-volume products\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:160}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4008937005,"name":"Israel","location":"Israel","child_ids":[4061058005,4052111005,4056876005],"parent_id":null}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4670627005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_optional","internal_job_id":4423565005,"location":{"name":"Taipei, Taiwan"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Field Applications Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Internship","value_type":"single_select"}],"id":4670627005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2347","title":"Field Application Engineering Intern","company_name":"Astera Labs","first_published":"2026-03-06T17:26:23-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;div\u0026gt;Astera Labs is seeking highly motivated Interns to join\u0026amp;nbsp;\u0026lt;strong\u0026gt;Field Application Engineering team\u0026lt;/strong\u0026gt; in their Taipei, Taiwan.\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;As an FAE, you will work to establish the team as trusted technical advisors to the world’s leading cloud service providers, server and network OEMs by working with them to design solutions that use Astera Labs’ portfolio of connectivity products. In this role, you will need to identify and understand customer requirements, propose Astera Labs solutions that provide clear value to the customer and provide hands-on design-in support. You will drive innovation by listening to the customer requirements, working with our engineering teams to implement into the product roadmap and delivering the results back to the customer.\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;strong\u0026gt;If you are:\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;A Junior going into Senior year or Senior graduating by the end of this year\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Have strong in academics and technical background in Electrical Engineering\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Someone with professional attitude, ability to prioritize a dynamic list of multiple tasks and work with minimal guidance and supervision\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong in analytical skills, self-motivated and a challenge taker\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Authorized to work in Taiwan and start immediately\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;strong\u0026gt;What we are looking for:\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;In AI infrastructure, high‑speed interfaces like PCIe, Ethernet, DDR, and NVMe are essential—interest in learning these is a strong plus.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Willingness to work with lab tools such as protocol analyzers and logic analyzers.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Basic understanding of schematics or PCB layout tools (Cadence, Altium, etc.).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Basic understanding of using an oscilloscope.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Some experience with C or Python, or curiosity about firmware and AI‑assisted development.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ability to use PowerPoint, Excel, and support simple project coordination.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;If the above position excites you? We would love to hear from you.\u0026lt;/div\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4134751005,"name":"Field Applications","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4009035005,"name":"Taipei","location":"Taipei, Taiwan","child_ids":[],"parent_id":4002874005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4674945005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_optional","internal_job_id":4425617005,"location":{"name":"Taipei, Taiwan"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Field Applications Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4674945005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2387","title":"Field Applications Engineer","company_name":"Astera Labs","first_published":"2026-03-19T06:51:00-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;As an Astera Labs Principal Field Applications Engineer, you will support the world’s leading cloud service providers, server and network OEMs by working with them to design solutions that use Astera Labs’ portfolio of connectivity products. In this role, you will need to identify and understand customer requirements, propose Astera Labs solutions that provide clear value to the customer and provide hands-on design-in support. You will drive innovation by listening to the customer requirements, working with our engineering teams to implement into the product roadmap and delivering the results back to the customer.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026amp;nbsp;Basic qualifications:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;BS in electrical engineering. Master’s degree in engineering is preferred.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Minimum of 8 years’ experience working with Cloud service providers and server OEM customers to design in complex SoC/silicon products for Server, Storage, and/or Networking applications.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Customer-oriented, Goal-driven, Self-motivated, be able to work independently and be able to travel frequently to customer sites\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Fluent in Mandarin and English\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Entrepreneurial, open-mind behavior and can-do attitude. Think and act with the customer in mind!\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required experience:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Hands-on, thorough knowledge of high-speed protocols like PCIe \u0026amp;amp; Ethernet\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Silicon/System bring-up and debug experience in customer systems.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with lab equipment including protocol analyzers and oscilloscopes.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;A strong background in high-speed board design techniques, and understanding of Data Center systems like Servers, JBOGs/JBODs, Networking switches/routers etc.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Intermediate level of proficiency in Python for automating system validation and link optimization.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Able to step through embedded firmware at the SerDes (SoC) or MCU level for debugging.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Firsthand experience with lab equipment including traffic generators, analyzers, and high-speed oscilloscopes.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Business travel to Asia and the North America region may be required as needed.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred experience:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong working knowledge of a high speed interface at a physical layer level, associated standards, and debug. Most recent experience with 12G NRZ signaling at a minimum, some experience with 25G NRZ/56G PAM4 preferred.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Development, support, and experience with PCIe ICs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience in embedded SW debug or development with firmware, drivers, and BIOS using PCIe technology.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4134751005,"name":"Field Applications","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4009035005,"name":"Taipei","location":"Taipei, Taiwan","child_ids":[],"parent_id":4002874005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4670943005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_optional","internal_job_id":4423704005,"location":{"name":"Taipei, Taiwan"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Quality Assurance","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Internship","value_type":"single_select"}],"id":4670943005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2349","title":"Field Quality Engineer Intern","company_name":"Astera Labs","first_published":"2026-03-09T22:26:07-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Job Summary\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;We are seeking a student intern to drive product quality improvements across both Astera Lab’s semiconductor and board-level products. In this role, the candidate will perform failure analysis for customer returns. The candidate will also compile 8D reports to communicate the analysis findings to the customers.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Key Responsibilities\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Perform system-level test for the customer returns on a bench in the lab.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Review ATE test log files.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Work with third-party labs to perform electrical FA (EFA) for more in-depth analysis.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Log analysis results to the portal system daily.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Work with internal teams and suppliers to drive product quality improvements.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Write up analysis reports to provide updates to the customers. Participate in the meetings with customers to present the technical findings.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Bring up and validate new test equipment in the lab. Update the lab inventory list.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Perform additional tasks assigned by the Director of Field Quality Engineering.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Education \u0026amp;amp; Experience\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Final year students from Bachelor’s degree are welcome to apply.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Students from Master’s degree are preferred.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Technical Skills\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Good knowledge of IC fabrication, packaging, board assembly (SMT), and test processes\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Strong communication skills in English and Mandarin.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Working Conditions:\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· May require occasional travel to customer sites within Taiwan.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Must be flexible to work on-site and available during business hours for at least 3 days per week.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4011733005,"name":"Quality","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4009035005,"name":"Taipei","location":"Taipei, Taiwan","child_ids":[],"parent_id":4002874005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4675837005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4426043005,"location":{"name":"Aachen, North Rhine-Westphalia, Germany"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Administration","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Internship","value_type":"single_select"}],"id":4675837005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2395","title":"Finance and Administration Intern (Part-Time, Germany 2026)","company_name":"Astera Labs","first_published":"2026-06-05T13:06:21-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;strong data-olk-copy-source=\u0026quot;MessageBody\u0026quot;\u0026gt;Support the finance team across accounting, procurement, financial planning, and process improvement in an international environment.\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Process invoices, create POs, and support vendor onboarding\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support OPEX planning and analyze production cost structures\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Contribute to financial analysis and planning activities\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Assist ERP migration and improve processes\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support automation initiatives (e.g., Power Automate, AI tools)\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;strong\u0026gt;Your Profile\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Student in Finance, Accounting, Business, or similar\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong analytical skills and attention to detail\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Structured, reliable, and proactive way of working\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Quick learner with ability to work independently\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Good Excel skills; ERP/automation tools are a plus\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;div\u0026gt;Fluent in English and German\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4130015005,"name":"Admin","child_ids":[],"parent_id":null}],"offices":[{"id":4056756005,"name":"Aachen","location":"Aachen, Germany","child_ids":[],"parent_id":4056755005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4608186005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4394409005,"location":{"name":"San Jose"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Firmware Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4608186005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"1986","title":"Firmware Engineering Director/ Manager","company_name":"Astera Labs","first_published":"2025-10-22T19:57:57-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Job Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As a \u0026lt;strong\u0026gt;Firmware Engineering Director/ Manager\u0026lt;/strong\u0026gt;, you will lead and scale firmware development efforts for Astera Labs’ SoC and systems products used in data-center and AI infrastructure. You will be responsible for technical direction, people leadership, and execution across core firmware, bare-metal software, and device driver development.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Firmware is a first-class differentiator at Astera Labs. In this role, you will build, mentor, and guide high-performing firmware teams while partnering closely with hardware, silicon architecture, validation, product, and customers to ensure successful delivery of complex firmware programs.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This role supports two leadership levels:\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Firmware Engineering Manager\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Firmware Engineering Director\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Own the firmware execution strategy across one or more SoC or systems programs, ensuring alignment with product and silicon roadmaps.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead and manage firmware teams responsible for bare-metal firmware, RTOS-based firmware, and device drivers.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Provide technical oversight and architectural guidance without being the primary implementer.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Partner closely with hardware architecture, RTL design, validation, and systems teams to define HW/SW interfaces, development milestones, and integration plans.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive SoC bring-up readiness, firmware validation strategy, and risk mitigation across pre-silicon and post-silicon phases.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Establish development processes, coding standards, and quality metrics to ensure predictable and scalable execution.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support customer engagements as needed, including escalation handling, technical reviews, and roadmap alignment.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Communicate status, risks, and tradeoffs clearly to executive leadership and cross-functional stakeholders.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026amp;nbsp;Director scope: own multi-team delivery, long-term roadmap planning, hiring strategy, and cross-org alignment across multiple product lines.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Firmware Domains Under Management\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Teams under this role may span one or more of the following areas:\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;PCIe Firmware: \u0026lt;/strong\u0026gt;PCIe switch and controller firmware (Gen3+), including link training, enumeration, error handling, and performance optimization.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Ethernet Firmware: \u0026lt;/strong\u0026gt;Embedded firmware for high-speed Ethernet systems (100G–400G+), including PHY/MAC interaction and link bring-up.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;UCIe / Chiplet Firmware: \u0026lt;/strong\u0026gt;Firmware for chiplet-based SoC architectures, including die-to-die interconnect initialization and advanced packaging enablement.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;10+ years of experience developing or supporting firmware for SoC, silicon, or systems products in compute, networking, or storage domains.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;5+ years of experience in a people-management role, leading firmware or low-level software teams.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of bare-metal firmware, RTOS environments, and firmware development lifecycles.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience managing teams working on complex SoCs and high-speed interfaces such as PCIe, Ethernet, DDR, NVMe, or similar.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven ability to lead execution across ambiguous, fast-moving environments with multiple stakeholders.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong communication skills, executive presence, and customer-facing professionalism.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Authorization to work in the U.S.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Prior experience managing firmware teams delivering PCIe or Ethernet switch products.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with UCIe, chiplet architectures, or advanced packaging ecosystems.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Track record of scaling teams through hiring, onboarding, and mentorship.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience working with or supporting customers during bring-up, deployment, or escalations.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Participation in industry ecosystems such as OCP or OpenBMC.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Director level: experience owning multi-program delivery, long-term technical roadmaps, and cross-functional organizational planning.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;This position can be hired as a\u0026amp;nbsp;\u0026lt;strong\u0026gt;Senior Manager Level or Director Level\u0026lt;/strong\u0026gt;.\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;The base salary range is $230,000 USD – $265,000 USD. Your base salary will be determined based on location, experience, and employees\u0026#39; pay in similar positions.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025528005,"name":"Software Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4695019005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4435647005,"location":{"name":"Bengaluru, Karnataka, India"},"metadata":[{"id":12122734005,"name":"Country","value":"India","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Bengaluru","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Firmware Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4695019005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2540","title":"Firmware QA Manager","company_name":"Astera Labs","first_published":"2026-05-26T03:42:34-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Title\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;: \u0026lt;strong\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Lead Firmware QA Engineer\u0026lt;/span\u0026gt;, A\u0026lt;/strong\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;stera Labs, Bengaluru, India.\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;br\u0026gt;\u0026amp;nbsp;\u0026lt;br\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Astera Labs Inc., a leader in purpose-built connectivity solutions for data-centric systems, is seeking\u0026lt;strong\u0026gt; Software QA Manager\u0026lt;/strong\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt; for their Bengaluru (India) Design Center. Partnering with leading processor and GPU vendors, cloud service providers, world-class manufacturing companies, Astera Labs is helping data-centric system designers remove performance bottlenecks in compute-intensive workloads such as Artificial Intelligence and Machine Learning.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134245417\u0026amp;quot;:false}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;:\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s degree in electrical engineering (EE) or Computer Science is required; a master’s or PhD in EE is preferred with minimum 15 years of experience.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Experience\u0026lt;/strong\u0026gt;:\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experienced and detail oriented PCIe switch test engineer with solid understanding of PCIe protocol.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Estimate work, identify dependencies and develop schedules.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Responsible for designing and executing functional, performance, interoperability and stress tests.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work closely with\u0026amp;nbsp; Silicon team, architecture team, FW development team to understand the design and develop test strategies.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Responsible for manual and automation testing.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong knowledge of scripting ( Python ) is must.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Responsible for automation development and manual testing.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Perform Signal integrity and protocol level validation.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Closely work with development teams to triage and debug issues.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of collecting PCIe trace using PCIe analyzer and analyzing the trace to triage issues.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience in PRBS testing, loopback and margining tests.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Good understanding of OOB testing and Protocols like MCTP, I2C, SPDM etc.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience is PCIe compliance testing is a plus.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Regularly working with Hyperscale\u0026#39;s and Tier 1 OEMs to communicate plans and status, address escalations, deliver on SLAs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge in validation of NIC controllers and storage controllers is preferred.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Requirements management and traceability through software development phases.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Mentoring and coaching team members to help them excel in their jobs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Power user of Git, Jira and Confluence.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025528005,"name":"Software Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4049113005,"name":"Bengaluru","location":"Bengaluru, India","child_ids":[],"parent_id":4052109005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4691421005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4433380005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose (HQ)","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Finance \u0026 Accounting","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4691421005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2498","title":"FP\u0026A Business Unit Controller","company_name":"Astera Labs","first_published":"2026-04-30T17:09:25-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As a \u0026lt;strong\u0026gt;FP\u0026amp;amp;A Business Unit Controller\u0026lt;/strong\u0026gt; you will be primarily responsible for managing the business partnering relationships for the R\u0026amp;amp;D business units including their annual budgets and quarterly forecast updates and actual performance. The ideal candidate has a strong understanding of financial processes and complex transaction flows with a desire to grow and contribute in a high-growth, fast-paced environment. This role must communicate and organize tasks well to be effective.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Primary Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Establish strong partnership with leadership to help business owners manage their business effectively\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead all forecasting and analysis activities for the business owners including: annual plan, quarterly forecast updates and strategic planning\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop, analyze, and interpret financial data to evaluate operating results against budget and profitability metrics\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Provide analytical insights, assess risks, and guide senior leadership in strategic decision-making\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with Corporate Finance on various projects as needed\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Provide business analysis and support where needed\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;8+ years experience in FP\u0026amp;amp;A and business partnering, preferably in semiconductor or other manufacturing\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent financial modeling and business partnering skills\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong analytical and problem solving skills\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Great organization and communication skills, able to work effectively with the business to meet deadlines\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with basic GAAP concepts (revenue recognition, accruals, capitalization vs expense)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Advanced Excel skills\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiar with Oracle planning tools\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of financial transaction flows and financial reporting\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong feeling of ownership over business processes and desire to improve and make them more efficient\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s degree in Finance or related field\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Salary range is $150,000 to $200,000 depending on experience, level, and business need. This role is eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4000199005,"name":"Finance","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4664494005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4420781005,"location":{"name":"San Jose, CA"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Hardware Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4664494005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2307","title":"Hardware Diagnostics Senior Engineer","company_name":"Astera Labs","first_published":"2026-02-23T19:42:23-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;As a\u0026amp;nbsp;\u0026lt;strong\u0026gt;Senior Software Diagnostics Engineer \u0026lt;/strong\u0026gt;on\u0026amp;nbsp;the Astera Labs Hardware Engineering team you will be responsible for building diagnostics and manufacturing software to allow design, test, and manufacture of cutting-edge high-speed datacenter products.\u0026amp;nbsp; You will be working on a project from conception to the final production stage at contract manufacturer.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;The role requires a strong and broad software background and a good understanding of hardware design and manufacturing practices.\u0026amp;nbsp; At the same time, we welcome candidates with deep experience in smaller areas and desire to learn.\u0026amp;nbsp; Depending on your experience, you may be focusing on design/validation or automation/manufacturing.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities: \u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Design, implement \u0026amp;amp; test production-grade diagnostics for high-speed digital boards and ASICS to help with hardware validation.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Design, implement \u0026amp;amp; test manufacturing tests to validate mass production of digital boards used in data center networking product\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Bring-up newly manufactured boards and port the first level of software.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Isolate and perform root-cause analysis of reported failures\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support new platform software and hardware features\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Coordinate with the hardware engineering team on bring-up schedules and feature delivery\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Participate proactively in design discussions, design review and project management\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelors in Computer Science/Computer Engineering or equivalent experience.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of modern software development\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency in Python, C or similar\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ability to work cross-functionally in a fast-paced, highly technical environment.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;2+ years of Experience in subset of diagnostics, hardware bring-up, test or manufacturing automation\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong debugging skills across hardware, firmware, and system layers\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Experience/Nice to Have\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience working with datacenter-level complex electronic equipment bring-up/diagnostic/manufacturing\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ability to read schematic/layout\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;System debug experience\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Embedded programming and good knowledge of OS internals (Linux/Unix)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Has knowledge of common interconnecting buses and interfaces such as PCIe, I2C, XAUI, 10G Ethernet drivers, FPGA, Switch chips, SSL offload, TCAM programming.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with DDR5\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;The base salary range is $120,000 - $195,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025526005,"name":"Hardware Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4702155005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4438890005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose (HQ)","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Hardware Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4702155005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2614","title":"Hardware Engineering Operations / Manufacturing, AVP","company_name":"Astera Labs","first_published":"2026-06-04T13:43:23-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;h1 data-local-id=\u0026quot;46934cd55fd6\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;heading\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot; data-pm-slice=\u0026quot;1 3 []\u0026quot;\u0026gt;AVP of Hardware Engineering Operations/Manufacturing\u0026lt;/h1\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;ee96d9e48d5a\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;d9b709a38d57\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Astera Labs is scaling rapidly as the connectivity backbone of rack-scale AI infrastructure, and our hardware manufacturing footprint is scaling with it. Smart Cable Modules (SCM), Active Electrical Cables (AEC), evaluation boards, AI Chassis-class systems, and ODM-built products are central to how we deliver purpose-built connectivity at hyperscale. We\u0026#39;re hiring an AVP of Hardware Engineering Operations/Manufacturing to bring focused, senior leadership to this growing function.\u0026lt;/p\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;fa000c7cc455\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;This is a wide-ranging role spanning the full breadth of Astera Labs\u0026#39; hardware portfolio — from Smart Cable Modules to rack-scale chassis-based products. You\u0026#39;ll own manufacturing strategy and execution across SCM, AEC, evaluation boards (SVB/EVB), AI Chassis-class systems, and ODM-built products such as switch trays and CEM cards. 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data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;cd826728d242\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Partner with Hardware Engineering, Product, Supply Chain, and Quality leaders, and represent hardware operations in executive reviews\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;5b016da6-6793-4a7d-95b9-6c55b2c370ab\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;f2214f95dad4\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;New Product Introduction (NPI) \u0026amp;amp; Advanced Manufacturing\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;605330a0-d9f7-4504-8007-76d037eb91fe\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;667b8e11-9aca-40b2-b7f5-d01f84d7b2c2\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;c0d383ac9065\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Drive Design for Manufacturability (DFM) reviews on early product designs to validate completeness and manufacturability before release to the floor\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;9cc32427-d074-4ade-8312-60f730b5bf7b\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;84e4f525f380\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Lead production scaling — estimating costs, production times, and staffing requirements for new designs\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;665cf7f9-bc2c-46c9-b938-841065d72be4\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;f2f79a2aeaa3\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Prepare and maintain technical documentation for new manufacturing processes and engineering procedures\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;d3e9d0ed-da5c-48f5-ac7a-34b0d5bc636e\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;d418b0343b2a\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Process \u0026amp;amp; Sustaining Engineering\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;8226bcd9-426a-4b14-86a1-a0d081cbf5e0\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;707d1a7d-fd1c-4192-80f8-f5a621edb5cc\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;c2c8503eab20\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Design factory layouts and analyze workflows to achieve maximum production efficiency\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;aaa5d98f-d918-4162-a1f7-8b1e8eaebc8e\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;9380862416fa\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Troubleshoot operational bottlenecks and investigate material use variances directly on the assembly line\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;d25fd50d-398d-49b5-9c35-87366fd5cde1\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;70e7a3c56aad\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Conduct ongoing time and cost analyses to identify waste reduction and lean manufacturing improvements\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;d0f5afc8-dcd8-4fbe-a276-f9afe0b7421f\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;b148e36513bc\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Test Engineering\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;32a22bad-018d-467d-bb7f-fb5d397f013e\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;b25c65e9-b8b6-453d-b300-b27fb5a61480\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;2c24f1ea0e69\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Architect test parameters for finished products to validate they meet exact process requirements\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;411f0492-618d-4bcc-9d00-af8ec6cf97b2\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;bc5dc8eb07e2\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Coordinate the design, procurement, build, and debug of automated test equipment\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;86dbcb98-5877-4ee4-aa23-3d3ca0a8f617\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;71811e583443\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Test products to identify anomalies and ensure compliance with functional and safety standards\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;d254e8aa-d050-4e58-b52e-7f7aaf00dfef\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;e27f7cb4e58e\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Product Engineering (Manufacturing Focus)\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;32f9badf-dc35-4e16-94ff-1f6be68d5a03\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;ef115ee8-4f5a-46e4-8d4e-39ec3ec22d33\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;33e6700c60b7\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Lead failure analysis using statistical methods and recommend changes in designs, tolerances, or processing methods\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;4e924934-eb2b-4303-bdc3-da4ad083e579\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;e478b92a534c\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Apply root-cause fixes to prevent reoccurrence of product problems involving existing designs or materials\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;32b3bf01-ead0-42d3-ab53-fe8b23381c21\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;1898c3dc71f7\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Monitor and analyze operational data to evaluate product performance and drive technical design changes that improve yield\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;6a117cfc-8e0d-45a0-942f-d3bd0b7f0739\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;701e0406b36f\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Tooling \u0026amp;amp; Automation\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;f93adef8-4204-4d07-b0ec-20184eee7bed\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;01d0e6f6-a96c-4abe-a823-2d73fa89d870\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;6b58e6afadac\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Assess, select, and schedule installation of manufacturing machinery and industrial processing systems\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;fe7efc32-8151-4cbc-b906-bf05b1cd0735\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;666954d94f12\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Design and implement custom jigs, fixtures, and manufacturing aids for daily assembly\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;7e414841-5706-4262-ae9e-5a7abf63a677\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;aad4a0d88591\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Apply automation techniques and robotics programming to improve workflow and reduce manual labor\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;040298488a60\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;4085a2cf-45fc-48e8-9a13-b9e60e5227a1\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;ee9c10b4-c015-4d1f-938e-a176bed539b7\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;531d18a96685\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering or related technical discipline\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;621de5dc-3cec-4835-b8d6-7b53e29d4bea\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;3a0221cf3d71\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;15+ years of hardware manufacturing experience, with significant time leading cable assembly, PCBA, board, module, or system/chassis manufacturing\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;8ff8bc75-8229-40f4-96a8-95aecb9a59a7\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;c96478e676c4\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Proven track record managing contract manufacturers in Asia, including site ramps and multi-site operations\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;c2ed6d2a-40d3-413c-90e1-c6b54d30a7a8\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;0fe5f6f28046\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Deep expertise in NPI, DFM, mass production ramp, yield/test, and quality systems for high-volume hardware products\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;715867aa-c8cf-4c21-a696-954212dec5c0\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;970d83f1baaa\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Hands-on experience across process/sustaining engineering, test engineering, and tooling/automation\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;1a1c17c3-fbe8-4da6-96ee-6961e2183d2c\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;621dc9dce9b8\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Experience leading and scaling hardware operations organizations through hyper-growth\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;09102c1d-3700-4495-a559-174420a5c033\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;bfb981d48f97\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Willingness and ability to travel internationally to CM and ODM sites on a regular cadence\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;b0d52c8ca755\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;strong data-prosemirror-content-type=\u0026quot;mark\u0026quot; data-prosemirror-mark-name=\u0026quot;strong\u0026quot;\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-local-id=\u0026quot;02bd72ef-e799-4987-9d1e-b720b33e4e0b\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;bulletList\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;417a4318-742c-4f40-9322-caf387dfe094\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;416b05d59a5d\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Master\u0026#39;s degree in Electrical Engineering or related field\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;ff607dc7-20ff-46f4-b8f5-4387c250f7e1\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;ffd50728032f\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Direct experience with Active Electrical Cables (AEC), optical transceivers, Smart Cable Modules, or high-speed cable/connector assemblies\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;923ede5c-5945-44ce-83b6-473f5907a74b\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;ea8bc7972070\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Experience manufacturing rack-scale or chassis-class systems for hyperscale or AI infrastructure\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;318228d1-44b2-4b41-b866-8a078eaa107f\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;0c35b636e3db\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Experience with ODM engagement models for system-level products (switch trays, CEM cards, or similar)\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li data-local-id=\u0026quot;0f6b13dd-445b-49e0-a3c2-1ed24ac8db32\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;listItem\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;\n\u0026lt;p data-local-id=\u0026quot;b1b2b2300a99\u0026quot; data-prosemirror-content-type=\u0026quot;node\u0026quot; data-prosemirror-node-name=\u0026quot;paragraph\u0026quot; data-prosemirror-node-block=\u0026quot;true\u0026quot;\u0026gt;Chinese language proficiency (Mandarin) for direct CM partnership in China\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025526005,"name":"Hardware Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4674439005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4425378005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Hardware Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4674439005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2373","title":"Hardware Lab Engineer","company_name":"Astera Labs","first_published":"2026-04-02T13:46:45-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;u\u0026gt;Overview\u0026lt;/u\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs Inc. is seeking an experienced and self-driven \u0026lt;strong\u0026gt;Hardware Lab Engineer\u0026lt;/strong\u0026gt; to join our dynamic team in developing world class connectivity products for AI infrastructure.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;u\u0026gt;Job Description\u0026lt;/u\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This role will work closely with firmware, system validation, quality, and product engineers to support silicon bring-up, characterization, and debug activities through hands-on lab execution. The ideal candidate will have a deep understanding of circuits, hands-on experience with PCBAs and silicon test environments, and the ability to work on complex, open-ended tasks with minimal oversight.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;u\u0026gt;Key Responsibilities\u0026lt;/u\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Setup and maintain test environments for silicon validation and characterization. Configure and update hardware, software, firmware, and applications. Replicate BKCs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Conduct hands-on testing of silicon devices including PCIe Gen5/6/7, CXL, Ethernet, and other high-speed interfaces\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Install and configure servers, including FW, BIOS, OS, and network\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;RMA intake/triage: inspection, electrical verification, screening (including CSAM inspection), and prioritization\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Manage logistics and communications with external labs\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Organize, track, and distribute lab equipment, hardware, and peripherals\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ad hoc PCBA rework and soldering of fine-pitch SMD components\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop, document, and maintain lab procedures\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;u\u0026gt;Required Qualifications\u0026lt;/u\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, Computer Engineering, or related field\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;5-12+ years of hands-on experience in lab environments supporting silicon validation or hardware development\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency with high-speed test equipment (oscilloscopes, protocol analyzers, BERTs, multimeters)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with high-speed interface testing (PCIe, CXL, DDR, Ethernet, or SerDes)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong programming skills in Python for test automation\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with Linux operating systems and command-line tools\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Demonstrated experience coordinating with third-party testing laboratories and managing logistics, including sample shipping, chain of custody, and scheduling\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong organizational skills for managing multiple RMA cases simultaneously and prioritizing based on severity/impact\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;u\u0026gt;Preferred Qualifications\u0026lt;/u\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience with post-silicon validation of ASICs, SoCs, or Retimer/PHY products\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of analog/mixed-signal circuit testing and debugging techniques\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with JTAG, I2C, SPI, and other embedded interfaces\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with PCB design, schematic reading, and signal integrity concepts\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of data center systems architecture (servers, AI platforms, networking equipment)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Understanding of ATE (Automated Test Equipment) systems and production test methodologies\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with defect screening methodologies including visual inspection, electrical testing, and acoustic imaging\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with complete RMA lifecycle management from intake through root cause analysis and corrective action\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of common semiconductor failure modes and failure analysis techniques including die attach inspection, delamination detection, void analysis, and crack identification\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with formal compliance testing and industry standards\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;The base salary range is $160,000.00 USD – $230,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.\u0026amp;nbsp;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025526005,"name":"Hardware Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4674410005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4425364005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Hardware Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Contract","value_type":"single_select"}],"id":4674410005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2372","title":"Hardware Lab Technician ","company_name":"Astera Labs","first_published":"2026-04-07T21:00:43-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;u\u0026gt;Overview\u0026lt;/u\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs Inc. is seeking a proactive and self-driven \u0026lt;strong\u0026gt;Hardware Lab Technician\u0026lt;/strong\u0026gt; to join our team in developing world class connectivity products for AI infrastructure.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;u\u0026gt;Job Description\u0026lt;/u\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This role works closely with various teams within our lab, including SI/PI, validation, design, NPI, and more. You will also be responsible for organizing and managing an inventory of consumables and peripherals while providing comprehensive support for lab infrastructure and daily operations. The ideal candidate will have hands-on technical skills, a strong work ethic, and the ability to manage various responsibilities in a fast-paced, collaborative environment.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;u\u0026gt;Key Responsibilities\u0026lt;/u\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Operate a manual probe station (MPI TS600-PCB) to probe printed circuit boards and components\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Perform DC and signal integrity measurements on PCBs and evaluation hardware\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Manage critical inventories of Astera products, tools, consumables, and peripherals, including purchasing, organizing, monitoring, and forecasting\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Assemble, inspect, and test modules/subassemblies\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Optimize and maintain lab organization\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Monitor compliance with lab policies, including ESD, cleanliness, food/drink, etc.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Assist engineers with various other hands-on tasks, including soldering and rework of SMDs on high-density PCBAs\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;u\u0026gt;Required Qualifications\u0026lt;/u\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;1 year of experience in a hardware lab environment\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;1 year of manual probe station experience\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Associate’s degree or equivalent technical certification in electronics engineering, electrical engineering, computer engineering, or a similar field\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Self-starter with a bias towards action\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong organizational skills and attention to detail\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Effective and clear communication, both written and verbal\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ability to lift and move up to 40lbs safely\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;u\u0026gt;Preferred Qualifications\u0026lt;/u\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;2 years of manual probe station experience\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;2 years of inventory management experience\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Comfortable performing solder rework on 0201 components, micro-coax cables, and fly line/magnet wire\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Fluent in interpreting circuit schematics and board layouts\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ability to troubleshoot and debug PCBAs using oscilloscopes, multimeters, power supplies, etc.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with Python, Bash, and/or Linux\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ability to clearly document and communicate findings and measurement results\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;p\u0026gt;The base salary range is $135,000 USD - $165,000 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.\u0026lt;/p\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;/div\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025526005,"name":"Hardware Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4701246005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4438344005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose (HQ)","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Human Resources","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4701246005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2597","title":"HR Operations \u0026 People Analytics Lead","company_name":"Astera Labs","first_published":"2026-05-29T20:46:02-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Role Overview\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Astera Labs is seeking an \u0026lt;strong\u0026gt;HR Operations \u0026amp;amp; People Analytics Lead\u0026lt;/strong\u0026gt; to help scale and strengthen our HR infrastructure during a period of rapid growth. This individual contributor role will report to the Director, HR Operations and will sit at the intersection of HR operations, systems, process execution, and workforce analytics.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;This role is ideal for someone who enjoys owning high-impact operational work end-to-end while also building\u0026amp;nbsp;the dashboards, reporting, and insights that help HR and business leaders make better decisions. The right candidate is highly detail-oriented, systems-minded, analytically strong, and comfortable working across both day-to-day execution and longer-term process improvement.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;You will partner closely with HR, Talent Acquisition, IT, Finance, and business stakeholders to improve employee lifecycle processes, strengthen HR data integrity, support system optimization, and develop meaningful\u0026amp;nbsp;people\u0026amp;nbsp;insights. This is an opportunity to play a key role in building\u0026amp;nbsp;a scalable, data-driven, and AI-enabled HR Operations function at Astera Labs.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;HR Operations Execution\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt; \u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;Own and execute core HR operational processes across the employee lifecycle, including preboarding, onboarding, offboarding, employee changes, and related system updates \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;Ensure timely, accurate, and consistent processing of employee data and HR transactions across systems \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;Partner with regional HR and internal stakeholders to support smooth execution of global HR processes while accounting for local requirements \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;Help document, standardize, and continuously improve HR workflows, SOPs, and operational practices\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;HR Systems, Data Integrity \u0026amp;amp; Process Improvement\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Support the ongoing optimization of\u0026amp;nbsp;Darwinbox\u0026amp;nbsp;and related HR systems to improve workflows, usability, and data accuracy\u0026lt;/span\u0026gt; \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;Maintain strong data governance and audit discipline across employee records, workflows, and reporting inputs \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;Identify and resolve process gaps, recurring errors, and manual handoffs that create inefficiency or risk \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;Partner across HR, IT, Finance, and Talent Acquisition on system improvements, integrations, and automation opportunities\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;People Analytics, Dashboarding \u0026amp;amp; Reporting\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Build,\u0026amp;nbsp;maintain, and improve HR dashboards and recurring reports across headcount, hiring, onboarding, attrition, and other key workforce metrics\u0026lt;/span\u0026gt; \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;Analyze HR data and translate findings into clear insights and recommendations for HR and business stakeholders \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;Support workforce planning, headcount tracking, and operational reporting needs with reliable and actionable data \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;Help establish scalable reporting practices, data definitions, and governance standards across HR systems\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Employee Experience \u0026amp;amp; Self-Service\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Support employee- and manager-facing HR processes with a strong service mindset and focus on ease of use\u0026lt;/span\u0026gt; \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;Identify opportunities to improve self-service, reduce manual support, and create a more streamlined employee experience \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;Partner on initiatives that improve process clarity, training, and adoption of HR tools and workflows \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;Help scale HR operations in a way that balances efficiency, compliance, and employee experience\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Cross-Functional Project Support\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Drive and support projects related to HR operations, systems optimization, reporting, and process automation\u0026lt;/span\u0026gt; \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;Partner with the Director, HR Operations to execute priority initiatives and operational improvements \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;Coordinate across stakeholders to ensure timelines, dependencies, risks, and follow-ups are managed effectively \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;Bring structure, ownership, and follow-through to fast-moving cross-functional work\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Basic Qualifications\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Bachelor’s degree in Human Resources, Business Administration, Information Systems, Analytics, or related field\u0026lt;/span\u0026gt; \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;6+ years of experience in HR Operations, HRIS, People Analytics, or related HR roles \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;Experience owning core HR operational processes across the employee lifecycle \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;Strong experience with HR reporting, dashboards, data analysis, and data management \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;Experience working with HR systems such as Darwinbox, Workday, SAP SuccessFactors, or similar platforms \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;Strong analytical, organizational, and problem-solving skills \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;High attention to detail and commitment to data accuracy, process quality, and operational excellence \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;Ability to work independently, manage multiple priorities, and collaborate effectively across functions\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Preferred Qualifications\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience in a high-growth technology or semiconductor environment\u0026lt;/span\u0026gt; \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;Hands-on experience with workforce reporting, dashboarding, and HR data visualization \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;Experience improving or implementing HR workflows, automation, and self-service processes \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;Familiarity with HR compliance, audits, and employee data governance practices \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;Experience partnering across HR, IT, Finance, and Talent Acquisition on systems and process initiatives \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;Comfort operating in ambiguity and building structure where processes are still evolving \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;Interest in leveraging AI and automation to improve HR service delivery and decision-making\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Salary range is $125,000 to $155,000 depending on experience, level, and business need. This role is eligible for discretionary bonus, incentives, and benefits.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4000202005,"name":"HR","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4701302005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4438375005,"location":{"name":"Tel Aviv-Yafo, Tel Aviv District, Israel"},"metadata":[{"id":12122734005,"name":"Country","value":"Israel","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Tel-Aviv","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Design Verification","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4701302005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2599","title":"Junior Design Verification Engineer","company_name":"Astera Labs","first_published":"2026-06-01T04:33:58-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is establishing a strategic R\u0026amp;amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical \u0026#39;data bottlenecks\u0026#39; enabling the future of AI at scale. As we expand our presence in Israel, we\u0026#39;re seeking a talented \u0026lt;strong\u0026gt;Junior Design Verification Engineer\u0026lt;/strong\u0026gt;\u0026amp;nbsp;to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, developing the verification environments that ensure our next-generation AI silicon performs flawlessly.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As a \u0026lt;strong\u0026gt;Junior Design Verification Engineer\u0026lt;/strong\u0026gt;, you will be a vital contributor to the quality and reliability of our Israel R\u0026amp;amp;D center. You will work on the front lines of functional verification, developing testbenches and environments that validate high-performance digital blocks, subsystems, and full-chip designs. You will tackle complex verification challenges that ensure our connectivity solutions meet the rigorous demands of the world\u0026#39;s largest AI clusters. If you thrive on solving technical puzzles and want to play a key role in delivering cutting-edge AI infrastructure connectivity, this is your opportunity.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Verification Environment Development\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Contribute to the design and development of ASIC verification environments, focusing on unit-level and subsystem functional blocks\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Develop and maintain SystemVerilog/UVM-based components including traffic generators, monitors, and checkers to ensure robust testing\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Execute detailed verification plans for challenging digital designs, ensuring all functional requirements are met and verified\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Coverage \u0026amp;amp; Quality Assurance\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Implement functional coverage models and analyze results to identify gaps in the verification process\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Drive designs toward 100% verification closure through comprehensive test development\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Contribute to verification methodology improvements and best practices\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Debug \u0026amp;amp; Cross-Functional Collaboration\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Work closely with design engineers to identify, root-cause, and resolve complex hardware bugs early in the development cycle\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Apply analytical skills and debugging techniques to solve intricate verification challenges\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Collaborate effectively in a fast-paced, team-oriented R\u0026amp;amp;D environment\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,0,0\u0026quot;\u0026gt;Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,2,0\u0026quot;\u0026gt;Strong understanding of Digital Logic and at least one programming language (C/C++ or Python)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,3,0\u0026quot;\u0026gt;Basic familiarity with Verilog or SystemVerilog from academic projects or lab work\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,4,0\u0026quot;\u0026gt;A natural curiosity for \u0026quot;breaking things\u0026quot; and finding bugs, with a strong attention to detail\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,5,0\u0026quot;\u0026gt;Fluent in Hebrew and English with the ability to work effectively in a team environment\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Master\u0026#39;s degree in Electrical Engineering or related field\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Basic proficiency in scripting languages such as Python or Tcl to automate verification tasks\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Any prior exposure to UVM/OVM or constrained-random verification is a major plus\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Basic understanding of protocols like PCIe, Ethernet, or DDR\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4052111005,"name":"Haifa","location":"Haifa, Israel","child_ids":[],"parent_id":4008937005},{"id":4056876005,"name":"Tel Aviv","location":"Tel Aviv, Israel","child_ids":[],"parent_id":4008937005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4677747005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4427019005,"location":{"name":"Taipei, Taiwan"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Test Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4677747005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2413","title":"Lead ATE Test Engineer","company_name":"Astera Labs","first_published":"2026-03-30T00:16:48-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;Job Description\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;We are looking for Lead ATE Test Engineers with proven experience in developing and supporting complex mixed-signal silicon SoC products to lead ATE Test solutions. The ideal candidate will develop and oversee SoC test strategy, interact with manufacturing partners, define, and implement ATE programs and own the product from design, initial samples all the way through high volume production ramp. The candidate should have working knowledge of communication/interface protocols such as PCI-Express (Gen-4/5/6), Ethernet, DDR, NVMe, USB, etc.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Basic Qualifications\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, and a Master’s is preferred.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· ≥5-year experience releasing complex SoC/silicon products to high volume manufacturing.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Working knowledge of high-speed protocols like PCIe, Ethernet, DDR, NVMe, USB, etc.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Professional attitude with ability to execute on multiple tasks with minimal supervision.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Strong team player with good communication skills to work alongside a team of high caliber engineers and different OSAT’s.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Required Experience\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Hands-on experience with high-speed mixed signal SoC test program/hardware development on multiple high-speed test platforms.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Collaboration with design team to define test strategy, create and own test plan.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Familiar with high-speed load board design techniques.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Proven track record of implementing ATE patterns to optimize tester resources and minimize ATE test time while maintaining product quality.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Strong knowledge and development of DFT techniques implemented in silicon that provide maximum defect and parametric device coverage – SCAN, MEMBIST, SerDes and other functional tests.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Skilled in control interfaces – I2C, I3C, SPI, MDIO, JTAG etc.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Expertise in production test of high speed SerDes operating at 16Gbps and higher.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Skilled in ATE programming, silicon/ATE bring-up, bench-ATE correlation and debug.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Experience in bringing up test programs at OSATs.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Experience with using Advantest 93k ATE platform.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Proficiency in, at least, one modern programming language such as C/C++, Python.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Preferred Experience\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Fluent in data processing using high level programming languages.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Familiarity with modern databases\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4009035005,"name":"Taipei","location":"Taipei, Taiwan","child_ids":[],"parent_id":4002874005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4693668005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_optional","internal_job_id":4434718005,"location":{"name":"Shanghai Shi, China"},"metadata":[{"id":12122734005,"name":"Country","value":"China","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Shanghai","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Firmware Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4693668005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2522","title":"Lead Firmware Engineer","company_name":"Astera Labs","first_published":"2026-05-08T08:47:08-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;h4 id=\u0026quot;Job-Description\u0026quot; data-renderer-start-pos=\u0026quot;15\u0026quot;\u0026gt;Job Description\u0026lt;/h4\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;32\u0026quot;\u0026gt;The mission of this role is to architect and develop firmware and microcontroller subsystems for Astera Labs’ \u0026lt;span data-highlighted=\u0026quot;true\u0026quot; data-vc=\u0026quot;highlighted-text\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;_kqswh2mm\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;_5pioz8co _189eyh40 _1il9buyh _19lcevot _d0altlke\u0026quot; data-testid=\u0026quot;definition-highlighter\u0026quot;\u0026gt;SoC\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt; and systems products. Firmware is responsible for implementing the major differentiating features of Astera Labs’ products. As such, firmware is considered equally important to the hardware, and the firmware team is often customer-facing accordingly to ensure the needs of the customer are fully comprehended.\u0026lt;/p\u0026gt;\n\u0026lt;h4 id=\u0026quot;Basic-qualifications\u0026quot; data-renderer-start-pos=\u0026quot;457\u0026quot;\u0026gt;Basic qualifications\u0026lt;/h4\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-indent-level=\u0026quot;1\u0026quot;\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;481\u0026quot;\u0026gt;Strong academic and technical background in Electronics/Electrical/Computer Science engineering. At a minimum, a Bachelor’s\u0026amp;nbsp;is required, and a Master’s is preferred.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;647\u0026quot;\u0026gt;Minimum 5 years’ experience supporting or developing complex \u0026lt;span data-highlighted=\u0026quot;true\u0026quot; data-vc=\u0026quot;highlighted-text\u0026quot;\u0026gt;SoC\u0026lt;/span\u0026gt;/silicon products for Server, Storage, and/or Networking applications.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;785\u0026quot;\u0026gt;Experience developing firmware to execute in on-chip microcontrollers as well as C-language software development kits (SDKs) to execute on system management controllers (e.g. \u0026lt;span data-highlighted=\u0026quot;true\u0026quot; data-vc=\u0026quot;highlighted-text\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;_kqswh2mm\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;_5pioz8co _189eyh40 _1il9buyh _19lcevot _d0altlke\u0026quot; data-testid=\u0026quot;definition-highlighter\u0026quot;\u0026gt;BMC\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;).\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;969\u0026quot;\u0026gt;Experience working with logic designers to architect and verify \u0026lt;span data-highlighted=\u0026quot;true\u0026quot; data-vc=\u0026quot;highlighted-text\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;_kqswh2mm\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;_5pioz8co _189eyh40 _1il9buyh _19lcevot _d0altlke\u0026quot; data-testid=\u0026quot;definition-highlighter\u0026quot;\u0026gt;HW-SW\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt; interfaces on complex SoCs.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;1070\u0026quot;\u0026gt;Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer meetings in advance, and to work with minimal guidance and supervision.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;1265\u0026quot;\u0026gt;Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h4 id=\u0026quot;Required-experience\u0026quot; data-renderer-start-pos=\u0026quot;1428\u0026quot;\u0026gt;Required experience\u0026lt;/h4\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-indent-level=\u0026quot;1\u0026quot;\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;1451\u0026quot;\u0026gt;\u0026lt;span data-highlighted=\u0026quot;true\u0026quot; data-vc=\u0026quot;highlighted-text\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;_kqswh2mm\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;_5pioz8co _189eyh40 _1il9buyh _19lcevot _d0altlke\u0026quot; data-testid=\u0026quot;definition-highlighter\u0026quot;\u0026gt;MQX\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt; \u0026lt;span data-highlighted=\u0026quot;true\u0026quot; data-vc=\u0026quot;highlighted-text\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;_kqswh2mm\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;_5pioz8co _189eyh40 _1il9buyh _19lcevot _d0altlke\u0026quot; data-testid=\u0026quot;definition-highlighter\u0026quot;\u0026gt;RTOS\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt; or ThreadX Development or enablement\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;1500\u0026quot;\u0026gt;High level of proficiency in C (preferred) or C++, including development of C-based SDKs\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;1592\u0026quot;\u0026gt;High level of proficiency in Python for automating pre-processors/post-processors and \u0026lt;span data-highlighted=\u0026quot;true\u0026quot; data-vc=\u0026quot;highlighted-text\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;_kqswh2mm\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;_5pioz8co _189eyh40 _1il9buyh _19lcevot _d0altlke\u0026quot; data-testid=\u0026quot;definition-highlighter\u0026quot;\u0026gt;FW\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt; \u0026lt;span data-highlighted=\u0026quot;true\u0026quot; data-vc=\u0026quot;highlighted-text\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;_kqswh2mm\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;_5pioz8co _189eyh40 _1il9buyh _19lcevot _d0altlke\u0026quot; data-testid=\u0026quot;definition-highlighter\u0026quot;\u0026gt;QC\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;1687\u0026quot;\u0026gt;Working knowledge of software/firmware build environments, gcc/Make, Doxygen, and GitHub.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;1780\u0026quot;\u0026gt;Hands-on experience with Server, Storage, and/or Networking equipment (e.g. Network Switches).\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;1878\u0026quot;\u0026gt;Familiarity with \u0026lt;span data-highlighted=\u0026quot;true\u0026quot; data-vc=\u0026quot;highlighted-text\u0026quot;\u0026gt;SoC\u0026lt;/span\u0026gt; interfaces to common IP blocks such as PCIe Controllers, \u0026lt;span data-highlighted=\u0026quot;true\u0026quot; data-vc=\u0026quot;highlighted-text\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;_kqswh2mm\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;_5pioz8co _189eyh40 _1il9buyh _19lcevot _d0altlke\u0026quot; data-testid=\u0026quot;definition-highlighter\u0026quot;\u0026gt;DDR\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt; Controllers, \u0026lt;span data-highlighted=\u0026quot;true\u0026quot; data-vc=\u0026quot;highlighted-text\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;_kqswh2mm\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;_5pioz8co _189eyh40 _1il9buyh _19lcevot _d0altlke\u0026quot; data-testid=\u0026quot;definition-highlighter\u0026quot;\u0026gt;NVME\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt; Controllers, \u0026lt;span data-highlighted=\u0026quot;true\u0026quot; data-vc=\u0026quot;highlighted-text\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;_kqswh2mm\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;_5pioz8co _189eyh40 _1il9buyh _19lcevot _d0altlke\u0026quot; data-testid=\u0026quot;definition-highlighter\u0026quot;\u0026gt;AMBA\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;/\u0026lt;span data-highlighted=\u0026quot;true\u0026quot; data-vc=\u0026quot;highlighted-text\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;_kqswh2mm\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;_5pioz8co _189eyh40 _1il9buyh _19lcevot _d0altlke\u0026quot; data-testid=\u0026quot;definition-highlighter\u0026quot;\u0026gt;AHB\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt; interfaces, on-chip memory interfaces, and other similar interfaces\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;2071\u0026quot;\u0026gt;Direct experience working on products with high-speed interfaces common in Data Center equipment: \u0026lt;span data-highlighted=\u0026quot;true\u0026quot; data-vc=\u0026quot;highlighted-text\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;_kqswh2mm\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;_5pioz8co _189eyh40 _1il9buyh _19lcevot _d0altlke\u0026quot; data-testid=\u0026quot;definition-highlighter\u0026quot;\u0026gt;PCI\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;- Express (Gen-3 and above), 100/400G Ethernet, Infiniband, \u0026lt;span data-highlighted=\u0026quot;true\u0026quot; data-vc=\u0026quot;highlighted-text\u0026quot;\u0026gt;DDR\u0026lt;/span\u0026gt;, \u0026lt;span data-highlighted=\u0026quot;true\u0026quot; data-vc=\u0026quot;highlighted-text\u0026quot;\u0026gt;NVMe\u0026lt;/span\u0026gt;, USB, etc.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Deep understanding of the L1, L2 and L3(good to have), and solid understanding of the IEEE 802.3(802.3df, 802.3db (good to have), 802.3de, 802.33dd)\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Experience developing the firmware for any of the TCP/IP based SoC (switch SoC or NIC function SoC) focusing on all aspects of RAS and its interface development for better user experience.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h4 id=\u0026quot;Preferred-experience\u0026quot; data-renderer-start-pos=\u0026quot;2256\u0026quot;\u0026gt;Preferred experience\u0026lt;/h4\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-indent-level=\u0026quot;1\u0026quot;\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;2280\u0026quot;\u0026gt;Experience developing firmware to execute in on-chip microcontrollers as well as C-language SDKs to execute on system management controllers (e.g. \u0026lt;span data-highlighted=\u0026quot;true\u0026quot; data-vc=\u0026quot;highlighted-text\u0026quot;\u0026gt;BMC\u0026lt;/span\u0026gt;)\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;2435\u0026quot;\u0026gt;Experience developing embedded firmware for PCIe or Ethernet Switch products\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;2515\u0026quot;\u0026gt;Experience with industry forums and collaboration workgroups such as \u0026lt;span data-highlighted=\u0026quot;true\u0026quot; data-vc=\u0026quot;highlighted-text\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;_kqswh2mm\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;_5pioz8co _189eyh40 _1il9buyh _19lcevot _d0altlke\u0026quot; data-testid=\u0026quot;definition-highlighter\u0026quot;\u0026gt;OCP\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt; and OpenBMC\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025528005,"name":"Software Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4002878005,"name":"Shanghai","location":"Shanghai, China","child_ids":[],"parent_id":4002875005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4655216005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4416824005,"location":{"name":"Bangalore, India"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Firmware Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4655216005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2257","title":"Lead Firmware QA Engineer","company_name":"Astera Labs","first_published":"2026-02-01T15:26:58-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Title\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;: \u0026lt;strong\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Lead Firmware QA Engineer\u0026lt;/span\u0026gt;, A\u0026lt;/strong\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;stera Labs, Bengaluru, India.\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;br\u0026gt;\u0026amp;nbsp;\u0026lt;br\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Astera Labs Inc., a leader in purpose-built connectivity solutions for data-centric systems, is seeking \u0026lt;strong\u0026gt;Lead Software QA Engineer\u0026lt;/strong\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt; for their Bengaluru (India) Design Center. Partnering with leading processor and GPU vendors, cloud service providers, world-class manufacturing companies, Astera Labs is helping data-centric system designers remove performance bottlenecks in compute-intensive workloads such as Artificial Intelligence and Machine Learning.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134245417\u0026amp;quot;:false}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;:\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s degree in electrical engineering (EE) or Computer Science is required; a master’s or PhD in EE is preferred with minimum 4 years of experience.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Experience\u0026lt;/strong\u0026gt;:\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experienced and detail oriented PCIe switch test engineer with solid understanding of PCIe protocol.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Estimate work, identify dependencies and develop schedules.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Responsible for designing and executing functional, performance, interoperability and stress tests.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work closely with\u0026amp;nbsp; Silicon team, architecture team, FW development team to understand the design and develop test strategies.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Responsible for manual and automation testing.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong knowledge of scripting ( Python ) is must.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Responsible for automation development and manual testing.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Perform Signal integrity and protocol level validation.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Closely work with development teams to triage and debug issues.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of collecting PCIe trace using PCIe analyzer and analyzing the trace to triage issues.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience in PRBS testing, loopback and margining tests.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Good understanding of OOB testing and Protocols like MCTP, I2C, SPDM etc.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience is PCIe compliance testing is a plus.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Regularly working with Hyperscale\u0026#39;s and Tier 1 OEMs to communicate plans and status, address escalations, deliver on SLAs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge in validation of NIC controllers and storage controllers is preferred.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Requirements management and traceability through software development phases.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Mentoring and coaching team members to help them excel in their jobs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Power user of Git, Jira and Confluence.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025528005,"name":"Software Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4049113005,"name":"Bengaluru","location":"Bengaluru, India","child_ids":[],"parent_id":4052109005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4602437005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4391605005,"location":{"name":"Taipei,Taiwan "},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Engineering Operations","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4602437005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"1917","title":"Lead HVM Product Engineer ","company_name":"Astera Labs","first_published":"2025-08-29T01:48:10-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Job Description:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As an Astera Labs HVM Product and Test Engineering, you will support existing products already in HVM (high volume manufacturing) at our Asia OSAT partners. Maintaining smooth manufacturing to ensure on-time customer shipments is one key objective. In this role, you will complement the New Product Introduction Product Engineers as products are released into production and own the engineering manufacturing during mass production. The ideal candidate possesses breadth of industry experience in high-speed product development in the field of product and/or test engineering, can apply fundamentals in circuit, ATE, and test program to aid problem solving, and is a self-driven, result focused go-getter in the pursuit of goals and objectives.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic qualifications:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Minimum of 5 years of experience in the field of post silicon product development dealing with high-speed XCVR (product, test or validation)\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Experience in working with PCIe Gen3 and above\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Have gone through at least one cycle of full product development life cycle\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Strong academic/technical background in electrical or computer engineering; Bachelor’s is required; MS preferred\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Strong problem-solving skills that involve system level analysis with test hardware, test program and DUT.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Digital and analog circuit level understanding for DUT.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Excellent team player with great communication skills\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Professional attitude with the ability to prioritize a dynamic list of multiple tasks\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required experience:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Proven track record continuing seamless production of semiconductor products partnering with OSATs supporting high volume manufacturing through the complete product lifecycle\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Hands on experience with using the Advantest 93k ATE platform with specific skills updating ATE test programs for wafer sort and final test solutions\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Hands-on knowledge of NRZ/PAM4 SerDes protocols like PCIe (Gen3 and above), Ethernet (25G and above), etc. and/or memory interfaces such as (LP)DDR5/4.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Detailed mindset monitoring device ATE test yields, ATE test time, device quality and rolling out new ATE test programs using consistent BKMs\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Strong data analysis skills using tools such as JMP or Spotfire calculating limits and drawing conclusions\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Energetic work mindset meeting the demands of shipping quality parts to Astera Labs’ customers through the manufacturing stage of development\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred experience:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Working with silicon validation teams to ensure device performance meets production requirements.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Firmware development in C/C++, scripting in Python, or other equivalent programming experience.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;· Hands on experience in product/package qualification\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4009035005,"name":"Taipei","location":"Taipei, Taiwan","child_ids":[],"parent_id":4002874005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4677686005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4426991005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Engineering Operations","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4677686005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2411","title":"Lead Product Engineer","company_name":"Astera Labs","first_published":"2026-03-25T19:04:43-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is seeking a Tech Lead Product Engineer to join our team in San Jose, CA. In this role, you will be at the intersection of silicon development and production excellence, ensuring our industry-leading connectivity solutions meet the highest standards of performance, reliability, and quality as they scale to volume production.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As a key technical contributor, you will own the RF and signal integrity aspects of product engineering — from silicon characterization and validation through production test development and customer-facing debug. You\u0026#39;ll work across the full product lifecycle, partnering with design, applications, and operations teams to drive our connectivity products from tape-out to high-volume manufacturing. This is a high-impact role at a company experiencing explosive growth, where your work directly enables the AI infrastructure revolution.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;With Astera Labs\u0026#39; portfolio spanning PCIe retimers, Ethernet solutions, and next-generation switching silicon operating at the bleeding edge of SerDes performance, you\u0026#39;ll tackle some of the most demanding RF and physical layer challenges in the semiconductor industry.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Silicon Characterization \u0026amp;amp; Validation\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Lead RF and signal integrity characterization of high-speed SerDes across PCIe Gen 6/7, Ethernet, and UALink/UCI interfaces\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Perform bench measurements using high-speed oscilloscopes, VNAs, BERTs, and TDRs to validate silicon performance against specifications\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Analyze S-parameters, eye diagrams, jitter, and channel loss to characterize physical layer performance across PVT corners\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Drive silicon qualification and reliability testing to ensure products meet production readiness criteria\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Production Test Development\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Develop and optimize ATE test programs for RF and high-speed I/O parametric testing\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Define test coverage strategies that balance quality, cost, and throughput for volume manufacturing\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Correlate bench characterization results with ATE measurements to ensure production screening effectiveness\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Partner with OSAT and test vendors to bring up and qualify production test hardware and loadboards\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Customer Debug \u0026amp;amp; Applications Support\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Provide RF and physical layer expertise to support customer platform bring-up and debug activities\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Analyze field returns and customer escalations related to signal integrity and link performance issues\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Develop reference measurement methodologies and application notes for high-speed interfaces\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Collaborate with applications engineering to resolve interoperability challenges across diverse customer platforms\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional Engineering Collaboration\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Partner with silicon design teams to provide characterization feedback that informs next-generation product improvements\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Drive DFT and design-for-manufacturing improvements based on production test learnings\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Contribute to product specifications and datasheet development with measured silicon performance data\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, RF Engineering, or a related field\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;5+ years of experience in product engineering, RF characterization, or signal integrity for high-speed semiconductor products\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Hands-on experience with RF/SI lab equipment including high-bandwidth oscilloscopes, vector network analyzers, BERTs, and TDRs\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Strong understanding of high-speed SerDes physical layer concepts including equalization, jitter analysis, S-parameters, and channel modeling\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience with ATE test development and production test methodologies for high-speed I/O\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Proficiency in data analysis and scripting (Python, MATLAB, or similar)\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Master\u0026#39;s degree in Electrical Engineering with emphasis on RF, microwave, or signal integrity\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience with PCIe, Ethernet, or CXL/UALink interface specifications and compliance testing\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Familiarity with high-speed connector/channel design and PCB stackup optimization\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience with statistical analysis techniques (Cpk, GRR, outlier screening) for production test\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Strong communication skills with the ability to present complex RF concepts to cross-functional audiences and customers\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Prior experience at a fabless semiconductor company operating in high-growth environments\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;The salary range for this position is $133,200 to $185,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4652615005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4415515005,"location":{"name":"Suzhou Qu, Gansu, China"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Business Operations","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4652615005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2227","title":"Manager, Hardware Sourcing ","company_name":"Astera Labs","first_published":"2026-01-23T06:44:05-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet,\u0026amp;nbsp;NVLink, PCIe®, and\u0026amp;nbsp;UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored\u0026amp;nbsp;architectures\u0026amp;nbsp;to meet their unique infrastructure requirements. Discover more at \u0026lt;/span\u0026gt;\u0026lt;a href=\u0026quot;http://www.asteralabs.com/\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-charstyle=\u0026quot;Hyperlink\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/a\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:259}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;About Astera Labs\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:259}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) is a pioneering fabless semiconductor company headquartered in Silicon Valley, driving the evolution of AI and cloud infrastructure through purpose-built connectivity solutions. As a leader in rack-scale architecture, Astera Labs is enabling the shift to AI Infrastructure 2.0, where\u0026amp;nbsp;compute\u0026amp;nbsp;is optimized at the rack level to support the demands of next-generation workloads.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:259}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Our portfolio includes high-performance silicon, software, and system-level solutions that address critical bottlenecks in data movement across compute, memory, and networking domains. Leveraging technologies such as PCIe®, CXL®, Ethernet, and\u0026amp;nbsp;UALink™, we deliver scalable, interoperable platforms that empower hyperscale data centers to deploy AI and cloud services with greater efficiency and flexibility.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:259}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;We are committed to open standards, software-defined architectures, and continuous innovation as we work to expand our product offerings and customer engagements. We foster a collaborative environment for professionals passionate about solving complex challenges and shaping the future of intelligent infrastructure.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:259}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Job Description:\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:259}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;We are\u0026amp;nbsp;seeking a strategic and results-oriented\u0026amp;nbsp;Hardware Sourcing\u0026amp;nbsp;Manager to\u0026amp;nbsp;lead sourcing initiatives across\u0026amp;nbsp;the\u0026amp;nbsp;component, PCB, PCBA, mechanical parts, etc.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:259}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;In this role, you will partner with cross-functional teams to develop and execute sourcing strategies that align with Astera Labs’ technology roadmap and business objectives. You’ll play a key role in identifying and securing the tools, platforms, and partnerships that power our silicon innovation, while driving cost optimization, supplier performance\u0026amp;nbsp;and long-term value.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:259}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;This is a unique opportunity to influence the sourcing strategy behind cutting-edge products and help scale a fast-growing company at the forefront of AI and cloud infrastructure.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:259}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:259}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;11\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Develop and execute category sourcing strategies for\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;c\u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;omponent, PCB,\u0026amp;nbsp;PCBA, mechanical parts, etc.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:259}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;11\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Partner with R\u0026amp;amp;D and engineering teams to align sourcing strategies with technology roadmaps and product development timelines.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:259}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;11\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Analyze industry trends, supplier capabilities\u0026amp;nbsp;and cost structures to identify opportunities for risk mitigation\u0026amp;nbsp;and cost savings.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:259}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;11\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Drive supplier relationship management programs to ensure performance, compliance\u0026amp;nbsp;and continuous improvement.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:259}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;11\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Build and maintain should-cost models, total cost analyses\u0026amp;nbsp;and financial assessments for strategic deals.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:259}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Basic Qualifications\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:259}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;12\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Bachelor’s degree in Engineering, Supply Chain, Business\u0026amp;nbsp;or related\u0026amp;nbsp;field.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:259}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;12\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;7+ years of experience in\u0026amp;nbsp;sourcing, procurement\u0026amp;nbsp;or supplier management in PCBA area.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:259}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;12\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;5+ years of\u0026amp;nbsp;experience\u0026amp;nbsp;in\u0026amp;nbsp;components and PCBA level sourcing.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:259}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;12\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Proven track record of negotiating\u0026amp;nbsp;with suppliers\u0026amp;nbsp;on PCBA level.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:259}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;12\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Demonstrated ability to lead complex negotiations and manage supplier relationships across global teams.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:259}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;12\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Willingness to travel as needed for\u0026amp;nbsp;suppliers visiting\u0026amp;nbsp;and meeting.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:259}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4000201005,"name":"Business Operations","child_ids":[],"parent_id":null}],"offices":[{"id":4009038005,"name":"Suzhou","location":"Suzhou, China","child_ids":[],"parent_id":4002875005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4678037005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4427158005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Engineering Operations","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4678037005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2414","title":"Manager, Package Design Engineering","company_name":"Astera Labs","first_published":"2026-03-26T17:39:13-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is seeking a Manager, Package Design Engineering to lead and scale our Package Design team in San Jose. In this high-impact role, you\u0026#39;ll own the end-to-end delivery of advanced IC packaging solutions—from early architecture definition through production ramp—enabling the next generation of AI infrastructure and connectivity products.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As the semiconductor industry races toward chiplet-based architectures, 2.5D/3D integration, and ever-increasing bandwidth demands, packaging has become a critical differentiator. You\u0026#39;ll build and mentor a high-performing team while driving cross-functional execution with silicon architecture, SIPI, PCB, validation, manufacturing, and external partners including substrate vendors and OSATs. Your work will directly impact Astera Labs\u0026#39; ability to deliver industry-leading PCIe, CXL, and Ethernet connectivity solutions to the world\u0026#39;s most demanding hyperscale and AI customers.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This role offers the opportunity to shape design methodology, establish scalable standards, and enable chip-package-board co-design frameworks across multiple product lines in a fast-moving, innovation-driven environment.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Team Leadership \u0026amp;amp; Execution\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Build, mentor, and scale a high-performing package design engineering team with clear ownership, accountability, and execution flows\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Establish design templates, standards, and best-known methods (BKMs) across multiple concurrent programs\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead design reviews, audits, and issue resolution through bring-up and production ramp\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Package Design Delivery\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Own end-to-end package design execution including FCBGA/FCCSP, monolithic, multi-die, and chiplet-based designs from concept feasibility through tape-out and production\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Define and review substrate stack-ups, pad stacks, routing strategies, and design constraints to meet electrical, thermal, mechanical, and manufacturability requirements\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive technical tradeoffs across performance, cost, yield, and schedule, ensuring high-quality design closure and on-time delivery\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Cross-Functional Collaboration\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Partner with SIPI, silicon architecture, system/board design, and product teams to drive chip-package-board co-design and resolve system-level challenges\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with OSATs and substrate vendors to ensure design feasibility, manufacturability, and alignment with evolving design rules and technology roadmaps\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support adoption of advanced packaging technologies such as 2.5D, chiplet, CPO/CPC, and heterogeneous integration platforms\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Methodology \u0026amp;amp; Automation\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Develop and scale design methodologies and automation flows to improve efficiency, quality, and repeatability across the organization\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, Materials Science, or related field\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;10+ years of progressive experience in IC package design using tools such as Cadence Allegro APD/SiP\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;5+ years of leadership experience managing teams or technical organizations in IC packaging environments\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong hands-on expertise in end-to-end package design with proven delivery of HVM-ready FCBGA/FCCSP packages using Cadence APD tool\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with high-speed SerDes systems (PCIe Gen5/6/7, CXL, Ethernet 100G/200G/400G+) and advanced nodes (7nm, 5nm, 3nm)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep understanding of substrate technologies, stack-ups, routing constraints, assembly processes, and SI/PI fundamentals\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven experience working with OSATs and substrate vendors through development and production ramp\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience working with OSATs and substrate vendors through development and production ramp\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with advanced packaging architectures such as 2.5D/3D, chiplet, or heterogeneous integration\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Master\u0026#39;s degree in Electrical Engineering or related field\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with advanced packaging architectures such as 2.5D/3D, chiplet, or heterogeneous integration\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience implementing automation, scripting (Python, SKILL, Tcl), or workflow optimization\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Background in early package feasibility, platform evaluation, and technology roadmap development\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with chip floor planning, architecture, and system-level tradeoffs\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Exposure to SIPI modeling and analysis, thermal, and mechanical performance considerations\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;The base salary range is $230,000 USD – $265,000 USD. This position can be hired as a Manager Level or Director Level. Your base salary will be determined based on location, experience, and employees\u0026#39; pay in similar positions.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4693903005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_optional","internal_job_id":4434832005,"location":{"name":"Toronto, Ontario, Canada"},"metadata":[{"id":12122734005,"name":"Country","value":"Canada","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Toronto","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Physical Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4693903005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2529","title":"Manager, Physical Design Engineer","company_name":"Astera Labs","first_published":"2026-05-08T19:46:51-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is seeking a\u0026lt;strong\u0026gt; Physical Design Engineering Manager\u0026lt;/strong\u0026gt; to lead a team of physical design engineers at our Toronto site, driving the implementation of connectivity ASICs within our Signal Connectivity Group. This group is responsible for products that enable high-speed serial connectivity including PCIe retimers, Ethernet retimers, and signal conditioning solutions deployed across the world\u0026#39;s largest AI clusters and hyperscale data centers.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As an Physical Design Manager Engineering Manager, you will combine hands-on technical leadership with people management, owning physical design execution from RTL to GDSII while building and mentoring a high-performing team. You will drive floorplanning, place-and-route, timing closure, and sign-off for complex designs requiring deep understanding of high-speed physical layer interfaces and SerDes integration at TSMC advanced nodes.\u0026amp;nbsp;\u0026lt;strong\u0026gt;\u0026lt;u\u0026gt;This role is fully on-site at our Toronto location\u0026lt;/u\u0026gt;\u0026lt;/strong\u0026gt;.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;text-decoration: underline;\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, Computer Engineering, or a related field; Master\u0026#39;s preferred.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;10+ years of experience in physical design implementation of complex SoCs at advanced nodes (7nm and below).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;2+ years of experience leading teams or projects with demonstrated ability to mentor and develop engineers.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on expertise across the physical design flow: synthesis, place-and-route, CTS, extraction, timing closure, EM-IR, DRC/LVS, and equivalence checking.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency with Cadence Innovus and/or Synopsys Fusion Compiler/ICC2 and supporting toolchains.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong scripting ability in Tcl, Python, and/or Perl.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Professional attitude with the ability to prioritize a dynamic list of tasks, plan and prepare for customer meetings in advance, and work with minimal guidance.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;text-decoration: underline;\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Required Experience\u0026lt;/strong\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Build, lead, and mentor a physical design team, owning Physical Design execution and team development for Signal Connectivity Group products.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive block and top-level physical design implementation from floorplan through tapeout for retimer and signal conditioning ASICs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with RTL, DFT, STA, EMIR, and verification teams to drive design convergence from synthesis through sign-off.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work with IP vendors for both RTL and hard-macro integration, ensuring placement constraints and routing guidelines are met.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive team execution, hiring, career development, and sprint planning for the Toronto PD team.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Establish physical design best practices, flow improvements, and quality checks to scale execution across multiple concurrent programs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Coordinate with global PD teams (San Jose, Irvine, Bangalore) to ensure consistent methodology and design quality.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with Cadence and/or Synopsys physical design tools/flows.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span style=\u0026quot;text-decoration: underline;\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Preferred Experience/Nice to Have\u0026lt;/strong\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Deep understanding of high-speed SerDes physical layer, including equalization, CDR, and signal integrity considerations impacting physical design.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of physical layer timing challenges specific to high-speed serial interfaces.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Track record of building and scaling physical design teams through multiple tapeouts.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of agentic AI solutions for EDA automation.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Base salary range is CAD 180,000 to CAD 220,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives, and benefits.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000119005,"name":"Toronto","location":"Toronto, Canada","child_ids":[],"parent_id":4004709005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4699143005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4437478005,"location":{"name":"Haifa District, Israel"},"metadata":[{"id":12122734005,"name":"Country","value":"Israel","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Haifa","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Administration","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4699143005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2579","title":"Office Administration Manager","company_name":"Astera Labs","first_published":"2026-05-26T03:43:50-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is establishing a strategic R\u0026amp;amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical \u0026#39;data bottlenecks\u0026#39; enabling the future of AI at scale. As we expand our presence in Israel,\u0026lt;br\u0026gt;We are looking for an experienced and proactive Office Administration Manager to oversee the daily operations of our Haifa site and ensure a smooth, organized, and employee-focused work environment. This role combines office operations, facilities coordination, employee welfare, logistics, and administrative support.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Manage day-to-day office operations and administrative processes\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support employee welfare initiatives, site events, and office experience activities\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Coordinate office facilities, maintenance, and vendor relationships\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Handle procurement and operational purchasing activities\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Manage office logistics, including import/export coordination\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Monitor office supplies, services, and operational budgets\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support onboarding and offboarding processes, including seating arrangements and site setup\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Coordinate meetings, office activities, and cross-functional operational needs\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work closely with HR, Finance, IT, and leadership teams to support site operations\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;span id=\u0026quot;message-body-1779780795806\u0026quot; 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class=\u0026quot;fui-Primitive ___11tzqds f1oy3dpc f89hs3r fqtknz5 fyvcxda\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience in logistics operations in Israel, including managing courier and delivery service providers\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;span id=\u0026quot;message-body-1779780795806\u0026quot; class=\u0026quot;fui-ChatMyMessage__body rxadtj ___1sow1r8 f10pi13n ftqa4ok f2hkw1w f8hki3x f1d2448m f1bjia2o ffh67wi f1j6vpng f1pniga2 f987i1v f1ffjurs f15bsgw9 f14e48fq f18yb2kv fd6o370 ffwy5si f3znvyf f57olzd f4stah7 f480a47 fs1por5 fk6fouc figsok6 fkhj508 f19n0e5 f9ijwd5 f1q0nqlt f1o0qvyv f9ggezi f1xp5gbu f150uoa4 ffyari3 fo7qwa0 f16xkysk fxowb0n f11ghf3q f13aoclr flypziy f10kwr27 fquw1qa fftr39l f13lathq f15hsm81 f2ss68y ffb60jq f8nuap2 f13nk4fk f7jacry fq08z5q fd9af6s fr74w9q fcl9uv6 f13sm7pj f1u6qqly f16wpxbl faim3u9 f6cs3qo fa2w2z3 fd39nx6 f10gn8j9 frcqmxy f1w9ws4k f1ddxkqj fd10euv fvuz61 f1nbc6gw f1h272qk f1ywigw8 fzvs3e4 f1rvyk3c f5fplu3 f1l4y2qi f4yr49c fxgblah faww4f1 f1oqrsiv f1nn8nf5 f1wss724 f2ub9nf fpr7uzl f86vlxv f7ay0zw f1j33hpw fp3omr5 fpqnlqw f1y5pldk f16ozm6t f83zfrz f1ygr8g5 f1bt2lqj f1dfpw40 f1sapace f1eq4dpx fim7mkj fdc55jo f16aewt4 frche94 f1pn7o2n fg127dc fanjz1e f6h47bw ffd45wr f1j14d18\u0026quot;\u0026gt;\u0026lt;span id=\u0026quot;content-1779780795806\u0026quot; class=\u0026quot;fui-Primitive ___11tzqds f1oy3dpc f89hs3r fqtknz5 fyvcxda\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;3–7 years of experience in office administration, operations, or office management roles\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong organizational and multitasking abilities\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent communication and interpersonal skills\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience working with vendors, contractors, and service providers\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ability to work independently in a dynamic, fast-paced environment\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency in Microsoft Office tools\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;High level of ownership, service orientation, and attention to detail\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4135902005,"name":"Facilities","child_ids":[],"parent_id":null}],"offices":[{"id":4052111005,"name":"Haifa","location":"Haifa, Israel","child_ids":[],"parent_id":4008937005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4586713005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4383619005,"location":{"name":"Multiple Locations"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Human Resources","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4586713005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"1833","title":"Open Application - Join Our Talent Network! ","company_name":"Astera Labs","first_published":"2025-07-15T17:15:27-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;h3\u0026gt;\u0026lt;strong\u0026gt;Why Apply Now?\u0026lt;/strong\u0026gt;\u0026lt;/h3\u0026gt;\n\u0026lt;p\u0026gt;Even if there’s no active posting for your expertise, we’re always on the lookout for exceptional talent to join our future product and team innovations. We are considering resume of all levels.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Early connection: Be on our radar for upcoming openings that match your skills\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Show your passion: Tell us how you can contribute to enterprise‑scale AI connectivity\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Stay informed: Receive priority updates on relevant job opportunities at Astera Labs\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h3\u0026gt;\u0026lt;strong\u0026gt;Who We Want to Meet\u0026lt;/strong\u0026gt;\u0026lt;/h3\u0026gt;\n\u0026lt;p\u0026gt;We welcome professionals across disciplines, including but not limited to:\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Hardware Engineering (ASIC, mixed‑signal, PCB)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Firmware \u0026amp;amp; Embedded Systems (CXL, PCIe, DDR)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Software \u0026amp;amp; Validation (Firmware QA, system validation, diagnostic SW)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Product \u0026amp;amp; Program Management\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Operations \u0026amp;amp; HR\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Sales, Customer Programs, and Field Applications\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs champions diversity in technical expertise and career stages from senior engineers and managers to internship candidates across all functions.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4141519005,"name":"Open Application","child_ids":[],"parent_id":null}],"offices":[{"id":4019546005,"name":"United States","location":null,"child_ids":[4055745005,4019545005,4050370005,4017614005,4000118005,4053188005,4000148005],"parent_id":null}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4693807005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4434779005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose (HQ)","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"CTO Organization","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4693807005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2526","title":"Optical Firmware Engineer, Principal ","company_name":"Astera Labs","first_published":"2026-05-15T13:08:50-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;div class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;We are seeking to hire an Optical Firmware Engineer, Principal develop, optimize, and maintain embedded firmware for optical engines, photonic integrated circuits (PICs) optical modules. This includes control of lasers, modulators, photodetectors, thermal management, calibration, and high-speed link optimization in silicon photonics systems. The role sits at the intersection of embedded systems, photonics, and hardware.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Design, develop, and debug real-time firmware for optical transceivers or PIC/EIC engines (e.g., in C/C++ for microcontrollers or embedded processors).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Implement algorithms for laser control, automatic power control (APC), temperature compensation, wavelength locking, and link training/adaptation.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Integrate firmware with hardware (DSP, drivers, ADCs/DACs) and higher-level software (e.g., via I2C, SPI, or custom interfaces).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop diagnostic, calibration, and telemetry features for manufacturing test, field monitoring, and reliability.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Optimize for low latency, power efficiency, and high reliability in high-speed (400G/800G/1.6T+) optical links.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with optical, electrical, DSP, and system validation teams to characterize and tune performance.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support bring-up, debugging, and qualification of silicon photonics prototypes.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Handle firmware updates, version control, and compliance with standards (e.g., OIF, CMIS).\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Qualifications:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;BS/MS/PhD in Electrical Engineering, Computer Engineering, Physics, or related field + 12+ years of industry experience.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong experience in embedded firmware development (bare-metal or RTOS) for optical or high-speed communication systems.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of photonics concepts: lasers, modulators, photodiodes, TIA, thermal tuning.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency in C/C++, Python (for scripting/tools), and debugging tools (JTAG, oscilloscopes, optical test equipment).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with high-speed SerDes, signal integrity, or optical link optimization is a plus.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with silicon photonics, or pluggable optics (QSFP, OSFP) is highly valued.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;/div\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4140921005,"name":"Optical","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4696245005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4436237005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose (HQ)","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"CTO Organization","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4696245005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2556","title":"Optical Test Engineering, Senior Director","company_name":"Astera Labs","first_published":"2026-06-05T15:34:33-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;div class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;h1\u0026gt;Senior Director, Optical Test Engineering\u0026lt;/h1\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;h2\u0026gt;Position Overview\u0026lt;/h2\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;We are seeking an experienced \u0026lt;strong\u0026gt;Senior Director of Optical Test Engineering \u0026lt;/strong\u0026gt;to lead the development, validation, and manufacturing support of advanced integrated optical interconnect solutions. This role focuses on optical-electrical integration at the module level, bridging transceiver and compute platform interfaces with comprehensive test strategy and execution.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;h2\u0026gt;Key Responsibilities\u0026lt;/h2\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;h3\u0026gt;Strategic Leadership\u0026lt;/h3\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Define and execute the optical test engineering roadmap for next-generation interconnect architectures\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Establish testing methodologies and standards for tightly integrated optical-electrical assemblies\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Lead cross-functional teams across optical design, electrical engineering, manufacturing, and quality\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Develop partnerships with ecosystem partners on test protocols and validation requirements\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;h3\u0026gt;Technical Program Management\u0026lt;/h3\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Oversee test strategy development for optical modules with embedded or adjacently mounted optical components\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Drive creation of comprehensive test plans covering optical performance, electrical performance, thermal management, and reliability\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Establish acceptance criteria and performance benchmarks aligned with data center and enterprise requirements\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Manage test equipment specifications, procurement, and deployment across manufacturing sites\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;h3\u0026gt;Validation \u0026amp;amp; Reliability\u0026lt;/h3\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Champion accelerated life testing programs for integrated optical-electrical systems\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Develop diagnostic and characterization protocols for novel optical assembly approaches\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Lead root-cause analysis on field failures and manufacturing defects\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Ensure compliance with industry standards (IEEE, IEC, Telcordia) and customer specifications\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;h3\u0026gt;Engineering Team Development\u0026lt;/h3\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Build and mentor a team of optical test engineers, technicians, and process specialists\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Foster innovation in test methodology and automation\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Develop talent pipeline and career advancement opportunities\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Promote continuous learning in optical testing technologies and practices\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;h3\u0026gt;Manufacturing Support\u0026lt;/h3\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Collaborate with manufacturing operations on yield improvement and test efficiency\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Establish in-line test protocols and inline measurement strategies\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Support transition from development to production testing\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Drive test cost reduction through automation and optimization\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;h2\u0026gt;Required Qualifications\u0026lt;/h2\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Experience:\u0026lt;/strong\u0026gt; 15+ years in optical engineering, with 5+ years in test engineering leadership\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Technical Expertise:\u0026lt;/strong\u0026gt; \n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Deep knowledge of optical transceiver design and testing\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience with optical-electrical integration challenges\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Proficiency in optical characterization (loss, dispersion, eye diagrams, jitter)\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Fluency with high-speed electrical measurements and signal integrity\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Leadership:\u0026lt;/strong\u0026gt; Demonstrated success managing technical teams and cross-functional programs\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Industry Knowledge:\u0026lt;/strong\u0026gt; Understanding of data center interconnect architectures and requirements\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Problem-Solving:\u0026lt;/strong\u0026gt; Strong analytical and troubleshooting capabilities\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;h2\u0026gt;Preferred Qualifications\u0026lt;/h2\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience with 112G+ or 200G+ optical systems\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Familiarity with thermal management in high-density optical modules\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Knowledge of automated test equipment (ATE) programming and optimization\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Background in manufacturing process capability analysis\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Understanding of substrate technologies (silicon photonics, planar lightwave circuits)\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Advanced degree in Physics, Optical Engineering, Electrical Engineering, or related field\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Strategic vision and execution\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Technical depth and credibility\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Cross-functional collaboration\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Process improvement and lean manufacturing principles\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Data-driven decision making\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Communication with technical and executive audiences\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Change management\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Budget and resource management\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/div\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4140921005,"name":"Optical","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4696244005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4436236005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose (HQ)","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"CTO Organization","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4696244005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2555","title":"Optical Test Engineer, Tech Lead","company_name":"Astera Labs","first_published":"2026-05-19T12:23:54-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;div class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;We are seeking a world-class \u0026lt;strong\u0026gt;Senior Staff to Principal Optical Test Engineer\u0026lt;/strong\u0026gt; to lead the development and execution of advanced test strategies for \u0026lt;strong\u0026gt;Co-Packaged Optics (CPO)\u0026lt;/strong\u0026gt; solutions.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This senior role drives optical and electro-optical testing for next-generation high-bandwidth CPO modules and optical engines integrated with ASICs for AI, hyperscale data centers, and high-performance computing.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;You will architect test methodologies, develop hardware/software platforms, and enable high-volume manufacturing while ensuring world-class performance, reliability, and yield. This is a high-impact technical leadership position at the forefront of silicon photonics and co-packaged optics innovation.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Lead the definition, development, and qualification of comprehensive test solutions for CPO optical engines, including wafer-level, die-level, package-level, and system-level testing.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Design and implement optical test hardware and automation systems (e.g., active alignment, fiber array attachment, high-speed optical I/O characterization).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop test programs and methodologies for key photonic parameters: insertion loss, eye diagrams, BER, PAM4 signaling, optical power, wavelength, thermal performance, and reliability stress testing.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate closely with Silicon Photonics design, package engineering, product engineering, and manufacturing teams to optimize design-for-test (DFT) and manufacturability.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive yield improvement, failure analysis, and root-cause investigations for complex electro-optical failures in CPO assemblies.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Establish correlations between bench/lab validation, ATE production test, and system-level performance.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Mentor junior engineers and provide technical direction on test architecture, equipment selection, and best practices for high-channel-count, high-speed optics.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support qualification, reliability testing (e.g., HTOL, temperature cycling), and customer audits for CPO products.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Evaluate and integrate new test technologies, instrumentation, and automation frameworks to scale CPO production efficiently.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Contribute to roadmaps for next-generation CPO test capabilities (e.g., higher data rates, multi-wavelength, advanced packaging).\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Qualifications and Requirements\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Education:\u0026lt;/strong\u0026gt; MS or PhD in Electrical Engineering, Optical Engineering, Physics, or a related field.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Experience:\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;8+ years (Senior Staff) to 12+ years (Principal) of relevant experience in optical/photonic test engineering.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong background in \u0026lt;strong\u0026gt;Co-Packaged Optics (CPO)\u0026lt;/strong\u0026gt;, silicon photonics, or high-speed optical transceivers (800G/1.6T+).\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;Proven track record developing optical test solutions for wafer, package, or module-level testing in high-volume environments.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep expertise in optical test instrumentation (e.g., optical spectrum analyzers, BER testers, oscilloscopes, tunable lasers, power meters, fiber alignment systems).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with automated test equipment (ATE), Python/LabVIEW/C# test development, and statistical process control (SPC).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of PAM4 signaling, signal integrity, mixed-signal testing, and reliability standards for data center optics.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Skills and Experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience with CPO-specific challenges: active alignment, thermal management, laser integration, fiber attach, and co-packaged ASIC testing.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with industry standards (e.g., IEEE 802.3, OIF, CMIS) and working with hyperscalers or module vendors.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience in semiconductor foundry/OSAT ecosystems and transitioning from NPI to high-volume production.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Track record of technical leadership, patents, or publications in photonics test.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong problem-solving, communication, and cross-functional collaboration skills.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;/div\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4140921005,"name":"Optical","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4693784005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4434765005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose (HQ)","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"CTO Organization","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4693784005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2523","title":"Optical Validation Engineer, Tech Lead","company_name":"Astera Labs","first_published":"2026-05-28T18:45:48-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;div class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;We are seeking an experienced \u0026lt;strong\u0026gt;Optical (EIC/PIC) Validation Engineer\u0026lt;/strong\u0026gt; at the Senior to Principal level to lead the validation, characterization, and qualification of advanced photonic integrated circuits (PICs) closely integrated with electronic integrated circuits (EICs) multiple optical configurations.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This high-impact role focuses on ensuring the performance, reliability, and manufacturability of next-generation optical engines for high-speed data center, AI/ML, and telecom applications. The ideal candidate has deep expertise in electro-optical testing, system-level validation, and multiple optical integration challenges.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Lead end-to-end validation and characterization of Optical Engines integrating EIC and PIC in multiple Silicon Photonic architectures.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop comprehensive test plans, methodologies, and automation frameworks for optical, electrical, and electro-optical performance metrics (e.g., BER, eye diagrams, insertion loss, extinction ratio, receiver sensitivity, transmitter power).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Perform detailed characterization of key building blocks: modulators, photodetectors, lasers, waveguides, couplers, and high-speed EIC/PIC interfaces.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Validate co-packaged optics performance including high-speed electrical interfaces (SerDes, UCIe), thermal management, signal integrity, power integrity, and optical coupling efficiency.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Design and implement test setups for wafer-level, package-level, and system-level testing, including active alignment, thermal cycling, reliability stress, and environmental qualification.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate closely with PIC Design, EIC Design, Packaging, Test Engineering, and Manufacturing teams to close design-for-test (DfT) and design-for-manufacturability (DfM) gaps.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Analyze large datasets from validation runs, perform failure analysis, root cause investigation, and drive corrective actions.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support bring-up and debug of silicon photonics prototypes and optical modules.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Define and execute qualification plans per industry standards (Telcordia, GR-468, JEDEC, etc.).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Mentor junior engineers and contribute to intellectual property through patents and technical publications.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Qualifications \u0026amp;amp; Requirements\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Master’s or PhD in Electrical Engineering, Optical Engineering, Photonics, Physics, or related field.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;8+ years (Senior) to 12+ years (Principal) of hands-on experience in silicon photonics or optical transceiver validation.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong experience with EIC/PIC co-design validation, multiple Optical Configurations.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Expertise in high-speed optical and electrical testing: BER testers, sampling oscilloscopes, VNAs, spectrum analyzers, tunable lasers, optical power meters, and automated test equipment.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency with photonic test automation (Python, LabVIEW, or equivalent) and data analysis tools (JMP, MATLAB, Python/Pandas).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep understanding of optical coupling, thermal effects in 2.5D/3D packaging, and high-speed signal integrity challenges in CPO systems.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with industry standards for reliability and qualification of photonic components.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent problem-solving, communication, and cross-functional collaboration skills.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Direct experience validating production-grade silicon photonics modules for hyperscale data centers or AI clusters.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of advanced packaging technologies (2.5D, 3D stacking, hybrid bonding, interposers).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with high-speed SerDes (112G/224G PAM4) and optical I/O chiplets.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Track record of shipping high-volume optical products.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Publications or patents in silicon photonics or co-packaged optics.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/div\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4140921005,"name":"Optical","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4696246005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4436238005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose (HQ)","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"CTO Organization","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4696246005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2557","title":"Photonic Packaging Engineer, Principal ","company_name":"Astera Labs","first_published":"2026-05-19T12:19:17-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;We are seeking a visionary and technically strong \u0026lt;strong\u0026gt;Photonic Packaging Engineer, Principal \u0026lt;/strong\u0026gt;to lead the design, development, and productization of advanced packaging solutions for advanced optics. This role will drive the intersection of photonics, high-speed electronics, thermal management, and mechanical integration to enable next-generation data center and networking platforms.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;You will guide a multidisciplinary team through all phases of product realization—from concept and design through manufacturing scale-up—working closely with silicon photonics, electrical packaging, systems, and supply chain teams to achieve world-class optical and electrical performance.\u0026lt;/p\u0026gt;\n\u0026lt;h2\u0026gt;Key Responsibilities\u0026lt;/h2\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;Lead the end-to-end development of photonic packaging strategies for Silicon Photonics Modules, including EIC/PIC co-packaging, optical coupling, fiber attach, and thermal and mechanical design.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;Define technical requirements and package architectures that balance performance, manufacturability, and cost with compatibility with established electronic packaging flows.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;Collaborate with IC packaging, optical connector, and silicon photonics teams to achieve co-design optimization\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Build and mentor a high-performing team of packaging engineers and scientists.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;Drive supplier engagement and technology partnerships for packaging partnerships and innovations.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Oversee failure analysis, reliability testing, and yield improvement efforts.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;Contribute to the long-term package technology roadmap for advanced optical integration and scalability with ALAB\u0026#39;s signal connectivity portfolio.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h2\u0026gt;Qualifications\u0026lt;/h2\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Ph.D. or M.S. in Electrical Engineering, Physics, Materials Science, Mechanical Engineering, or related field.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;10+ years of experience in photonic packaging, optical transceivers, or advanced semiconductor packaging.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Proven expertise in high-speed optical/electrical packaging, thermal management, and precision optomechanical design.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;Deep understanding of optoelectronic package integration\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Track record of leading complex hardware from R\u0026amp;amp;D through high-volume manufacturing.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Strong program management and cross-functional leadership skills.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Excellent communication, negotiation, and organizational abilities.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h2\u0026gt;Preferred Experience\u0026lt;/h2\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Experience with silicon photonics integrated devices\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p class=\u0026quot;x_elementToProof\u0026quot;\u0026gt;Familiarity with advanced packaging optics trends and data center network architectures.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p\u0026gt;Background in contract manufacturing, vendor qualification, and global supply chain management.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4140921005,"name":"Optical","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4679751005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4428081005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Physical Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4679751005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2435","title":"Physical Design/CAD Engineer ","company_name":"Astera Labs","first_published":"2026-03-31T14:28:20-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;As an Astera Labs \u0026lt;strong\u0026gt;Physical Design/CAD Engineer\u0026lt;/strong\u0026gt; you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs\u0026#39; portfolio of connectivity ASICs used in the world\u0026#39;s leading cloud service providers, server and network OEMs. This role requires RTL to GDS ownership across design stages (Synthesis/PnR/STA/Signoff), deep technical expertise, and close collaboration with RTL and verification teams to ensure robust full-chip signoff.\u0026amp;nbsp;This role is fully on-site and in-person.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;As Physical Design CAD Engineer you will support and build flows for world class EDA tools.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive various Physical Design flow related activities, ensuring robust signoff across complex SoCs or sub-systems.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Architect and recommend flow improvements and enhance existing methodology for high performance design.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Good understanding of flow development related to backend tools like Synthesis/PnR/Extraction/DRC/LVS etc.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work with cross function teams to define requirements and specifications to achieve best PPA\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Opportunity to own a small block partition and closure (PnR, STA, DRC and LVS etc) based on interest and capacity\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Partner closely with design, implementation, and verification teams to drive block/top convergence, providing sign-off level expertise and guidance.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s in Electrical Engineering or Computer Science required; Master’s preferred.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;2-10 years of experience in PnR and sign-off for complex SoCs in Server, Storage, or Networking applications.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Expertise in PnR, Extraction, Timing closure, EM-IR, Formality and DRC/LVS at both block and full-chip level.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows in advanced nodes (7nm or below).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency with Cadence and/or Synopsys physical design/STA toolchains.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong scripting ability (Tcl, Python, Perl).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ability to work independently with strong prioritization and a professional, customer-focused mindset.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of agentic AI solutions is a plus.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience working with EDA/IP vendors for both RTL and hard-macro integration.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with high-speed SERDES and Ethernet PHY timing challenges.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of ECO methodologies, DFT tools, and test coverage analysis.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;p\u0026gt;Your base salary will be determined based on your experience and the pay of employees in similar positions. The base salary range is $135,000 USD - $165,000 USD for Senior Level, and $160,000 USD - $195,000 USD for Staff Level.\u0026lt;/p\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;/div\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4649866005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4414102005,"location":{"name":"Israel"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Physical Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4649866005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2202","title":"Physical Design Engineer","company_name":"Astera Labs","first_published":"2026-01-15T19:49:44-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is establishing a strategic R\u0026amp;amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical \u0026#39;data bottlenecks\u0026#39; enabling the future of AI at scale. As we expand our presence in Israel, we\u0026#39;re seeking a visionary\u0026lt;strong\u0026gt;\u0026amp;nbsp;Physical Design Engineer\u0026lt;/strong\u0026gt; to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world\u0026#39;s largest AI clusters.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As a\u0026amp;nbsp;\u0026lt;strong\u0026gt;Physical Design Engineer\u0026lt;/strong\u0026gt;, you will be a key architect of our silicon\u0026#39;s physical reality. You won\u0026#39;t just execute a flow—you will help establish our local execution culture and technical standards, owning the transformation of complex logic into high-performance silicon. You will drive the physical implementation journey from synthesis through signoff, ensuring our connectivity solutions meet the extreme performance, power, and area targets required for next-generation AI infrastructure. If you thrive on solving complex challenges in deep-submicron processes and want to shape the backend methodology for AI infrastructure connectivity, this is your opportunity.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Physical Implementation \u0026amp;amp; Execution\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Be part of the founding Backend team in Israel, playing a critical role in establishing local execution culture and technical standards\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Take full responsibility for physical implementation journey including Synthesis, Floorplanning, Place \u0026amp;amp; Route, and Clock-Tree Synthesis (CTS)\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Own macro-level implementation with deep hands-on experience in floorplanning and complex routing\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Signoff \u0026amp;amp; Design Integrity\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Drive final stages of design integrity, owning Timing signoff (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR)\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Ensure first-pass silicon success through rigorous signoff flows and analysis\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Apply Logic Equivalence Checking (LEC) and other verification techniques to guarantee design correctness\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Methodology Development \u0026amp;amp; Cross-Functional Collaboration\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Participate in defining and refining Backend methodologies with autonomy to improve workflows and tool automation\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Work closely with Architecture, Design, and DFT teams to navigate challenges of advanced process nodes and high-speed connectivity\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Leverage scripting and automation to make engineering environment faster and more robust\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering or related technical field\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;3+ years of hands-on experience in Physical Design at semiconductor companies\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Proven expertise in the full RTL2GDS flow with deep hands-on experience in macro-level implementation, floorplanning, and complex routing\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience working with advanced process technologies (7nm and below)\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Solid experience with signoff tools and flows including STA, Logic Equivalence Checking (LEC), DRC, and EMIR analysis\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Proficiency in TCL or Python scripting to drive EDA tool flows and automate repetitive tasks\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience with full-chip level implementation and integration\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Knowledge of Power and Noise analysis (SI/PI) to optimize high-performance silicon\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Familiarity with Design-for-Test (DFT) requirements and their impact on physical layout\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience with industry-standard EDA tools (Synopsys Fusion Compiler/ICC2, Cadence Innovus)\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Background in high-speed interface designs or connectivity protocols\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4056876005,"name":"Tel Aviv","location":"Tel Aviv, Israel","child_ids":[],"parent_id":4008937005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4691424005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_optional","internal_job_id":4433383005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose (HQ)","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Physical Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4691424005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2500","title":"Physical Design Engineer (Place \u0026 Route) ","company_name":"Astera Labs","first_published":"2026-05-06T21:11:19-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;As an Astera Labs \u0026lt;strong\u0026gt;Physical Design Engineer (Place \u0026amp;amp; Route) \u0026lt;/strong\u0026gt;to play a crucial role in the planning, coordination, and execution supporting the design of Astera Labs\u0026#39; portfolio of connectivity ASICs used in the world\u0026#39;s leading cloud service providers, server and network OEMs. This is a generalist physical design role requiring broad expertise across floorplanning, place-and-route, timing closure, and physical sign-off. You will work closely with designers, verification engineering, and engineering operations to drive blocks from RTL to GDSII. This role is fully on-site and in-person.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong academic and technical background in electrical engineering. A Bachelor\u0026#39;s degree in EE / Computer Engineering is required, and a Master\u0026#39;s degree is preferred.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;3+ years of experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Experience:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Hands-on and thorough knowledge of synthesis, place and route, timing, extraction, EM-IR, formal verification (equivalence) and other backend tools and methodologies for technologies 7nm or less.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Block level ownership from architecture to GDSII, driving multiple complex designs to production.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with Cadence and/or Synopsys physical design tools/flows.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity and working knowledge of SystemVerilog/Verilog.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven expertise in developing/maintaining timing constraints, timing signoff methodology, timing closure at the block or full-chip level.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience in working with IP vendors for both RTL and hard-macro blocks.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Good scripting skills in Tcl, Python, or Perl.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Nice to Have Experience Includes:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of design for test (DFT).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with ECO methodologies and tools.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of LVS/DRC closures.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with high-speed SERDES or Ethernet PHY design integration.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with clock tree synthesis optimization.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with PCIe, CXL, or Ethernet connectivity protocols.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;p\u0026gt;Your base salary will be determined based on your experience and the pay of employees in similar positions. The base salary range is 135,000 USD - $165,000 USD for Senior Level, and 160,000 USD - 195,000 USD for Staff Level. You will also be eligible for equity and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;/div\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4693111005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_optional","internal_job_id":4434393005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose (HQ)","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Physical Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4693111005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2515","title":"Physical Design Engineer (Place \u0026 Route) ","company_name":"Astera Labs","first_published":"2026-05-06T21:15:08-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;As an Astera Labs \u0026lt;strong\u0026gt;Physical Design Engineer (Place \u0026amp;amp; Route) \u0026lt;/strong\u0026gt;to play a crucial role in the planning, coordination, and execution supporting the design of Astera Labs\u0026#39; portfolio of connectivity ASICs used in the world\u0026#39;s leading cloud service providers, server and network OEMs. This is a generalist physical design role requiring broad expertise across floorplanning, place-and-route, timing closure, and physical sign-off. You will work closely with designers, verification engineering, and engineering operations to drive blocks from RTL to GDSII. This role is fully on-site and in-person.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong academic and technical background in electrical engineering. A Bachelor\u0026#39;s degree in EE / Computer Engineering is required, and a Master\u0026#39;s degree is preferred.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;8+ years of experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Experience:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Hands-on and thorough knowledge of synthesis, place and route, timing, extraction, EM-IR, formal verification (equivalence) and other backend tools and methodologies for technologies 7nm or less.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Block level ownership from architecture to GDSII, driving multiple complex designs to production.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with Cadence and/or Synopsys physical design tools/flows.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity and working knowledge of SystemVerilog/Verilog.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven expertise in developing/maintaining timing constraints, timing signoff methodology, timing closure at the block or full-chip level.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience in working with IP vendors for both RTL and hard-macro blocks.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Good scripting skills in Tcl, Python, or Perl.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Nice to Have Experience Includes:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of design for test (DFT).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with ECO methodologies and tools.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of LVS/DRC closures.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with high-speed SERDES or Ethernet PHY design integration.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with clock tree synthesis optimization.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with PCIe, CXL, or Ethernet connectivity protocols.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;p\u0026gt;Your base salary will be determined based on your experience and the pay of employees in similar positions. The base salary range is 160,000 USD - 195,000 USD for Staff Level, and 203,000 USD - 230,000 USD for Principal Level. You will also be eligible for equity and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;/div\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4701792005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4438671005,"location":{"name":"Tel Aviv-Yafo, Tel Aviv District, Israel"},"metadata":[{"id":12122734005,"name":"Country","value":"Israel","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Tel-Aviv","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Physical Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Internship","value_type":"single_select"}],"id":4701792005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2607","title":"Physical Design Student","company_name":"Astera Labs","first_published":"2026-06-02T13:34:52-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is establishing a strategic R\u0026amp;amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical \u0026#39;data bottlenecks\u0026#39; enabling the future of AI at scale. As we expand our presence in Israel, we are seeking a motivated\u0026amp;nbsp;\u0026lt;strong data-path-to-node=\u0026quot;8\u0026quot; data-index-in-node=\u0026quot;260\u0026quot;\u0026gt;Physical Design Student\u0026lt;/strong\u0026gt;\u0026amp;nbsp;to join our founding local engineering team.\u0026lt;/p\u0026gt;\n\u0026lt;p data-path-to-node=\u0026quot;9\u0026quot;\u0026gt;This is a unique opportunity to kickstart your career in the semiconductor industry. Working alongside senior industry veterans, you will gain hands-on experience in backend execution and advanced methodologies for cutting-edge chips that power the world\u0026#39;s largest AI clusters. If you are passionate about silicon hardware, eager to learn, and thrive on solving complex engineering challenges, this role offers the perfect bridge between your academic studies and a high-impact career.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p data-path-to-node=\u0026quot;10\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;h4 data-path-to-node=\u0026quot;11\u0026quot;\u0026gt;Guided Implementation \u0026amp;amp; Learning\u0026lt;/h4\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;12,0,0\u0026quot;\u0026gt;Partner with and learn from senior engineers to support the physical implementation journey, including synthesis, floorplanning, Place \u0026amp;amp; Route (P\u0026amp;amp;R), and Clock-Tree Synthesis (CTS)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;12,1,0\u0026quot;\u0026gt;Assist in macro-level implementation and develop hands-on skills in complex layout routing\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;12,2,0\u0026quot;\u0026gt;Participate in deep-submicron process challenges under close professional mentorship\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Signoff \u0026amp;amp; Design Integrity Support\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;14,0,0\u0026quot;\u0026gt;Assist in running engineering checks for design integrity, including Static Timing Analysis (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;14,1,0\u0026quot;\u0026gt;Learn to apply Logic Equivalence Checking (LEC) to help guarantee design correctness\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;14,2,0\u0026quot;\u0026gt;Gain exposure to the rigorous flows required to ensure first-pass silicon success\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Scripting \u0026amp;amp; Cross-Functional Collaboration\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;16,0,0\u0026quot;\u0026gt;Leverage and develop scripting tools to automate repetitive tasks and optimize the engineering environment\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;16,1,0\u0026quot;\u0026gt;Collaborate with Architecture, Design, and DFT teams to understand how different chip design disciplines intersect\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;16,2,0\u0026quot;\u0026gt;Actively participate in team reviews and technical discussions to ramp up backend methodologies\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p data-path-to-node=\u0026quot;18,0,0\u0026quot;\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Pursuing a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;18,1,0\u0026quot;\u0026gt;Strong academic foundation in digital systems, VLSI design, or semiconductor devices.\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;18,1,0\u0026quot;\u0026gt;Familiarity with Python, TCL, Bash, or Perl.\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;18,1,0\u0026quot;\u0026gt;Ability to work at least 2 days per week at our Haifa/Tel Aviv Center\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;18,1,0\u0026quot;\u0026gt;A \u0026quot;can-do\u0026quot; attitude with a passion for solving complex technical challenges\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;18,1,0\u0026quot;\u0026gt;Fluent in Hebrew and English with the ability to work effectively in a team environment\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026amp;nbsp;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p data-path-to-node=\u0026quot;18,2,0\u0026quot;\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Prior experience from a previous VLSI/Hardware student position or a significant academic project in physical design/VLSI\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;20,1,0\u0026quot;\u0026gt;Hands-on university lab experience with industry-standard EDA tools (e.g., Synopsys Fusion Compiler/ICC2, Cadence Innovus)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;20,2,0\u0026quot;\u0026gt;Understanding of basic verification concepts (STA, DRC, LVS)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;20,3,0\u0026quot;\u0026gt;Fast learner with a proactive attitude and a passion for deep-tech hardware infrastructure\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4052111005,"name":"Haifa","location":"Haifa, Israel","child_ids":[],"parent_id":4008937005},{"id":4056876005,"name":"Tel Aviv","location":"Tel Aviv, Israel","child_ids":[],"parent_id":4008937005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4683285005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4429664005,"location":{"name":"Suzhou Qu, Gansu, China"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Hardware Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4683285005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2457","title":"Principal AEC / AOC Program Manager","company_name":"Astera Labs","first_published":"2026-04-09T01:37:18-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Job Description:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As an Astera Labs Principal AEC / AOC Program Manager you will play a crucial role in overseeing the planning, coordination, and execution of manufacturing projects featuring Astera Labs\u0026#39; AEC / AOC portfolio of connectivity ASICs used in the world\u0026#39;s leading cloud service providers, server and network OEMs. You will ensure that production processes run smoothly, meet quality standards, and are completed on time and within budget and responsible for manufacturing from NPI to mass production phases. To accomplish that, you will be working closely with designers, the manufacturing team, suppliers, and contract manufacturers. \u0026lt;strong\u0026gt;This role is expected to travel up to 30% of the year and will require business English skills. \u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Job Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Project Planning and Execution\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Develop Project Plans:\u0026lt;/strong\u0026gt; Create detailed project plans, including schedules, budgets, resource allocation, and timelines.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Coordinate Production Activities:\u0026lt;/strong\u0026gt; Oversee all aspects of the manufacturing process, ensuring alignment with project goals.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Monitor Progress:\u0026lt;/strong\u0026gt; Track project milestones, deliverables, and deadlines to ensure timely completion.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Problem Solving:\u0026lt;/strong\u0026gt; Address and resolve issues that arise during the manufacturing process to avoid delays.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Change Management\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;ECO: \u0026lt;/strong\u0026gt;Drive Engineering Change Order and Deviation processes in product design, manufacturing, and disposition\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;PLM: \u0026lt;/strong\u0026gt;Use Product Lifecycle Management systems such as Agile, Arena\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ability to evaluate change including trade-offs\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional Team Leadership\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Lead Cross-Functional Teams:\u0026lt;/strong\u0026gt; Manage and lead cross-functional teams, including engineering, production, quality, supply chain, and logistics.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Facilitate Communication:\u0026lt;/strong\u0026gt; Ensure effective communication between different departments and stakeholders involved in the manufacturing process.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Assign Tasks:\u0026lt;/strong\u0026gt; Delegate tasks and responsibilities to team members and monitor their performance.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Budget and Cost Management\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Manage Budgets:\u0026lt;/strong\u0026gt; Develop and manage project budgets, ensuring costs are controlled and within budget.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Cost Analysis:\u0026lt;/strong\u0026gt; Conduct cost-benefit analyses and identify opportunities for cost savings and efficiency improvements.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Financial Reporting:\u0026lt;/strong\u0026gt; Provide regular financial updates to senior management, highlighting any variances from the budget.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Quality Assurance\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Ensure Quality Standards:\u0026lt;/strong\u0026gt; Ensure that manufacturing processes meet the required quality standards and regulatory requirements.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Implement Quality Controls:\u0026lt;/strong\u0026gt; Develop and implement quality control procedures and processes to minimize defects and rework.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Continuous Improvement:\u0026lt;/strong\u0026gt; Identify areas for improvement and implement lean manufacturing practices to enhance efficiency and quality.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Supply Chain Management\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Work closely with Business Operations / Supply Chain team to ensure timely delivery of materials and components.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Risk Management\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Identify Risks:\u0026lt;/strong\u0026gt; Identify potential risks in the manufacturing process, including supply chain disruptions, equipment failures, or quality issues.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Develop Mitigation Plans:\u0026lt;/strong\u0026gt; Create and implement risk mitigation plans to minimize the impact of identified risks.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Monitor and Report:\u0026lt;/strong\u0026gt; Continuously monitor risks and provide regular updates to stakeholders.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Stakeholder Management\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Engage Stakeholders:\u0026lt;/strong\u0026gt; Maintain strong relationships with key stakeholders, including customers, suppliers, and internal teams.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Stakeholder Reporting:\u0026lt;/strong\u0026gt; Prepare and present reports on project progress, challenges, and successes to senior management and other stakeholders.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Regulatory Compliance\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Ensure Compliance:\u0026lt;/strong\u0026gt; Ensure that all manufacturing processes comply with relevant industry regulations, safety standards, and environmental laws.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Documentation:\u0026lt;/strong\u0026gt; Maintain accurate documentation of manufacturing processes, quality controls, and compliance activities.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Technology and Innovation\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Adopt New Technologies:\u0026lt;/strong\u0026gt; Identify and implement new technologies and processes that can improve manufacturing efficiency, quality, and cost-effectiveness.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Process Optimization:\u0026lt;/strong\u0026gt; Continuously seek ways to optimize manufacturing processes through automation, innovation, and best practices.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Reporting and Documentation\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Project Reports:\u0026lt;/strong\u0026gt; Prepare detailed project reports, including progress updates, financial status, and quality metrics.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Documentation:\u0026lt;/strong\u0026gt; Ensure all project documentation is accurate, up-to-date, and easily accessible for future reference.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Educational Background\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Bachelor’s Degree (Required):\u0026lt;/strong\u0026gt; A bachelor’s degree in electrical engineering, manufacturing, industrial engineering, mechanical engineering, or a related field.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Advanced Degree (Preferred):\u0026lt;/strong\u0026gt; A Master’s degree in business administration (MBA), engineering management, or a related field can be an advantage, especially for leadership roles.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Professional Experience\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Relevant Experience:\u0026lt;/strong\u0026gt; A minimum of 8 years of experience in manufacturing, engineering, or production environments, with several years in a project management or program management role.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Leadership Experience:\u0026lt;/strong\u0026gt; Proven experience leading cross-functional teams and managing complex projects from concept through production.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Industry-Specific Experience:\u0026lt;/strong\u0026gt; Experience in electronics industry. Experience with high speed / high complexity projects preferred.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Technical Skills\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Manufacturing Processes:\u0026lt;/strong\u0026gt; In-depth knowledge of manufacturing processes, production techniques, and industry best practices.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Project Management:\u0026lt;/strong\u0026gt; Strong project management skills, including planning, scheduling, budgeting, and resource management.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Lean Manufacturing:\u0026lt;/strong\u0026gt; Familiarity with lean manufacturing principles, Six Sigma, and other process improvement methodologies.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Quality Assurance:\u0026lt;/strong\u0026gt; Knowledge of quality management systems (e.g., ISO standards) and quality control processes.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Supply Chain Management:\u0026lt;/strong\u0026gt; Understanding of supply chain management, procurement, and logistics in a manufacturing environment.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/ul\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025526005,"name":"Hardware Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4009038005,"name":"Suzhou","location":"Suzhou, China","child_ids":[],"parent_id":4002875005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4697312005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4436741005,"location":{"name":"United States, Remote"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose (HQ)","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"CTO Organization","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4697312005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2562","title":"Principal AI Infrastructure \u0026 Hardware Program Management","company_name":"Astera Labs","first_published":"2026-05-19T19:37:15-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;h2\u0026gt;About the Role\u0026lt;/h2\u0026gt;\n\u0026lt;p\u0026gt;We are seeking a highly experienced and results-driven leader to drive our global AI, Storage, and Networking hardware design programs. This role will be responsible for end-to-end program leadership across complex, multi-disciplinary initiatives, ensuring successful delivery of cutting-edge products in a fast-paced, innovation-driven environment.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;You will work closely with executive leadership, Tier-1 customers, and cross-functional global teams to deliver next-generation infrastructure solutions, including advanced AI platforms.\u0026lt;/p\u0026gt;\n\u0026lt;h2\u0026gt;Key Responsibilities\u0026lt;/h2\u0026gt;\n\u0026lt;h3\u0026gt;Program Leadership \u0026amp;amp; Execution\u0026lt;/h3\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Lead and manage global AI, Storage, and Networking hardware design programs, ensuring on-time delivery, scope control, and budget adherence\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive program governance, risk management, and execution excellence across all phases of product development\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Provide regular program updates, risk assessments, and financial reporting to executive leadership through structured reviews (e.g., Leadership Program Reviews)\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h3\u0026gt;Product Innovation \u0026amp;amp; Delivery\u0026lt;/h3\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Oversee the successful launch of complex hardware platforms, including AI GPU-based systems\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Manage high-priority, resource-constrained programs while maintaining quality and schedule commitments\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Enable innovation in next-generation AI infrastructure and high-performance computing platforms\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h3\u0026gt;UALink Switch Tray Development (Rack-Scale AI Systems)\u0026lt;/h3\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Lead end-to-end program management for \u0026lt;strong\u0026gt;UALink / PCIe Gen6 switch tray development\u0026lt;/strong\u0026gt; supporting rack-scale AI platforms and GPU clusters\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Coordinate design, validation, and manufacturing readiness of switch trays across EVT, DVT, and PVT phases\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive integration of \u0026lt;strong\u0026gt;switch silicon, retimer cards, cabling, and system-level connectivity\u0026lt;/strong\u0026gt; within full rack-scale architectures\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with ODMs and partners to align on design specifications, cost models, and development schedules\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Manage technical trade-offs across \u0026lt;strong\u0026gt;performance, signal integrity, power delivery, thermals, and scalability\u0026lt;/strong\u0026gt; for high-density GPU deployments\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h3\u0026gt;Customer \u0026amp;amp; Partnership Management\u0026lt;/h3\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Partner with Tier-1 customers to deliver Joint Design Manufacturing (JDM) programs\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ensure alignment with customer-specific requirements in design, supply chain, and quality\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Build strong customer relationships and act as a trusted advisor throughout the product lifecycle\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h3\u0026gt;Global Cross-Functional Leadership\u0026lt;/h3\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Lead globally distributed teams across engineering (HW/SW), supply chain, manufacturing, and quality organizations\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Coordinate teams across multiple regions (e.g., North America and Asia) to drive seamless execution\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Guide programs through EVT, DVT, and PPVT phases, ensuring technical validation across electrical, thermal, power, signal integrity, and mechanical domains\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h2\u0026gt;Qualifications\u0026lt;/h2\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;12+ years of experience in hardware program management, preferably in AI, servers, storage, or networking\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven track record of delivering complex global hardware programs from concept to production\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience leading cross-functional teams across multiple geographies\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong background in product development lifecycle (EVT, DVT, PPVT)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience working with Tier-1 customers and JDM models\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Demonstrated ability to manage program financials, timelines, and risks at scale\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent communication skills with experience presenting to senior executives\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h2\u0026gt;Preferred Qualifications\u0026lt;/h2\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience with AI GPU platforms or high-performance computing infrastructure\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with AMD, NVIDIA, or similar AI hardware ecosystems\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with \u0026lt;strong\u0026gt;PCIe Gen6, CXL, or UALink-based connectivity architectures\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Exposure to industry forums such as OCP (Open Compute Project)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;MBA or advanced technical degree\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4141010005,"name":"Platform Architecture","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4055745005,"name":"Remote - United States","location":"Remote-United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4610204005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4395425005,"location":{"name":"Toronto , Canada"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"IC Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4610204005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2016","title":"Principal Analog Mixed-Signal Design Engineer","company_name":"Astera Labs","first_published":"2026-01-20T12:59:34-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Job Description: \u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As an Analog/Mixed-Signal IC Design Engineer, you will be part of a key team designing sophisticated advanced node CMOS products. Your responsibilities will include developing and verifying circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs to meet performance targets. You will also work on analog and clocking blocks for connectivity applications, using industry-standard tools like Spectre and MATLAB. The company seeks a highly motivated designer for this role\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong academic and technical background in electrical engineering. A Master’s or PhD degree in EE is required, preferably from a top-tier university.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;8+ years of experience supporting or developing complex analog IC designs.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Experience:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience in designing high-speed mixed-signal circuits including ADC/DAC data converters, RX front-end, TX driver/serializer, low-jitter PLLs, TX/RX calibration, low-jitter CLK distribution are other high-speed analog circuits is a must\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Have a deep understanding of biasing, band-gaps, reference circuits, opamps, comparators and other analog circuits\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Solid track-record for implementation of analog circuits high-speed data transmission.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Design and tape out experience in advanced CMOS nodes (ex. 7nm, 5nm 3nmFinFET) is a must.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Solid fundamentals in detailed transistor-level design, feedback/stability analysis, and noise/jitter analysis.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of TIA design and drivers for optical applications is highly desirable\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience in RFIC design for wireless or wireline communication systems is highly desirable.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong technical independent contributor with a proven ability to drive results.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent teamwork, presentation, and documentation skills.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ability to collaborate with global teams across multiple time zones and deliver under pressure with strict deadlines.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong experience in lab chip bring-up and debugging efforts.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Experience:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Relevant research publications and/or patents in analog or RF IC design.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity in programming/scripting languages such as Python, Matlab, or C.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with PCB design.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with Verilog RTL or DSP design concepts.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of optical transceivers.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Expertise in ESD protection techniques and IC packaging methodologies.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4135671005,"name":"SerDes","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000119005,"name":"Toronto","location":"Toronto, Canada","child_ids":[],"parent_id":4004709005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4676963005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4426612005,"location":{"name":"San Jose, United States"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Design Verification","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4676963005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2398","title":"Principal Design Verification Engineer ","company_name":"Astera Labs","first_published":"2026-03-26T19:08:39-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;Astera Labs is seeking a \u0026lt;strong\u0026gt;Principal Design Verification Engineer\u0026lt;/strong\u0026gt; with strong problem-solving abilities and a passion for developing robust verification methodologies for complex ASICs. The ideal candidate will have a solid background in SystemVerilog and experience with C/C++, Python, or similar scripting languages. This role involves full lifecycle verification—from planning and test development to debugging and coverage closure—contributing to the success of cutting-edge SoC designs.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Lead the functional verification of advanced ASICs, including test planning, development, execution, and coverage analysis.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate closely with software and system validation teams to create and execute test plans on emulation platforms.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Apply both directed and constrained-random verification techniques using SystemVerilog/UVM and other relevant tools.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Debug test failures, analyze coverage results, and close functional coverage gaps to ensure comprehensive verification.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work with RTL designers to troubleshoot and resolve design issues.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive verification strategy and methodology for SoCs in server and networking applications.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s degree in Electrical Engineering (Master’s preferred).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;8+ years of experience in SoC verification, particularly for server and networking applications.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Expertise in SystemVerilog/UVM and hands-on experience across the full verification lifecycle.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency with industry-standard simulators, version control, and regression systems.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong debugging and coverage analysis skills.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience developing and executing test sequences, generating stimuli, and identifying verification holes.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with verification of switching architectures, including packet processing and forwarding engines.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent communication skills and ability to work independently with minimal supervision.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience with third-party Verification IP for protocols such as PCIe, Ethernet, and InfiniBand.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Background in Network-on-Chip (NoC) architectures for smart NICs and AI accelerators.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of Ethernet/PCIe switching and central buffer architectures.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with emulation platforms and hardware-software co-verification\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Salary range is $185,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4601154005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4390719005,"location":{"name":"San Jose, CA"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Hardware Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4601154005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"1913","title":"Principal Diagnostic Platform Software Engineer","company_name":"Astera Labs","first_published":"2025-08-26T17:07:45-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Job Description:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As member of Astera Labs Hardware Engineering team you will be responsible for building diagnostics and manufacturing software to allow design, test, and manufacture cutting edge high speed datacenter products.\u0026amp;nbsp; You will be working on projects from conception to the final production stage at contract manufacturer.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;The role requires a strong and broad software background and good understanding of hardware design and manufacturing practices.\u0026amp;nbsp; At the same time we welcome candidates with deep experience in smaller areas with the desire to learn.\u0026amp;nbsp; Depending on your experience, you may be focusing on design/validation or automation/manufacturing.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Design, implement \u0026amp;amp; test production-grade diagnostics for high-speed digital boards and ASICS to help with hardware validation.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Design, implement \u0026amp;amp; test manufacturing tests to validate mass production of digital boards used in data center networking product\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Bring-up newly manufactured boards and develop the first level of software.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Isolate and perform root-cause analysis of reported failures\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support new platform software and hardware features\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Coordinate with the hardware engineering team on bring-up schedules and feature delivery\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Participate proactively in design discussions, design review, and project management\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work independently as well as in team roles, mentor younger team members\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications/Required Experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s in CS/CE or equivalent experience.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;8+ years of Experience in subset of diagnostic, hardware bring-up, test or manufacturing automation\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of modern software development\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency in Python, C/C++\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience working with datacenter-level complex electronic equipment bring-up/diagnostic/manufacturing\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ability to read schematic/layout\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;System debug experience\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Embedded programming and good knowledge of OS internals (Linux/Unix)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Has knowledge of common interconnecting buses and interfaces such as PCIe, I2C, XAUI, 10G Ethernet drivers, FPGA, Switch chips, SSL offload, TCAM programming.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with DDR5\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;The base salary range is $203,000 - $230,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025526005,"name":"Hardware Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4697340005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4436752005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose (HQ)","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Digital Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4697340005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2565","title":"Principal Digital Design Engineer","company_name":"Astera Labs","first_published":"2026-05-19T20:22:04-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Job Description\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;We are looking for \u0026lt;strong\u0026gt;Principal Digital Design Engineers \u0026lt;/strong\u0026gt;with experience developing micro-architecture and implementation of the front-end circuit design, including RTL, synthesis, IP integration, and block-level verification for high performance network controllers. The candidate must have good knowledge of communication/interface protocols such as PCI-Express (Gen-3 and above), Ethernet, Infiniband, DDR, NVMe, USB, etc.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE is required, and a Master’s degree is preferred.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;+8 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Authorized to work in the US and start immediately.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Experience:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Hands-on, thorough knowledge of high-speed protocols like PCIe, Ethernet, Infiniband, DDR, NVMe, USB, etc.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven front end design expertise – architecture, RTL, simulations, synthesis, timing closure, GLS, DFT etc.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Full chip or block level ownership from architecture to GDS, driving multiple complex designs to production\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with Synopsys and/or Cadence digital design tools/flows\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Good knowledge of design for test (DFT), stuck-at and transition scan test insertion\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with UVM based design verification\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Silicon bring-up and debug expertise\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Small-geometry CMOS (≤28nm) design\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Experience:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Firmware development with C-language, scripting with Python or other equivalent programming languages.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Development/support for PCIe or Ethernet Switch products.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;p\u0026gt;The base salary range is $185,000.00 USD – $230,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;/div\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4699436005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4437667005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose (HQ)","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Digital Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4699436005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2587","title":"Principal Digital Design Engineer","company_name":"Astera Labs","first_published":"2026-05-26T15:16:49-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;Job Description: As a Digital Designer in the DSP SerDes team, you will join a pivotal project to develop \u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;advanced high speed SerDes\u0026lt;/span\u0026gt; wireline and optical transceivers for AI systems.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Basic Qualifications:\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Hold a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;5-10 years of experience in digital design for high-speed DSP data path.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Be proficient in coding System Verilog for complex design blocks.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Have experience with EDA tools for Synthesis, Lint, CDC, and Prime Time.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Have experience taking design blocks through the full design cycle, from micro-architecture to tapeout.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Have experience with timing fixes, area and power optimizations, and resolving silicon issues.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Required Experience:\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Serve as the responsible engineer for at least one critical design block, including architecture definition, design specifications, and RTL delivery.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Code and deliver high-quality RTL to the PD and DV teams.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with the DSP Architecture team to define new features and suggest optimizations for power, latency, and performance.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work with the PD team to resolve timing violations, Spyglass warnings/errors, and CDC violations.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Partner with the DV team to root-cause and fix design bugs.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Preferred Experience:\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience in digital design for high speed data path in 100G+ PAM4 DSP SerDes\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience in designing PAM4 DSP blocks for FFE, DFE, MLSD, and digital timing recovery.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4135671005,"name":"SerDes","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4672627005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4424481005,"location":{"name":"San Jose, CA"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Digital Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4672627005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2362","title":"Principal Digital Design Engineer ","company_name":"Astera Labs","first_published":"2026-03-12T15:00:01-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Join Astera Labs as a \u0026lt;strong\u0026gt;Principal Digital Design Engineer\u0026lt;/strong\u0026gt; to architect and implement next-generation digital designs for high-performance AI connectivity solutions. You\u0026#39;ll own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, physical design, and DFT teams to deliver production-quality silicon supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This role offers the opportunity to work on cutting-edge technology at the forefront of AI infrastructure, taking ownership of critical design challenges in a fast-paced, collaborative environment where your contributions directly impact products deployed by the world\u0026#39;s leading hyperscalers.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Design Ownership \u0026amp;amp; Execution\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Develop and implement complex digital blocks and subsystems by defining micro-architecture and driving RTL implementation with an exceptional power, performance and area trade-off using silicon technologies better than 7nm.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead efforts to achieve timing closure and implement Design-for-Test (DFT) features for optimal design performance\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive designs to production, ensuring accountability for quality, schedule, and overall design success\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Verification \u0026amp;amp; Integration\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with verification teams to develop test plans, achieve coverage closure, and debug complex issues\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Own third-party IP integration and block-level verification through sign-off\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work closely with post-silicon teams to facilitate silicon bring-up and debug\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Technical Leadership\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Mentor junior engineers to develop their technical skills and expertise\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Actively contribute to the development and improvement of silicon development processes\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive design methodology improvements and CAD automation initiatives\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering or equivalent\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;10+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Expertise in architecture definition, micro-architecture development, RTL coding, functional simulation, and synthesis\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of timing closure, gate-level simulation (GLS), and DFT implementation\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep expertise in at least one high-speed protocol: PCIe, CXL, Ethernet, DDR, or similar\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Production experience with advanced CMOS nodes (≤7nm)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency with Cadence and/or Synopsys digital design flows\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Master\u0026#39;s degree in Electrical Engineering or related field\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Track record of delivering multiple high-performance designs to production in data-center environments\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on collaboration with embedded firmware teams; understanding of firmware development challenges\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with standard embedded processor subsystems (RISC-V, Arm, etc.)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven contributions to design methodology, CAD automation, or design infrastructure\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Salary range is $185,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4645005005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4411914005,"location":{"name":"San Jose, CA"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Digital Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4645005005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2181","title":"Principal Digital Design Engineer (AI Fabric)","company_name":"Astera Labs","first_published":"2025-12-30T17:30:53-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Join our team as \u0026lt;strong\u0026gt;Principal Digital Design Engineer\u0026amp;nbsp;\u0026lt;/strong\u0026gt;to architect and implement next-generation digital designs for high-performance connectivity solutions. You\u0026#39;ll own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, PD and DFT teams to deliver high performance products in a fast-paced, collaborative environment.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Develop and implement complex digital blocks and subsystems by defining micro-architecture and driving digital design.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with verification teams to develop test plans, achieve coverage closure, and debug complex issues.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead efforts to achieve timing closure and implement Design-for-Test (DFT) features for optimal design performance.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work closely with post-silicon teams to facilitate silicon bring-up and debug.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Mentor junior engineers to develop their technical skills and expertise.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Actively contribute to the development and improvement of silicon development processes.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive designs to production, ensuring accountability for quality, schedule, and overall design success.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Qualifications:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Education \u0026amp;amp; Experience:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s degree in electrical engineering or equivalent.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;8+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Digital Design Expertise:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Architecture definition and micro-architecture development\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;RTL coding, functional simulation, and synthesis\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Timing closure and gate-level simulation (GLS)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Design for test (DFT) implementation\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Production experience with advanced CMOS nodes (≤7nm)\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Protocols \u0026amp;amp; Integration:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Deep expertise in at least one high-speed protocol—PCIe , Ethernet, Infiniband, DDR, or similar\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Third-party IP integration and verification.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Block-level design ownership from architecture through GDS\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Tools \u0026amp;amp; Methodologies:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Proficiency with Cadence and/or Synopsys digital design flows\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with UVM-based verification methodologies.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Silicon bring-up, debug, and failure analysis expertise\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Professional Attributes:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong work ethic with the ability to balance multiple priorities in a dynamic environment\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent communication and collaboration skills; comfortable working cross-functionally with global teams\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Self-directed learner who thrives with minimal supervision and adapts quickly to changing requirements\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Customer-focused mindset with ability to translate business needs into technical excellence\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Track record of delivering multiple high-performance designs to production in data-center environments\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on collaboration with embedded firmware teams; deep understanding of firmware development challenges and constraints\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with standard embedded processor subsystems (RISC-V, Arm, etc.)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven contributions to design methodology, CAD automation, or design infrastructure to improve productivity or design quality\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;p\u0026gt;The base salary range is $185,000.00 USD – $230,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4698851005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4437331005,"location":{"name":"Shanghai Shi, China"},"metadata":[{"id":12122734005,"name":"Country","value":"China","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Shanghai","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Hardware Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4698851005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2572","title":"Principal Electrical Engineer – Smart Cable Modules ","company_name":"Astera Labs","first_published":"2026-05-22T12:15:23-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;We are looking for a Principal Electrical Engineer to take strategic ownership of our Smart Cable Module (SCM) hardware platform. This is a senior individual-contributor role that combines deep technical leadership with cross-organizational influence\u0026amp;nbsp;-\u0026amp;nbsp;you will define the electrical architecture of our next-generation active copper cable assemblies and pluggable modules in OSFP, QSFP-DD, and emerging form-factor enclosures targeting 400G, 800G, and beyond.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:60,\u0026amp;quot;335559739\u0026amp;quot;:60}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;As a Principal Engineer you will set design direction, establish engineering standards, and serve as the primary technical authority on module hardware across the full product lifecycle\u0026amp;nbsp;-\u0026amp;nbsp;from concept and architecture through production release and sustaining engineering. You will partner with\u0026amp;nbsp;cross functional team, contract manufacturers, firmware teams, and hyperscale customers to deliver differentiated, high-reliability products for data center AI/ML fabric and high-performance computing applications.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:60,\u0026amp;quot;335559739\u0026amp;quot;:60}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:80}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:340,\u0026amp;quot;335559739\u0026amp;quot;:100,\u0026amp;quot;335572079\u0026amp;quot;:8,\u0026amp;quot;335572080\u0026amp;quot;:4,\u0026amp;quot;335572081\u0026amp;quot;:11824430,\u0026amp;quot;469789806\u0026amp;quot;:\u0026amp;quot;single\u0026amp;quot;}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Architecture \u0026amp;amp; Technical Leadership\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:60,\u0026amp;quot;335559739\u0026amp;quot;:60}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:640,\u0026amp;quot;335559991\u0026amp;quot;:320,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Define and own the end-to-end electrical architecture for smart cable modules, including SerDes channel topology, power delivery strategy, and thermal budgeting\u0026amp;nbsp;for muti-Gig (112G PAM4 and 56G NRZ\u0026amp;nbsp;)\u0026amp;nbsp;designs\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:44,\u0026amp;quot;335559739\u0026amp;quot;:44}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:640,\u0026amp;quot;335559991\u0026amp;quot;:320,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Establish and maintain internal electrical design standards, PCB layout rules, and SI/PI guidelines that the broader hardware team\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:44,\u0026amp;quot;335559739\u0026amp;quot;:44}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:640,\u0026amp;quot;335559991\u0026amp;quot;:320,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Lead technical reviews (architecture, schematic, layout, DVT) and provide authoritative sign-off on high-speed digital designs\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:44,\u0026amp;quot;335559739\u0026amp;quot;:44}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:640,\u0026amp;quot;335559991\u0026amp;quot;:320,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Contribute to\u0026amp;nbsp;the module hardware roadmap in alignment with host ASIC platform generations, MSA form-factor evolution, and customer requirements\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:44,\u0026amp;quot;335559739\u0026amp;quot;:44}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:640,\u0026amp;quot;335559991\u0026amp;quot;:320,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Evaluate and select\u0026amp;nbsp;components; engage directly with supplier engineering teams on reference design adaptation and silicon bring-up support\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:44,\u0026amp;quot;335559739\u0026amp;quot;:44}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:60}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Electrical Design Ownership\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:60,\u0026amp;quot;335559739\u0026amp;quot;:60}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:640,\u0026amp;quot;335559991\u0026amp;quot;:320,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Drive schematic capture and PCB design for complex multi-layer modules housing\u0026amp;nbsp;muti-Gig\u0026amp;nbsp;SerDes retimer or DSP ASICs in thermally and spatially constrained OSFP/QSFP-DD enclosures\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:44,\u0026amp;quot;335559739\u0026amp;quot;:44}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:640,\u0026amp;quot;335559991\u0026amp;quot;:320,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;7\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Own power delivery design including multi-rail regulation, hot-plug sequencing, brownout protection, and inrush management within MSA-defined power envelopes.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:44,\u0026amp;quot;335559739\u0026amp;quot;:44}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:640,\u0026amp;quot;335559991\u0026amp;quot;:320,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;8\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Review and\u0026amp;nbsp;recommendation\u0026amp;nbsp;on\u0026amp;nbsp;PCB stack-up, impedance targets, via structures, and differential-pair routing rules; review and approve layout execution with sufficient SI understanding to ensure first-pass compliance\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:44,\u0026amp;quot;335559739\u0026amp;quot;:44}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:640,\u0026amp;quot;335559991\u0026amp;quot;:320,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;9\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Define module management hardware architecture: I2C\u0026amp;nbsp;topology, register map implementation, microcontroller selection, and diagnostic monitoring interface circuitry\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:44,\u0026amp;quot;335559739\u0026amp;quot;:44}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:640,\u0026amp;quot;335559991\u0026amp;quot;:320,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;10\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Perform analog and mixed-signal sub-circuit design including clock distribution, oscillator selection, ESD protection, and supervisory logic\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:44,\u0026amp;quot;335559739\u0026amp;quot;:44}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:60}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Validation \u0026amp;amp; Bring-Up Leadership\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:60,\u0026amp;quot;335559739\u0026amp;quot;:60}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:640,\u0026amp;quot;335559991\u0026amp;quot;:320,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;11\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Author/co-author\u0026amp;nbsp;hardware bring-up strategies, debug plans, and acceptance test procedures for new module designs; lead or directly execute board bring-up.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:44,\u0026amp;quot;335559739\u0026amp;quot;:44}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:640,\u0026amp;quot;335559991\u0026amp;quot;:320,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;12\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Oversee firmware integration testing,\u0026amp;nbsp;control-interface validation, and module diagnostic monitoring verification\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:44,\u0026amp;quot;335559739\u0026amp;quot;:44}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:640,\u0026amp;quot;335559991\u0026amp;quot;:320,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;13\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Lead root-cause analysis on complex hardware failures;\u0026amp;nbsp;review\u0026amp;nbsp;failure analysis reports and\u0026amp;nbsp;implement changes.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:44,\u0026amp;quot;335559739\u0026amp;quot;:44}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:640,\u0026amp;quot;335559991\u0026amp;quot;:320,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;14\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Define and champion DFT/DFM strategies with CM and PCB fabrication partners to improve yield and reduce manufacturing cost\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:44,\u0026amp;quot;335559739\u0026amp;quot;:44}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:60}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Cross-Functional \u0026amp;amp; Organizational Impact\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:60,\u0026amp;quot;335559739\u0026amp;quot;:60}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:640,\u0026amp;quot;335559991\u0026amp;quot;:320,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;15\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Collaborate with firmware and software teams to define initialization sequences, power management schemes, and real-time diagnostic algorithms\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:44,\u0026amp;quot;335559739\u0026amp;quot;:44}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:640,\u0026amp;quot;335559991\u0026amp;quot;:320,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;16\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Represent the organization in relevant MSA, and IEEE standards working groups; influence specification development in support of company product strategy\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:44,\u0026amp;quot;335559739\u0026amp;quot;:44}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:640,\u0026amp;quot;335559991\u0026amp;quot;:320,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;17\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Mentor and technically develop senior and mid-level engineers; elevate the hardware team\u0026#39;s collective capabilities in high-speed design\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:44,\u0026amp;quot;335559739\u0026amp;quot;:44}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:640,\u0026amp;quot;335559991\u0026amp;quot;:320,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;18\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Contribute to strategic hiring, technical onboarding, and department-level engineering process improvement\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:44,\u0026amp;quot;335559739\u0026amp;quot;:44}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:80}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Required Qualifications\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:340,\u0026amp;quot;335559739\u0026amp;quot;:100,\u0026amp;quot;335572079\u0026amp;quot;:8,\u0026amp;quot;335572080\u0026amp;quot;:4,\u0026amp;quot;335572081\u0026amp;quot;:11824430,\u0026amp;quot;469789806\u0026amp;quot;:\u0026amp;quot;single\u0026amp;quot;}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:640,\u0026amp;quot;335559991\u0026amp;quot;:320,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;19\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Bachelor’s or Master’s degree in electrical engineering\u0026amp;nbsp;or closely related field;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:44,\u0026amp;quot;335559739\u0026amp;quot;:44}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:640,\u0026amp;quot;335559991\u0026amp;quot;:320,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;20\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;10-12+ years of progressive electrical engineering experience, with at least 5 years focused on high-speed SerDes-based interconnect, active copper cable, or optical/pluggable module products\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:44,\u0026amp;quot;335559739\u0026amp;quot;:44}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:640,\u0026amp;quot;335559991\u0026amp;quot;:320,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;21\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Demonstrated track record of architecting and delivering production hardware with 56G\u0026amp;nbsp;/\u0026amp;nbsp;112G\u0026amp;nbsp;and faster\u0026amp;nbsp;SerDes interfaces (Ethernet, PCIe, or InfiniBand)\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:44,\u0026amp;quot;335559739\u0026amp;quot;:44}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:640,\u0026amp;quot;335559991\u0026amp;quot;:320,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;22\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Expert-level understanding of signal integrity principles\u0026amp;nbsp;- impedance\u0026amp;nbsp;control, differential pair management, eye mask budgeting, channel loss allocation\u0026amp;nbsp;-\u0026amp;nbsp;sufficient to author design rules and review layout without performing full SI simulation\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:44,\u0026amp;quot;335559739\u0026amp;quot;:44}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:640,\u0026amp;quot;335559991\u0026amp;quot;:320,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;23\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Proficiency with EDA tools: industry-standard schematic capture (Cadence Allegro / OrCAD) and PCB layout review\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:44,\u0026amp;quot;335559739\u0026amp;quot;:44}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:640,\u0026amp;quot;335559991\u0026amp;quot;:320,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;24\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Deep familiarity with OSFP, QSFP-DD800, and SFP-DD MSA mechanical, electrical, and management specifications\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:44,\u0026amp;quot;335559739\u0026amp;quot;:44}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; 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data-font=\u0026quot;\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:640,\u0026amp;quot;335559991\u0026amp;quot;:320,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;27\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Strong PDN design fundamentals: multi-rail sequencing, transient response, decoupling strategy, and thermal-electrical co-analysis\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:44,\u0026amp;quot;335559739\u0026amp;quot;:44}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:640,\u0026amp;quot;335559991\u0026amp;quot;:320,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;28\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Experience interfacing with silicon\u0026amp;nbsp;vendors/teams\u0026amp;nbsp;on\u0026amp;nbsp;customizing\u0026amp;nbsp;reference design, silicon errata management, and platform bring-up\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:44,\u0026amp;quot;335559739\u0026amp;quot;:44}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:80}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Preferred Qualifications\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:340,\u0026amp;quot;335559739\u0026amp;quot;:100,\u0026amp;quot;335572079\u0026amp;quot;:8,\u0026amp;quot;335572080\u0026amp;quot;:4,\u0026amp;quot;335572081\u0026amp;quot;:11824430,\u0026amp;quot;469789806\u0026amp;quot;:\u0026amp;quot;single\u0026amp;quot;}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:640,\u0026amp;quot;335559991\u0026amp;quot;:320,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;29\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Experience at the architecture or lead engineer level on 800G or beyond module programs\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:44,\u0026amp;quot;335559739\u0026amp;quot;:44}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:640,\u0026amp;quot;335559991\u0026amp;quot;:320,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;30\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Familiarity with co-packaged optics (CPO) or linear drive (LPO) module electrical\u0026amp;nbsp;architecture\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:44,\u0026amp;quot;335559739\u0026amp;quot;:44}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:640,\u0026amp;quot;335559991\u0026amp;quot;:320,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;31\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Working knowledge of host-side switching ASIC electrical interfaces and SerDes equalization schemes\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:44,\u0026amp;quot;335559739\u0026amp;quot;:44}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:640,\u0026amp;quot;335559991\u0026amp;quot;:320,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;32\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Participation in OIF, IEEE 802.3, or QSFP/OSFP MSA standards bodies\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:44,\u0026amp;quot;335559739\u0026amp;quot;:44}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:640,\u0026amp;quot;335559991\u0026amp;quot;:320,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;33\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Experience with PCIe Gen 5/6 retimer module designs\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:44,\u0026amp;quot;335559739\u0026amp;quot;:44}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;•\u0026quot; data-font=\u0026quot;\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:640,\u0026amp;quot;335559991\u0026amp;quot;:320,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;•\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;34\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Scripting fluency in Python for lab automation, measurement data reduction, or hardware characterization workflows\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;335559738\u0026amp;quot;:44,\u0026amp;quot;335559739\u0026amp;quot;:44}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025526005,"name":"Hardware Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4002878005,"name":"Shanghai","location":"Shanghai, China","child_ids":[],"parent_id":4002875005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4644664005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4411761005,"location":{"name":"San Jose, CA"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Hardware Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4644664005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2179","title":"Principal Electronics Engineer - Board Validation","company_name":"Astera Labs","first_published":"2025-12-30T17:11:06-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;As a\u0026amp;nbsp;\u0026lt;strong\u0026gt;Principal Electronics Engineer\u0026amp;nbsp;\u0026lt;/strong\u0026gt;you will join the Hardware Electrical Validation team at Astera Labs, linking between the Hardware Electrical Design teams and Post-Silicon Electrical Validation teams, among others.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Note: This role is not post-silicon electrical validation; it is electrical validation of PCBAs and related\u0026amp;nbsp;hardware products.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Support the Hardware Electrical Design teams with de-risking circuits and modules from project kick-off to gerber out.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop comprehensive hardware electrical validation plans using correct test methods and processes.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Bring up the PCBAs upon arrival in the lab, and execute the electrical validation plans to validate all circuits on the board.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Debug complex multi-point failures in hardware - power regulators, DPMs, clock synthesizers, digital control paths, I2C, SPI, etc.\u0026amp;nbsp; \u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Rework components on the PCBAs to unblock debugging activities.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Pre-empt and de-risk system validation architectures - collaborate with the System Validation teams.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support hardware activities in auxiliary teams - Post-Silicon Electrical Validation, Product Apps, System Validation, FAEs, etc.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support the new designs using knowledge of existing products to de-risk new features and requirements.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Self-informed of new industry test standards and equipment to introduce modern testing methodologies.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Specify test equipment, develop test fixtures, help improve hardware lab functions.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Skills:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Demonstrated strong skills in electronic circuit analysis, comprehensive testing and debug\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Bachelor degree in EE with 10+ years of experience in hardware test or design\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Define/refine hardware test methodologies and identify appropriate test equipment\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Expert understanding of design and test for power regulators, PDNs, Bode, clock gens\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ability to produce test description from a schematic design, and execute and document results\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Demonstrated knowledge of the full hardware product lifecycle from Project Kick-off to RTM\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lab equipment for hardware test - oscilloscopes, e-loads, VNA, TDR, environmental chambers, etc.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Automating lab equipment to optimize test processes, Python preferred\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Skills:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Measurements of high-speed interfaces - PCIe, DDR, 25/50G/100G SERDES, etc.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;EMI/EMC compliance\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Technical writing skills - ECOs, Bug Reports, Rework WIs, MCOs, etc.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;PLM, Arena or equivalent\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Understanding of the ASIC/silicon product development process\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Base salary range is $185,000 USD-$230,000 USD, and will be determined based on the candidate\u0026#39;s capabilities and employees in similar positions.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025526005,"name":"Hardware Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4600077005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4390181005,"location":{"name":"San Jose, CA"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Design Verification","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4600077005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"1906","title":"Principal Emulation Engineer","company_name":"Astera Labs","first_published":"2025-09-09T19:59:51-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;We are looking for a Principal Emulation Engineer with hands-on experience verifying protocols on complex ASICs and experience with or interest in emulation. \u0026amp;nbsp;The ideal candidate would be at ease creating environments to enable verification teams to stress test ASICs, as well as debugging design, environment, transactor, and code issues. \u0026amp;nbsp;The candidate must have good knowledge of communication protocols such as PCI-Express (Gen-3 and above), DDR, Ethernet, NVMe, or similar interfaces.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Basic qualifications:\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong academic and technical background in computer/electrical engineering. At a minimum, a Bachelor’s in EE or Computer Science is required, and a Master’s is preferred.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;≥8 years’ experience supporting or developing complex SoC/silicon products for Server, Storage or Networking applications.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience working with logic designers to architect, specify, and verify hardware-software interfaces on complex SoCs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Professional attitude with the ability to prioritize a dynamic list of multiple tasks and to work with minimal guidance and supervision.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Authorized to work in the US and start immediately.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Required experience:\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Working knowledge of PCIe, Ethernet, DDR, SPI, I2C/I3C or similar protocols.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;High level of proficiency in System Verilog and verification environments.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience understanding software and hardware co-simulation limitations and debug methods.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience in programming and scripting languages (like perl/python/C).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Currently based locally or open to relocation.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Preferred experience:\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience in emulation and prototyping technologies like Palladium/Zebu/Veloce or HAPS and FPGA prototyping.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience in modeling for emulation and prototyping, and/or non-UVM environments\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;p\u0026gt;The base salary range is $209,000.00 USD – $230,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.\u0026amp;nbsp;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4663818005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4420460005,"location":{"name":"Bengaluru, Karnataka, India"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"IC Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4663818005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2294","title":"Principal Engineer, Analog Mixed-Signal IC Layout","company_name":"Astera Labs","first_published":"2026-03-10T04:33:59-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;div\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-olk-copy-source=\u0026quot;MessageBody\u0026quot;\u0026gt;Job Overview:\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;p\u0026gt;As an Analog Mixed-Signal IC Layout Lead Engineer, you will play a critical role in designing advanced node Bi-CMOS / CMOS products. You will be responsible for managing chip top-level layout and integration along with block level layout design and ensuring successful tapeout. You will work to build state-of-the art high speed circuits minimizing layout parasitics, while applying techniques to reduce skew and crosstalk. Meeting EM/IR compliance requirements is essential. You will ensure strict adherence to DRC, LVS, ANT, and density rules. Additionally, awareness of ESD and latch-up design practices is expected to ensure robust and reliable layout implementations. You will apply a solid foundation in device physics, along with demonstrating a strong three-dimensional understanding of device layout.\u0026lt;/p\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;p\u0026gt;You will collaborate with a dynamic, cross-functional team of analog designers and layout engineers across multiple time zones. We are looking for a highly motivated, team-oriented individual who thrives in a collaborative environment.\u0026lt;/p\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;ul type=\u0026quot;disc\u0026quot;\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s degree or advanced diploma in Electrical Engineering (EE)\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Experience:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;ul type=\u0026quot;disc\u0026quot;\u0026gt;\n\u0026lt;li\u0026gt;10+ years of experience in high-speed analog IC layout using Cadence Virtuoso\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Prior experience with BiCMOS layout is strongly preferred\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven experience handling at least one chip top-level through tapeout\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency in layout extraction and parasitic analysis for high-speed circuits\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Awareness of EMIR and antenna DRC rule-compliant layout practices\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with Cadence SKILL and TCL scripting is highly recommended\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4135671005,"name":"SerDes","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4049113005,"name":"Bengaluru","location":"Bengaluru, India","child_ids":[],"parent_id":4052109005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4667065005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4422035005,"location":{"name":"Shanghai, China"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Ecosystem Marketing","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4667065005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2325","title":"Principal Engineer, Ecosystem Partnership \u0026 Marketing ","company_name":"Astera Labs","first_published":"2026-03-05T16:51:41-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Principal Engineer, Ecosystem Partnership \u0026amp;amp; Marketing – Asia Region\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with\u0026amp;nbsp;hyperscalers\u0026amp;nbsp;and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet,\u0026amp;nbsp;NVLink, PCIe®, and\u0026amp;nbsp;UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored\u0026amp;nbsp;architectures\u0026amp;nbsp;to meet their unique infrastructure requirements.\u0026amp;nbsp;Learn\u0026amp;nbsp;more at \u0026lt;/span\u0026gt;\u0026lt;a href=\u0026quot;http://www.asteralabs.com/\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-charstyle=\u0026quot;Hyperlink\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/a\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Are you passionate about creating differentiated products and working with hyperscale and AI platform\u0026amp;nbsp;providers to deploy the next generation of data center infrastructure?   \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;We are\u0026amp;nbsp;seeking\u0026amp;nbsp;a highly technical and experienced\u0026amp;nbsp;Principal Ecosystem Partnership \u0026amp;amp; Marketing Manager\u0026amp;nbsp;drive business growth, product adoption, and ecosystem innovation across the Asia region, with\u0026amp;nbsp;an initial\u0026amp;nbsp;focus on China. This role will lead strategic engagement with key ecosystem partners—including CPU, GPU, and XPU platform providers—and customers, working closely with Astera Labs sales, field applications engineering (FAE), product management, engineering, and corporate marketing teams.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;This is a high-visibility role with regular interaction with executive leadership and requires a strong blend of technical depth, market insight, and leadership. The ideal candidate has deep experience in AI and cloud infrastructure, excels at cross-functional collaboration, and can translate complex technologies into compelling rack-scale solutions built on Astera Labs’ Intelligent Connectivity Platform.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;This position is based in Astera Labs’ Shanghai office and requires an in-person presence, with regular travel across the Asia region.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Key Responsibilities\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Define compelling product\u0026amp;nbsp;and solution\u0026amp;nbsp;positioning and messaging that differentiates our products in the market and resonates with our target\u0026amp;nbsp;partners and\u0026amp;nbsp;customers\u0026amp;nbsp;in the Asia region\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Drive technology roadmap alignment with key CPU, GPU, and XPU ecosystem partners to ensure tight integration and long-term platform relevance\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Collaborate with partners and internal teams to\u0026amp;nbsp;jointly\u0026amp;nbsp;create compelling rack-scale solutions built on Astera Labs’ Intelligent Connectivity Platform, increasing customer value and accelerating adoption\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Drive competitive analysis and gather partner and customer insights to\u0026amp;nbsp;identify\u0026amp;nbsp;market trends, unmet needs, and opportunities for innovation\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Act as the Voice of the Customer (VoC) for assigned strategic accounts, influencing product direction, platform strategy, and go-to-market execution\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Collaborate closely with cross-functional teams including product line management, engineering, sales,\u0026amp;nbsp;field applications engineering\u0026amp;nbsp;and corporate marketing to align on product roadmap, features, and\u0026amp;nbsp;customer facing\u0026amp;nbsp;deliverables\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;7\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Leverage, translate and customize high-impact marketing collateral including presentations, blogs, whitepapers, and case studies to support product sales and adoption\u0026amp;nbsp;in the Asia region\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;8\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Develop engaging cross-product sales enablement collateral, perform regular training sessions with customer-facing\u0026amp;nbsp;teams\u0026amp;nbsp;and support strategic sales activities\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;9\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Serve as a product evangelist internally and externally,\u0026amp;nbsp;representing\u0026amp;nbsp;our products at industry events, conferences, press/analyst\u0026amp;nbsp;presentations\u0026amp;nbsp;and customer engagements\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;10\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Track and analyze key performance metrics to measure the effectiveness of product marketing initiatives and drive continuous improvement\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Qualifications\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Bachelor’s degree in\u0026amp;nbsp;Engineering, or related field; MBA preferred\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;7+ years of experience in\u0026amp;nbsp;product-focused, customer-facing roles\u0026amp;nbsp;within the semiconductor industry\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Understanding of PCIe, CXL,\u0026amp;nbsp;Ethernet, and/or\u0026amp;nbsp;UALink\u0026amp;nbsp;technologies and their applications in\u0026amp;nbsp;AI and\u0026amp;nbsp;cloud infrastructure\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Network of contacts in AI and cloud infrastructure industry in China\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Previous\u0026amp;nbsp;experience in Business Development, Product Marketing, Product Management, Ecosystems\u0026amp;nbsp;Partnerships\u0026amp;nbsp;or similar roles\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; 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data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;10\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience working with customers and partners to understand their needs and drive product adoption\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;11\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience with customer negotiation,\u0026amp;nbsp;influencing successful pricing strategies, and\u0026amp;nbsp;executing agreements\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;4\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;12\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Willingness to travel\u0026amp;nbsp;up to approximately 25%\u0026amp;nbsp;for\u0026amp;nbsp;partner/customer meetings,\u0026amp;nbsp;company training,\u0026amp;nbsp;industry events, and conferences\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025317005,"name":"Marketing","child_ids":[],"parent_id":null}],"offices":[{"id":4002878005,"name":"Shanghai","location":"Shanghai, China","child_ids":[],"parent_id":4002875005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4690506005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4433033005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"CTO Organization","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4690506005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2493","title":"Principal Engineer, SOC IP Systems \u0026 Lifecycle Management","company_name":"Astera Labs","first_published":"2026-04-29T14:48:55-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;h3\u0026gt;\u0026lt;strong\u0026gt;Role Objective\u0026lt;/strong\u0026gt;\u0026lt;/h3\u0026gt;\n\u0026lt;p\u0026gt;As the gatekeeper of IP Management, Methodology and Quality at Astera Labs, you will lead the strategic development of our AI-powered IP Lifecycle Management and IP Quality Assurance Platform. You won\u0026#39;t just run tools; you will architect a scalable, user-friendly system that serves as the foundation for our \u0026quot;AI-first\u0026quot; IP ecosystem. Your mission is to ensure every IP, whether internal or external is easily accessible, physically, logically, and structurally \u0026quot;SOC-ready,\u0026quot; preventing late-stage integration breaks that delay tape-outs. Our vision is to revolutionize IP Management and Quality Assurance with an AI-first approach.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;The candidate will be responsible for developing the platform, auditing and qualifying internal and external IP (Hard/Soft Macros, PHYs, Memories and standard cells libraries among other IPs). The IPLM and IPQA tools will scale to cover SOC QA and be a key element of the tape out sign-out requirements. The successful candidate will have the right expertise to run all EDA tools, understand the results, challenge the false pass scenarios, and dig into the root cause of real errors. They will work with the vendors or with our internal IP teams to solve the issues.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;They will be responsible for ensuring that all IP deliveries are integrable, timing-clean, and manufacturable, preventing \u0026quot;late-stage\u0026quot; SOC breaks caused by inconsistent IP views or structural violations. IPQA will cover all aspects of the design flow starting from Architecture coherence, PPA evaluation, Front-End integration, SDC, RDC, DFT, PD and PDV, Packaging, ESD, Waivers, IP-XACT; and be scalable from the technology foundations, FinFet and Gate-All-Around transistors’ properties, DK/PDK integrity and rule decks from foundries, Standard Cells, Memories, IP, Subsystems and SOC Quality.\u0026lt;/p\u0026gt;\n\u0026lt;h3\u0026gt;\u0026lt;strong\u0026gt;Technical Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/h3\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;AI-Driven Automation:\u0026lt;/strong\u0026gt; Architect and Lead the integration of agentic AI workflows into the IPLM and IPQA platform to automate IP Management, root-cause analysis of false pass scenarios and self-heal real issues.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Chiplet Readiness:\u0026lt;/strong\u0026gt; Verify IP compliance with high-speed and high-bandwidth interface standards for heterogeneous integration.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Cross-View Consistency:\u0026lt;/strong\u0026gt; Architect automated audits for logical-to-physical consistency across RTL, Liberty, LEF, GDSII, and CDL views, focusing on pin-naming, bus-integrity, and functionality.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Physical \u0026amp;amp; Sign-off Audits:\u0026lt;/strong\u0026gt; Perform independent LVS, DRC, and Antenna signoffs using native runsets for 5nm/3nm and beyond nodes.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Structural \u0026amp;amp; DFT Verification:\u0026lt;/strong\u0026gt; Validate DFT requirements, including scan-chain integrity, MBIST handshakes, and fault-coverage transparency.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Power \u0026amp;amp; Timing Integrity:\u0026lt;/strong\u0026gt; Audit Power Domain (UPF/CPF) consistency and conduct deep-dive Liberty (.lib) audits to identify missing timing arcs or non-monotonic lookup tables. Audit IR-drop/EM (Electromigration) reports to ensure the IP won\u0026#39;t cause localized power grid failures.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Waiver Management:\u0026lt;/strong\u0026gt; Develop rigorous, automated Waiver Audit Protocol to ensure that provider-cleared violations do not violate Astera Labs\u0026#39; internal sign-off deck requirements.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Lessons learned\u0026lt;/strong\u0026gt; from release to release, from generation to generation need to be tracked and checked. Responsible for making sure releases are complete; patches are integrated. Constraints are updated, and documentation reflects the updates including PPA impact.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h3\u0026gt;\u0026lt;strong\u0026gt;Required Skills \u0026amp;amp; Expertise\u0026lt;/strong\u0026gt;\u0026lt;/h3\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;IP \u0026amp;amp; EDA Expert:\u0026lt;/strong\u0026gt; Mastery of the full sign-off suite: PrimeTime, Fusion Compiler, Genus, Calibre, Innovus, IC Compiler, SpyGlass, Tessent, Liberate (/MX), PrimeSim. Cross-Tool Consistency expertise is a must.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Advanced Scripting for Information Systems:\u0026lt;/strong\u0026gt; Expert in Tcl for tool manipulation and Python for building AI-wrapper layers. Familiarity with SystemVerilog.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Domain Depth:\u0026lt;/strong\u0026gt; Deep understanding of FinFET/Gate-All-Around (GAA) properties, Electromigration (EM), and ESD rules. Deep knowledge of Liberty modeling and LEF/DEF physical formats.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;QA Philosophy:\u0026lt;/strong\u0026gt; A \u0026quot;Detective\u0026quot; mindset with the ability to look past a \u0026quot;green\u0026quot; or “red” report to find false errors and rootcause real ones.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Management skills:\u0026lt;/strong\u0026gt; Ability to work with design teams and IP vendors to solve issues in a timely manner.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;The base salary range is \u0026lt;strong\u0026gt;$175,000.00 USD – $230,000.00 USD\u0026lt;/strong\u0026gt;. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4133890005,"name":"CTO","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4700203005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4438038005,"location":{"name":"Bengaluru, Karnataka, India"},"metadata":[{"id":12122734005,"name":"Country","value":"India","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Bengaluru","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Physical Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4700203005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2595","title":"Principal Engineer, STA","company_name":"Astera Labs","first_published":"2026-06-03T05:04:08-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is hiring a \u0026lt;strong\u0026gt;Principal Engineer, Static Timing Analysis\u0026lt;/strong\u0026gt; to own top-level timing closure and signoff for our next-generation connectivity silicon powering rack-scale AI infrastructure. In this role, you\u0026#39;ll drive full-chip STA strategy across advanced process nodes, partner with physical design, RTL, DFT, and CAD teams, and ensure first-pass timing success on some of the most complex SoCs in the industry.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This is a high-impact technical leadership role at a hyper-growth company purpose-built for AI connectivity. Your work directly enables the PCIe, CXL, UALink, and Ethernet platforms that hyperscalers depend on — and you\u0026#39;ll have the ownership, influence, and tooling to do the best work of your career.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Full-Chip STA Signoff \u0026amp;amp; Timing Closure\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Own end-to-end top-level STA signoff across multiple modes, corners, and operating conditions (MMMC) for complex AI connectivity SoCs\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive timing convergence on advanced process nodes (5nm/4nm/3nm and below) from early floorplan through tapeout\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Analyze and resolve setup, hold, recovery/removal, and clock-domain crossing (CDC) timing violations at the chip level\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Methodology \u0026amp;amp; Flow Development\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Define and evolve STA methodology, constraints (SDC) strategy, and signoff criteria across the organization\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop and automate flows using PrimeTime, PrimeTime SI, and related signoff tools for crosstalk, noise, and IR-aware timing\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Establish best practices for hierarchical STA, ETM/IPXACT model generation, and budgeting across blocks\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional Technical Leadership\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Partner with Physical Design, RTL, DFT, CAD, and Package teams to drive timing-aware design decisions from architecture through tapeout\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Review and sign off on block-level timing handoffs, ensuring consistency between block and top-level closure\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with low-power design teams on UPF/CPF, multi-voltage, and clock-gating timing implications\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Mentorship \u0026amp;amp; Technical Strategy\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Mentor STA engineers and review timing reports, ECOs, and signoff collateral\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive root-cause analysis of silicon timing issues and feed learnings back into methodology\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Influence tool selection, EDA vendor engagements, and STA roadmap for future products\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor\u0026#39;s or Master\u0026#39;s degree in Electrical Engineering, Electronics Engineering, or related field\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;10+ years of hands-on experience in Static Timing Analysis on complex ASIC/SoC designs\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven track record of full-chip top-level STA signoff on at least one tapeout at advanced nodes (7nm or below)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep expertise with PrimeTime, PrimeTime SI, and SDC constraint development\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of clocking architectures, CDC, OCV/AOCV/POCV, crosstalk, and IR-aware timing\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency in scripting (Tcl, Python, Perl) for STA flow automation and report analysis\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience with high-speed connectivity SoCs (PCIe Gen 6/7, CXL, UALink, or Ethernet)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with hierarchical STA, ETM/ILM models, and timing budgeting across large partitions\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with low-power signoff (UPF/CPF), multi-voltage domains, and DVFS timing implications\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong cross-functional collaboration and mentorship skills in a fast-paced product environment\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4135671005,"name":"SerDes","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4049113005,"name":"Bengaluru","location":"Bengaluru, India","child_ids":[],"parent_id":4052109005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4696806005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_optional","internal_job_id":4425617005,"location":{"name":"Taipei, Taiwan"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Field Applications Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4696806005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2387","title":"Principal Field Applications Engineer","company_name":"Astera Labs","first_published":"2026-05-19T00:30:28-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;As an Astera Labs Principal Field Applications Engineer, you will support the world’s leading cloud service providers, server and network OEMs by working with them to design solutions that use Astera Labs’ portfolio of connectivity products. In this role, you will need to identify and understand customer requirements, propose Astera Labs solutions that provide clear value to the customer and provide hands-on design-in support. You will drive innovation by listening to the customer requirements, working with our engineering teams to implement into the product roadmap and delivering the results back to the customer.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026amp;nbsp;Basic qualifications:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;BS in electrical engineering. Master’s degree in engineering is preferred.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Minimum of 8 years’ experience working with Cloud service providers and server OEM customers to design in complex SoC/silicon products for Server, Storage, and/or Networking applications.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Customer-oriented, Goal-driven, Self-motivated, be able to work independently and be able to travel frequently to customer sites\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Fluent in Mandarin and English\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Entrepreneurial, open-mind behavior and can-do attitude. Think and act with the customer in mind!\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required experience:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Hands-on, thorough knowledge of high-speed protocols like PCIe \u0026amp;amp; Ethernet\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Silicon/System bring-up and debug experience in customer systems.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with lab equipment including protocol analyzers and oscilloscopes.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;A strong background in high-speed board design techniques, and understanding of Data Center systems like Servers, JBOGs/JBODs, Networking switches/routers etc.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Intermediate level of proficiency in Python for automating system validation and link optimization.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Able to step through embedded firmware at the SerDes (SoC) or MCU level for debugging.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Firsthand experience with lab equipment including traffic generators, analyzers, and high-speed oscilloscopes.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Business travel to Asia and the North America region may be required as needed.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred experience:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong working knowledge of a high speed interface at a physical layer level, associated standards, and debug. Most recent experience with 12G NRZ signaling at a minimum, some experience with 25G NRZ/56G PAM4 preferred.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Development, support, and experience with PCIe ICs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience in embedded SW debug or development with firmware, drivers, and BIOS using PCIe technology.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4134751005,"name":"Field Applications","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4009035005,"name":"Taipei","location":"Taipei, Taiwan","child_ids":[],"parent_id":4002874005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4695017005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4435646005,"location":{"name":"Bengaluru, Karnataka, India"},"metadata":[{"id":12122734005,"name":"Country","value":"India","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Bengaluru","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Firmware Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4695017005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2539","title":"Principal Firmware QA Engineer ","company_name":"Astera Labs","first_published":"2026-05-26T03:42:00-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Title\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;: \u0026lt;strong\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Lead Firmware QA Engineer\u0026lt;/span\u0026gt;, A\u0026lt;/strong\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;stera Labs, Bengaluru, India.\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;br\u0026gt;\u0026amp;nbsp;\u0026lt;br\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Astera Labs Inc., a leader in purpose-built connectivity solutions for data-centric systems, is seeking \u0026lt;strong\u0026gt;Lead Software QA Engineer\u0026lt;/strong\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt; for their Bengaluru (India) Design Center. Partnering with leading processor and GPU vendors, cloud service providers, world-class manufacturing companies, Astera Labs is helping data-centric system designers remove performance bottlenecks in compute-intensive workloads such as Artificial Intelligence and Machine Learning.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134245417\u0026amp;quot;:false}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;:\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s degree in electrical engineering (EE) or Computer Science is required; a master’s or PhD in EE is preferred with minimum 4 years of experience.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Experience\u0026lt;/strong\u0026gt;:\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experienced and detail oriented PCIe switch test engineer with solid understanding of PCIe protocol.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Estimate work, identify dependencies and develop schedules.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Responsible for designing and executing functional, performance, interoperability and stress tests.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work closely with\u0026amp;nbsp; Silicon team, architecture team, FW development team to understand the design and develop test strategies.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Responsible for manual and automation testing.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong knowledge of scripting ( Python ) is must.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Responsible for automation development and manual testing.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Perform Signal integrity and protocol level validation.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Closely work with development teams to triage and debug issues.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of collecting PCIe trace using PCIe analyzer and analyzing the trace to triage issues.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience in PRBS testing, loopback and margining tests.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Good understanding of OOB testing and Protocols like MCTP, I2C, SPDM etc.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience is PCIe compliance testing is a plus.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Regularly working with Hyperscale\u0026#39;s and Tier 1 OEMs to communicate plans and status, address escalations, deliver on SLAs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge in validation of NIC controllers and storage controllers is preferred.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Requirements management and traceability through software development phases.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Mentoring and coaching team members to help them excel in their jobs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Power user of Git, Jira and Confluence.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025528005,"name":"Software Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4049113005,"name":"Bengaluru","location":"Bengaluru, India","child_ids":[],"parent_id":4052109005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4515946005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4347019005,"location":{"name":"Singapore"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"IC Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4515946005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"1694","title":"Principal Integrated Circuit Designer","company_name":"Astera Labs","first_published":"2025-01-29T21:08:39-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As an Integrated Circuit Designer, you will be part of a key team designing sophisticated advanced node CMOS products.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Key Job Duties:\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;The design and development of the layout for integrated circuits according to electronics engineering principles, using software to create design schematics and diagrams. This will include [developing and verifying circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs to meet performance targets].\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;The management of manufacturing process of the products, including technology yield and performance of the products.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;The development of test programmes and procedures to ensure the products meet their performance specifications. This will include [working on analog and clocking blocks for connectivity applications, using industry-standard tools like Spectre and MATLAB].\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;The provision of advice on aspects of semiconductor process technology and maintain and repair semiconductor process equipment.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Basic Qualifications\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong academic and technical background in electrical engineering. A Master’s or PhD degree in EE is required, preferably from a top-tier university.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;6+ years of experience supporting or developing complex analog IC designs.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Required Experience:\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience in designing high-speed mixed-signal circuits, including ADC/DAC data converters, RX front-end, TX driver/serializer, low-jitter PLLs, TX/RX calibration, low-jitter CLK distribution and other high-speed analog circuits is a must.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Have a deep understanding of biasing, band-gaps, reference circuits, opamps, comparators and other analog circuits.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026amp;nbsp;Solid track-record for implementation of analog circuits high-speed data transmissions.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Design and tapeout experience in advanced CMOS nodes (ex. 20nm or newer) is a must.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Solid fundamentals in detailed transistor-level design, feedback/stability analysis, and noise/jitter analysis.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of TIA design and drivers for optical applications is highly desirable.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience in RFIC design for wireless or wireline communication systems is highly desirable.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong technical independent contributor with a proven ability to drive results.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent teamwork, presentation, and documentation skills.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ability to collaborate with global teams across multiple time zones and deliver under pressure with strict deadlines.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong experience in lab chip bring-up and debugging efforts.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Preferred Experience:\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Relevant research publications and/or patents in analog or RF IC design.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity in programming/scripting languages such as Python, Matlab, or C.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with PCB design.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with Verilog RTL or DSP design concepts.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of optical transceivers.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Expertise in ESD protection techniques and IC packaging methodologies.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4135671005,"name":"SerDes","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4052115005,"name":"Singapore City, Singapore","location":"Singapore","child_ids":[],"parent_id":4050465005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4668457005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4422722005,"location":{"name":"San Jose, CA"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"IC Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4668457005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2333","title":"Principal Mixed Signal Design Verification Engineer","company_name":"Astera Labs","first_published":"2026-03-03T12:50:18-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Job Description\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;We are looking for Principal Design Verification Engineers with proven experience in all aspects of verification in UVM and C/C++. The candidate must have experience using high level programming languages such as C/C++ to communicate with System Verilog and/or UVM based environments to aid RTL simulation, CoSimulation and Emulation.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic qualifications:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is\u0026lt;br\u0026gt;required, and a Maser’s is preferred.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;≥8 years’ experience supporting or developing complex high-speed SerDes/silicon products for Server, Storage, and/or\u0026lt;br\u0026gt;Networking applications.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for\u0026lt;br\u0026gt;customer meetings in advance, and to work with minimal guidance and supervision.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Authorized to work in US and start immediately.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience with integrating Matlab/Simulink/C/C++ in System Verilog environments using DPI/PLI\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ability to use scripting tools (Perl/Python) to automate verification infrastructure.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience in developing infrastructure and tests in a hybrid directed and constrained random\u0026lt;br\u0026gt;environments\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Must be able to work independently to develop test-plans, and related test-sequences in UVM to\u0026lt;br\u0026gt;generate stimuli and work collaboratively with RTL designers to debug failures.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop user-controlled random constraints in transaction-based verification methodology. Experience\u0026lt;br\u0026gt;writing assertions, cover properties and analyzing coverage data\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Must have prior experience on End-to-End Mix-Signal SerDes verification with channel modeling and compliance testing.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Must have prior experience on verification with firmware to control and configure the SerDes and related components.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;SW debugging for Mix-Signal based designs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with PHY layer verification in PCIe, Ethernet, and/or UAL.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with FPGA-based verification/emulation.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4135671005,"name":"SerDes","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4697341005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4436753005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose (HQ)","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Hardware Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4697341005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2566","title":" Principal Optical Module Validation Engineer ","company_name":"Astera Labs","first_published":"2026-05-21T17:41:21-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Job Overview\u0026lt;br\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;br\u0026gt;As a\u0026amp;nbsp;\u0026lt;strong\u0026gt;Principal Optical Module Validation Engineer \u0026lt;/strong\u0026gt;at Astera Labs,\u0026amp;nbsp; you will be working alongside many functions in the company, from Marketing to Engineering, Validation and Applications. You will be responsible for validating optical systems that incorporate Astera Labs’ diverse range of connectivity and memory products that are widely used by leading cloud service providers, server manufacturers, and network OEMs. You will be involved in every stage of design, from concept, test, to mass production.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;In addition to your core responsibilities, you will have the opportunity to drive innovation within the organization by providing insightful feedback to internal teams. Your expertise and suggestions will contribute to the continuous improvement of our products and processes. You may also collaborate on or even lead activities that are closely related, such as manufacturing, customer engagement, and post-production support.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;We are looking for an ideal candidate who brings industry experience, possesses innovative thinking, and demonstrates a high level of expertise in their field. Moreover, you should exhibit a proactive “do what it takes” attitude, always ready to assist and contribute wherever necessary to effectively solve problems and achieve successful outcomes.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong academic and technical background in direct detect optical systems for data center applications\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s in EE is required; Master’s is preferred.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Minimum of 8 years’ experience in optical link analysis and module design, from component selection and schematic capture through bring-up, debug, optimization, and validation.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Experience:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Understanding of high speed (\u0026amp;gt;32Gbps) signal and power integrity challenges for electro-optical interfaces\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Technical knowledge of single mode (preferred) and/or multimode optical systems design, simulation and manufacturing.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Optical simulation flow experience for link analysis\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Optical system bring-up and debug experience.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on optical equipment measurements such as TDECQ, Laser Rin and/or optical system BER\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Understanding of FW closed-loop systems required for laser, modulator, and PD systems\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Track record of taking products from concept to mass production\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Experience/Nice to Have:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Working with mechanical and thermal teams to create achievable system design specifications.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Working with silicon characterization/validation teams to ensure device performance is readily achievable in customer systems.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Technical writing skills to generate clear, precise documentation such as hardware specifications and user’s guides for internal and customer-facing audiences.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience in “adjacent” areas such as manufacturing, quality, compliance.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience working with CMs, OSTATs and other external suppliers\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;The base salary range is $160,000 - $240,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025526005,"name":"Hardware Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4667442005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4422237005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Engineering Operations","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4667442005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2327","title":"Principal Package Signal \u0026 Power Integrity ","company_name":"Astera Labs","first_published":"2026-02-27T20:07:55-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Job Description: \u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As a \u0026lt;strong\u0026gt;Principal Package Signal \u0026amp;amp; Power Integrity Engineer\u0026lt;/strong\u0026gt; at Astera Labs, you will serve as a senior technical leader responsible for architecting, optimizing, and signing off package SIPI solutions for next-generation connectivity products. You will drive package electrical architecture across high-performance IC packaging platforms, including FCBGA, coreless substrates, chiplet-based packages, 2.5D/3D integration, silicon interposers, bridge-based interconnect, and heterogeneous multi-die systems.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;In this role, you will lead SIPI strategy and execution for products supporting PCIe, CXL, Ethernet, 200G/400G+ SerDes, and die-to-die interconnect. You will partner closely with silicon architecture, SerDes/IP teams, package design, PCB design, hardware validation, manufacturing, substrate vendors, and OSAT partners to optimize signal integrity, power delivery, substrate/interposer routing, bump planning, and system-level electrical performance while balancing cost, manufacturability, reliability, yield, and schedule.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;You will also drive SIPI methodology, modeling standards, simulation-to-measurement correlation, and chip–package–board co-design frameworks to enable scalable execution across multiple product lines.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Define package SIPI architecture and design strategy for high-performance connectivity products, including PCIe 5.0/6.0/7.0, CXL, Ethernet, 200G/400G+ SerDes, and die-to-die interconnect.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Perform package and system-level SI and PI simulations using industry-standard simulation software such as HFSS, SIwave, and Keysight ADS to develop, optimize, and sign off package electrical models, validate package architecture and designs, and ensure robust signal and power integrity across chip–package–board systems.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead cross-functional execution across silicon team, package design, marketing and APPs, PCB board team, validation team, package manufacturing, and external substrate/OSAT partners, managing technical tradeoffs among SIPI performance, cost, DFM, yield, etc., and deliver packaging solutions on schedule.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive simulation-to-measurement correlation strategy, ensuring strong alignment between EM extraction, system-level models, and lab validation (VNA, TDR, high-speed oscilloscope), continuously improving model accuracy, simulation efficiency, and SIPI signoff criteria.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Own SIPI simulation and signoff for advanced packaging platforms, including chiplet-based packages, 2.5D/3D integration, silicon interposers, and bridge-based interconnect, by leading simulations for D2D interconnect (e.g., UCIe), multi-die PDN, micro-bump modeling, TSV/interposer modeling, and multi-die CPM co-simulation.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Define substrate, interposer, and bridge routing guidelines for high-speed SerDes and D2D interfaces, including impedance targets, differential-pair geometry, via/transition optimization, return-current management, shielding, skew control, and crosstalk isolation.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Establish SIPI modeling standards, design rules, review checklists, automation flows, and signoff methodologies to improve execution efficiency, while mentoring engineers across the organization.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required qualifications:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;10+ years of experience in signal integrity, power integrity, package electrical design, or chip–package–board co-design for high-performance semiconductor products.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep expertise in package SIPI modeling, analysis, optimization, and signoff across the chip–package–board system, for high-speed SerDes, PCIe, CXL, Ethernet, etc.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong experience with PCIe 5.0/6.0, PAM4 SerDes channel design, high-speed S-parameter extraction, package model development, eye-diagram analysis, return/insertion-loss optimization, and crosstalk analysis.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven track record delivering high-performance packages using FCBGA, FCCSP, coreless substrates, advanced organic substrates, chiplet-based packages, 2.5D integration, silicon interposers, or heterogeneous integration platforms.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on expertise with EM extraction and SIPI simulation tools such as ANSYS HFSS, SIwave, Q3D, 3D Layout, Keysight ADS, Cadence Sigrity, or equivalent tools.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Expert-level knowledge of PDN design, including DC IR drop, AC impedance, target impedance, loop inductance, decoupling optimization, transient response, noise coupling, and chip-package-model methodology.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Demonstrated ability to correlate simulation to lab measurement (VNA, TDR, high-speed oscilloscope).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of tradeoffs between SIPI performance, cost, reliability, and manufacturability.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience leading vendor engagements and managing technical execution through production ramps.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;:\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience influencing silicon floor planning, bump map definition, SerDes and power-grid planning, package escape strategy, and PCB breakout from a SIPI perspective.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with automation and scripting for SIPI modeling flow.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Exposure to Allegro Package Designer (APD) for hands-on substrate editing.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge on traditional FCBGA type package and advanced package (chiplet/2.5D/3D) manufacturing and assembly process flows\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with CPO and NPO optical package SIPI design, including high-speed channel modeling between EIC/PIC/optical engine, PDN design, crosstalk/noise analysis, and chip–package–board co-design for optical connectivity applications.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;The base salary range is $203,000 USD – $230,000 USD. Your base salary will be determined based on location, experience, and employees\u0026#39; pay in similar positions.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4678609005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4427459005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Engineering Operations","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4678609005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2422","title":"Principal Package Thermal \u0026 Mechanical Engineer","company_name":"Astera Labs","first_published":"2026-03-27T20:31:40-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As a \u0026lt;strong\u0026gt;Principal Package Thermal \u0026amp;amp; Mechanical Engineer\u0026lt;/strong\u0026gt; at Astera Labs, you will serve as a technical leader driving the development and modeling of advanced IC packaging solutions that enable next-generation AI and high-performance connectivity systems.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;In this highly visible role, you will define and execute thermal and mechanical modeling strategies across the chip–package–board system, influencing package architecture, material selection, and reliability design. You will partner closely with package design, SIPI, silicon, system, and manufacturing teams to ensure robust thermal/mechanical performance and first-pass success.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;You will also drive modeling methodologies, correlation strategies, and best-known methods (BKMs), while engaging directly with customers to translate complex simulation insights into actionable system-level solutions.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Thermal \u0026amp;amp; Mechanical Modeling Leadership\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Define and drive thermal and mechanical modeling strategies for advanced packages (FCBGA, FCCSP, multi-die, and chiplet-based architectures)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Perform detailed thermal simulations including steady-state and transient heat transfer (conduction, convection, and interface resistances such as TIM1/TIM2)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop and deploy compact thermal models (CTM), reduced-order models (ROM), and DELPHI-based models for system-level integration\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Analyze power density, hotspot behavior, and package-to-system thermal interactions across air and liquid cooling environments\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Perform thermo-mechanical stress/strain analysis including CTE mismatch, viscoelastic material behavior, and deformation\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Predict package warpage across process and use conditions (reflow, underfill cure, board attach, field operation)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Model solder joint reliability and fatigue using industry standard models\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Package Architecture\u0026lt;/strong\u0026gt; \u0026lt;strong\u0026gt;\u0026amp;amp; Thermal Design Strategy\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Drive package design decisions including material selection (EMC, substrate, TIM, lid/heat spreader), thermal path optimization, and early-stage architecture definition across air and liquid cooling solutions (air, cold plate, CPO/CPC)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Conduct DOE, sensitivity studies, and worst-case analysis to guide tradeoffs across performance, cost, reliability, and manufacturability\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;System Co-Design \u0026amp;amp; Automation \u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Partner cross-functionally to drive chip–package–board co-design and resolve system-level thermal/mechanical challenges, including system integration constraints\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Serve as a technical interface for customers and internal teams, translating modeling results into actionable insights and leading design reviews and issue resolution\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop and scale modeling methodologies, workflows, and BKMs; mentor engineers and improve efficiency through automation and scripting (Python, MATLAB)\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;M.S. or Ph.D. in Mechanical Engineering, Materials Science, Electrical Engineering, or related field\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;8+ years of experience in semiconductor packaging with strong focus on thermal and mechanical modeling\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep expertise in thermal modeling and simulation, including steady-state and transient analysis, compact thermal modeling (CTM), DELPHI methodology, and system-level thermal integration using tools such as ANSYS Icepak, Flotherm, or equivalent\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep expertise in thermo-mechanical modeling and FEA simulation, including stress/strain analysis, warpage prediction, and reliability modeling (BLR/CLR), using tools such as ANSYS Mechanical, or equivalent\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven ability to correlate simulation results with lab measurements\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience influencing package design and delivering solutions to production\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong cross-functional collaboration across package design, SIPI, system, and manufacturing teams\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience with high-power AI / HPC packages and large FCBGA (\u0026amp;gt;50mm)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with advanced packaging technologies:2.5D / 3D integration, Chiplet, CPO/CPC\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with system-level cooling solutions: Liquid cooling, cold plates, immersion cooling\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of JEDEC standards and reliability qualification methodologies\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience working with OSATs and substrate vendors on thermal/mechanical design optimization\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency in scripting (Python, MATLAB) for modeling automation\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Exposure to multi-physics coupling (electrical–thermal–mechanical interactions)\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;The base salary range is $185,000 USD – $230,000 USD. Your base salary will be determined based on location, experience, and employees\u0026#39; pay in similar positions.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4691422005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4433382005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose (HQ)","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Physical Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4691422005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2499","title":"Principal Physical Design Engineer, STA","company_name":"Astera Labs","first_published":"2026-05-20T17:38:52-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Overview\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;br\u0026gt;As an Astera Labs \u0026lt;strong\u0026gt;Principal Physical Design Engineer (STA) \u0026lt;/strong\u0026gt;you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs\u0026#39; portfolio of connectivity ASICs used in the world\u0026#39;s leading cloud service providers, server and network OEMs. This role requires end-to-end STA ownership across design stages, deep technical expertise, and close collaboration with RTL, physical design, and verification teams to ensure robust full-chip timing convergence. This role is fully on-site and in-person.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Drive timing closure from RTL through sign-off, ensuring robust timing across complex SoCs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop and validate SDC constraints, including MMMC setup, to enable accurate and efficient STA analysis.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Define and manage I/O timing budgets across hierarchical designs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Apply advanced sign-off methodologies at TSMC 7nm and below, including OCV/AOCV and PVT effects.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Leverage ETM libraries for hierarchical timing analysis and correlation, balancing runtime and accuracy.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Provide actionable timing feedback at both block and full-chip levels, including root cause analysis and ECO guidance.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Manage large-scale multi-corner/multi-mode STA runs with automation, partitioning, and efficient resource usage.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Generate and validate timing ECOs, partnering with physical design and RTL teams for quick closure.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Partner closely with design, implementation, and verification teams to drive timing convergence, providing sign-off level expertise and guidance.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s in Electrical Engineering or Computer Science required; Master’s preferred.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;≥10 years of experience in timing analysis and sign-off for complex SoCs in Server, Storage, or Networking applications.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Expertise in timing constraints, STA methodology, and timing closure at both block and full-chip level.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows in advanced nodes (7nm or below).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency with Cadence and/or Synopsys physical design/STA toolchains.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong scripting ability (Tcl, Python, Perl).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ability to work independently with strong prioritization and a professional, customer-focused mindset.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with high-speed SERDES and Ethernet PHY timing challenges.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of ECO methodologies, DFT tools, and test coverage analysis.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience working with IP vendors for both RTL and hard-macro integration.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;SystemVerilog/Verilog familiarity.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;The base salary range is USD 209,000.00 USD – USD 250,000.00. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4592489005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4386552005,"location":{"name":"San Jose, CA "},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Hardware Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4592489005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"1854","title":"Principal Power and Board Design Engineer ","company_name":"Astera Labs","first_published":"2025-08-04T21:35:45-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p data-renderer-start-pos=\u0026quot;2479\u0026quot;\u0026gt;\u0026lt;strong data-renderer-mark=\u0026quot;true\u0026quot;\u0026gt;Principal Power and Board Design Engineer\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;2479\u0026quot;\u0026gt;\u0026lt;strong data-renderer-mark=\u0026quot;true\u0026quot;\u0026gt;Overview:\u0026lt;/strong\u0026gt;\u0026lt;br\u0026gt;We are seeking a highly skilled and experienced Power and Board Design Engineer to join our team. In this role, you will be responsible for designing and optimizing power delivery systems for our \u0026lt;span data-highlighted=\u0026quot;true\u0026quot; data-vc=\u0026quot;highlighted-text\u0026quot;\u0026gt;ASIC\u0026lt;/span\u0026gt; products, ensuring robust power integrity, and developing board-level designs. Your expertise will be crucial in selecting power components, collaborating with vendors, and utilizing industry-leading tools to deliver high-performance solutions.\u0026lt;/p\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;2936\u0026quot;\u0026gt;\u0026lt;strong data-renderer-mark=\u0026quot;true\u0026quot;\u0026gt;Key Responsibilities:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-indent-level=\u0026quot;1\u0026quot;\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;2961\u0026quot;\u0026gt;Develop and optimize power conversion circuits, including \u0026lt;span data-highlighted=\u0026quot;true\u0026quot; data-vc=\u0026quot;highlighted-text\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;_kqswh2mm\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;_5pioz8co _189eyh40 _1il9buyh _19lcevot _d0altlke\u0026quot; data-testid=\u0026quot;definition-highlighter\u0026quot;\u0026gt;DC-DC\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt; converters, voltage regulators, and power modules.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;3079\u0026quot;\u0026gt;Design and optimize power delivery for ASICs, ensuring stable voltage and current distribution across the board. Address power integrity challenges such as voltage ripple, noise, and impedance mismatches.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;3287\u0026quot;\u0026gt;Develop and implement board-level designs, to meet electrical and mechanical requirements with a deep understanding of \u0026lt;span data-highlighted=\u0026quot;true\u0026quot; data-vc=\u0026quot;highlighted-text\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;_kqswh2mm\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;_5pioz8co _189eyh40 _1il9buyh _19lcevot _d0altlke\u0026quot; data-testid=\u0026quot;definition-highlighter\u0026quot;\u0026gt;PCB\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt; layout rules and constraints.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;3443\u0026quot;\u0026gt;Implement thermal solutions to maintain optimal operating temperatures for components.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;3533\u0026quot;\u0026gt;Evaluate and select appropriate power components, such as voltage regulators, capacitors, and inductors, ensuring they meet performance, thermal, and reliability specifications. Also will be asked to do the same evaluation on overall system level design components.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;3802\u0026quot;\u0026gt;Work closely with component vendors to identify and source the best power solutions, ensuring compatibility with our \u0026lt;span data-highlighted=\u0026quot;true\u0026quot; data-vc=\u0026quot;highlighted-text\u0026quot;\u0026gt;ASIC\u0026lt;/span\u0026gt; designs and meeting quality standards.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;3966\u0026quot;\u0026gt;Work closely with cross-functional teams, including firmware, mechanical, and validation engineers, to integrate designs into complete systems.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;4113\u0026quot;\u0026gt;Generate and maintain comprehensive design documentation, including, Specifications, schematics and BOMs.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;4222\u0026quot;\u0026gt;Conduct thorough debugging and analysis of power-related or system level issue utilizing lab equipment such as oscilloscopes and power analyzers to identify and resolve problems.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;4404\u0026quot;\u0026gt;\u0026lt;strong data-renderer-mark=\u0026quot;true\u0026quot;\u0026gt;Qualifications:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-indent-level=\u0026quot;1\u0026quot;\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;4423\u0026quot;\u0026gt;\u0026lt;strong data-renderer-mark=\u0026quot;true\u0026quot;\u0026gt;Education:\u0026lt;/strong\u0026gt; Bachelor’s or Master’s degree in electrical engineering or a related field.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;4513\u0026quot;\u0026gt;\u0026lt;strong data-renderer-mark=\u0026quot;true\u0026quot;\u0026gt;Experience:\u0026lt;/strong\u0026gt; 8-10 years of experience in power and board design engineering, with a focus on \u0026lt;span data-highlighted=\u0026quot;true\u0026quot; data-vc=\u0026quot;highlighted-text\u0026quot;\u0026gt;ASIC\u0026lt;/span\u0026gt; or high-speed digital designs.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;4644\u0026quot;\u0026gt;\u0026lt;strong data-renderer-mark=\u0026quot;true\u0026quot;\u0026gt;Technical Skills:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-indent-level=\u0026quot;2\u0026quot;\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;4665\u0026quot;\u0026gt;Proficiency in Cadence \u0026lt;span data-highlighted=\u0026quot;true\u0026quot; data-vc=\u0026quot;highlighted-text\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;_kqswh2mm\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;_5pioz8co _189eyh40 _1il9buyh _19lcevot _d0altlke\u0026quot; data-testid=\u0026quot;definition-highlighter\u0026quot;\u0026gt;OrCAD\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt; and Allegro for schematic capture and \u0026lt;span data-highlighted=\u0026quot;true\u0026quot; data-vc=\u0026quot;highlighted-text\u0026quot;\u0026gt;PCB\u0026lt;/span\u0026gt; layout.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;4747\u0026quot;\u0026gt;Strong understanding of power integrity principles and techniques.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;4817\u0026quot;\u0026gt;Experience with power component selection and vendor collaboration.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;4888\u0026quot;\u0026gt;Hands-on experience with debugging power-related issues using lab equipment.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;4970\u0026quot;\u0026gt;\u0026lt;strong data-renderer-mark=\u0026quot;true\u0026quot;\u0026gt;Soft Skills:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-indent-level=\u0026quot;2\u0026quot;\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;4986\u0026quot;\u0026gt;Excellent problem-solving and analytical skills.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;5038\u0026quot;\u0026gt;Strong communication and teamwork abilities.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;5086\u0026quot;\u0026gt;Ability to work in a fast-paced, collaborative environment.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;5151\u0026quot;\u0026gt;\u0026lt;strong data-renderer-mark=\u0026quot;true\u0026quot;\u0026gt;Preferred Qualifications:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-indent-level=\u0026quot;1\u0026quot;\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;5180\u0026quot;\u0026gt;Experience with high-speed interfaces such as PCIe, \u0026lt;span data-highlighted=\u0026quot;true\u0026quot; data-vc=\u0026quot;highlighted-text\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;_kqswh2mm\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;_5pioz8co _189eyh40 _1il9buyh _19lcevot _d0altlke\u0026quot; data-testid=\u0026quot;definition-highlighter\u0026quot;\u0026gt;DDR\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;, and USB.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;5249\u0026quot;\u0026gt;Familiarity with electromagnetic interference (\u0026lt;span data-highlighted=\u0026quot;true\u0026quot; data-vc=\u0026quot;highlighted-text\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;_kqswh2mm\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;_5pioz8co _189eyh40 _1il9buyh _19lcevot _d0altlke\u0026quot; data-testid=\u0026quot;definition-highlighter\u0026quot;\u0026gt;EMI\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;) and electromagnetic compatibility (\u0026lt;span data-highlighted=\u0026quot;true\u0026quot; data-vc=\u0026quot;highlighted-text\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;_kqswh2mm\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;_5pioz8co _189eyh40 _1il9buyh _19lcevot _d0altlke\u0026quot; data-testid=\u0026quot;definition-highlighter\u0026quot;\u0026gt;EMC\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;) considerations.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;5360\u0026quot;\u0026gt;Familiarity with Design for Manufacturability (DFM) considerations.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;5431\u0026quot;\u0026gt;Experience in thermal management and reliability analysis.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;5493\u0026quot;\u0026gt;\u0026lt;strong data-renderer-mark=\u0026quot;true\u0026quot;\u0026gt;Why Join Us:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul class=\u0026quot;ak-ul\u0026quot; data-indent-level=\u0026quot;1\u0026quot;\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;5509\u0026quot;\u0026gt;Work on cutting-edge \u0026lt;span data-highlighted=\u0026quot;true\u0026quot; data-vc=\u0026quot;highlighted-text\u0026quot;\u0026gt;ASIC\u0026lt;/span\u0026gt; designs in a collaborative and innovative environment.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;5593\u0026quot;\u0026gt;Opportunity to influence power design strategies and contribute to product success.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;5680\u0026quot;\u0026gt;Access to state-of-the-art tools and resources to enhance your skills and career growth.\u0026lt;/p\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;5772\u0026quot;\u0026gt;If you are passionate about power and board design engineering and meet the qualifications outlined above, we encourage you to apply and become a key contributor to our team.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Base pay range for this role is $209,000 - $230,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. \u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025526005,"name":"Hardware Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4690430005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4433012005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Product Applications Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4690430005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2490","title":"Principal Product Application Engineer - Leo","company_name":"Astera Labs","first_published":"2026-04-29T13:45:01-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;About the Role\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As a Principal Product Applications Engineer on the Leo team, you will sit at the intersection of firmware engineering and customer-facing technical engagement. You will be a key technical resource for enabling Leo CXL Smart Memory Controllers at hyperscale customers and OEM partners — owning firmware bring-up, validation, and customer issue resolution from early silicon through production ramp.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Firmware is considered equally important to hardware at Astera Labs, and this role reflects that. You will work directly with customers to ensure their needs are fully understood and translated into firmware solutions, while collaborating closely with the internal firmware, hardware, and systems engineering teams.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This position is required onsite in San Jose, CA.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Lead firmware-focused customer engagements for Leo CXL Smart Memory Controllers, including bring-up support, feature enablement, and issue triage on customer platforms\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop, validate, and debug firmware using \u0026lt;strong\u0026gt;C\u0026lt;/strong\u0026gt; and \u0026lt;strong\u0026gt;Python\u0026lt;/strong\u0026gt; across Leo\u0026#39;s PCIe/CXL and DDR memory subsystems\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Spearhead internal and external discussions on design requirements of \u0026lt;strong\u0026gt;DDR4/DDR5 DRAM interfaces\u0026lt;/strong\u0026gt;, including initialization, training, RAS (Reliability, Availability, Serviceability) features, and performance tuning\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Serve as the primary firmware technical point of contact for key customer accounts (hyperscalers, OEMs), driving issue resolution and feature demonstrations\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Interpret and implement requirements from CXL, PCIe, and JEDEC DDR specifications into robust firmware solutions\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with cross-functional teams (FW engineering, HW, systems, product management) to deliver firmware releases and customer collateral on schedule\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop and maintain Python-based test scripts, automation frameworks, and diagnostic tools to support validation and customer debug workflows\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Contribute to technical documentation including application notes, release notes, design guides, and customer-facing collateral\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Represent the Leo team in customer technical reviews, design-in engagements, and industry forums\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, Computer Science, or a related technical field; Master\u0026#39;s degree preferred\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;8+ years\u0026lt;/strong\u0026gt; of experience in firmware development, product applications engineering, or a related technical role supporting complex SoC/silicon products for Server, Storage, and/or Networking applications\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Professional attitude with the ability to prioritize a dynamic list of tasks and work with minimal guidance\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Entrepreneurial, open-minded behavior and can-do attitude — think and act fast with the customer in mind!\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Authorized to work in the US and available to start immediately\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;High proficiency in C\u0026lt;/strong\u0026gt; for embedded firmware development in RTOS environments\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Working knowledge of \u0026lt;strong\u0026gt;CXL (Compute Express Link)\u0026lt;/strong\u0026gt; — CXL 1.1/2.0/3.0 — including memory expansion, pooling, and sharing concepts\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Proficiency in Python\u0026lt;/strong\u0026gt; for scripting, test automation, and diagnostic tooling\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep hands-on knowledge of \u0026lt;strong\u0026gt;high-speed memory interfaces\u0026lt;/strong\u0026gt; — DDR4 and/or DDR5 DRAM — including initialization sequences, training algorithms, timing margins, and ECC/RAS features\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with firmware bring-up, debug, and validation of memory or I/O subsystems on server platforms\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong debugging skills with the ability to triage and root-cause issues in complex embedded systems\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with SoC interfaces including DDR controllers, PCIe controllers, and on-chip memory subsystems\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience working with developer workflows: SCM (preferably Git), code reviews, CI/CD pipelines\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience with \u0026lt;strong\u0026gt;PCIe\u0026lt;/strong\u0026gt; endpoint firmware at the PHY, Link, and Transaction layers; familiarity with PCIe enumeration, MSI/MSI-X, SR-IOV, and error handling\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience with PCIe/CXL protocol analyzers, BERT, and other lab debug equipment\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with BIOS/BMC/OS interactions with PCIe/CXL devices and MMIO/RAS concepts\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with server memory performance tuning — latency and bandwidth optimization\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Prior customer-facing or field applications experience in a semiconductor or systems company is a strong plus\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Compensation\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;The base salary range for this role is \u0026lt;strong\u0026gt;$175,000 – $230,000 USD\u0026lt;/strong\u0026gt;. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;em\u0026gt;Astera Labs is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.\u0026lt;/em\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4000702005,"name":"Product Applications","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4697866005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4436935005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose (HQ)","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Product Applications Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4697866005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2570","title":"Principal Product Application Engineer - PCIe","company_name":"Astera Labs","first_published":"2026-05-20T14:23:14-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is seeking a Principal Product Applications Engineer to join our Aries PCIe Retimer team and serve as a critical technical bridge between our customers and engineering organization. As AI infrastructure demands explode, our Aries Smart Retimers are enabling the high-speed, low-latency PCIe connectivity that powers the world\u0026#39;s most advanced data centers—and you\u0026#39;ll be at the center of that growth.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;In this high-impact role, you\u0026#39;ll work directly with hyperscalers, OEMs, and system builders to drive successful adoption of our Aries PCIe products. You\u0026#39;ll combine deep technical expertise with customer-facing skills to solve complex system-level challenges, create compelling technical documentation, and influence product direction based on real-world customer needs. This is an opportunity to shape how next-generation AI and cloud infrastructure connects and scales.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;You\u0026#39;ll collaborate cross-functionally with design engineering, validation, sales, and marketing teams while building strong relationships with customers who are defining the future of computing. If you thrive at the intersection of cutting-edge silicon and customer success, this role offers exceptional visibility and impact.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Customer Technical Engagement\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Serve as the primary technical resource for customers during pre-sales evaluation and post-sales deployment of Aries PCIe retimers\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deliver technical presentations, product training, and demonstrations to customer engineering teams\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Build trusted advisor relationships with key accounts and drive product adoption\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;System-Level Debug \u0026amp;amp; Validation Support\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Lead root cause analysis and debugging of complex PCIe signal integrity and protocol issues in customer systems\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support customer lab bring-up, characterization, and validation activities\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop and execute test plans to reproduce and resolve customer-reported issues\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Technical Documentation \u0026amp;amp; Enablement\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Create application notes, reference designs, and best practices guides for PCIe system implementation\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop collateral that accelerates customer time-to-deployment\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Contribute to product documentation including datasheets and user guides\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional Collaboration\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Partner with product management and engineering to translate customer feedback into product requirements\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support sales teams with technical expertise during customer engagements\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Represent the voice of the customer in internal roadmap and feature discussions\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, Computer Engineering, or related field\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;8+ years of experience in applications engineering, technical support, or system engineering roles\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of PCIe architecture, protocol, and electrical specifications (Gen4/Gen5/Gen6)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience with lab equipment including oscilloscopes, protocol analyzers, and BERT tools\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience debugging high-speed serial interfaces at both the physical and protocol layers\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent written and verbal communication skills with ability to explain complex technical concepts\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop and modify firmware using C to implement features, optimize performance, and resolve technical issues\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Travel to customer sites worldwide to provide on-site technical support, conduct system integration, and drive issue resolution\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience with PCIe retimers, redrivers, or similar connectivity components\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with server, storage, or GPU system architectures\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Background in signal integrity analysis and simulation tools\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Scripting proficiency (Python, TCL) for test automation and data analysis\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Prior experience working directly with hyperscale or enterprise data center customers\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Track record of creating high-quality technical documentation and application notes\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Salary range is $170,500 to $220,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4000702005,"name":"Product Applications","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4689274005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4408914005,"location":{"name":"Taipei, Taiwan"},"metadata":[{"id":12122734005,"name":"Country","value":"Taiwan","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Taipei","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Product Applications Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4689274005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2161","title":"Principal Product Applications Engineer","company_name":"Astera Labs","first_published":"2026-04-27T12:28:19-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Job Description:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As an Astera Labs Principal Product Application Engineer, you will need to provide technical guidance to ODMs to overcome design challenges, generate collateral for existing and new products, and drive innovation by providing insightful feedback to other internal teams to continuously improve products and processes. We need experience supporting the development and designing-in of semiconductor products for PCIe/CXL. There are opportunities to support key ODMs directly, and also to dive deep in the lab to address the challenges associated with leading edge semiconductor products.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, Master’s is preferred.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Minimum of 10 years’ experience designing in complex SoC/silicon products with a high speed (preferably PCIe) interface.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!\u0026lt;strong\u0026gt;\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Experience\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong working knowledge of PCIe LTSSM at a physical layer level, associated standards, and debug. Most recent experience with PCIe 4.0 at a minimum, some experience with 5.0/CXL preferred.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Silicon/System bring-up and debug experience in customer systems.\u0026amp;nbsp;\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Technical ownership of issue resolution: Driving and directing internal teams, and driving communication to customers through FAE and sales teams.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Firsthand experience with lab equipment such as protocol analyzers/exercisers, high-speed oscilloscopes, or BERTs.\u0026amp;nbsp;\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Technical writing skills to generate clear, precise documentation including application notes and similar guides for internal and customer-facing audiences.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Global customer engagement support, with travel as required for on-site activities, reviews, and system bring-up.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred experience\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Triaging complex customer reported issues which require taking into account multiple layers of conditions; for instance, silicon, firmware, hardware board design, and system environment.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Development/support for PCIe or Ethernet Switch or Retimer products.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;PCIe compliance testing methodology and troubleshooting.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Comfort working with software/firmware associated with semiconductor products, such as; Firmware development with C-language, scripting with Python or other equivalent programming languages.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Understanding of Data Center systems like Servers, JBOGs/JBODs, Networking switches/routers/interconnects etc.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4000702005,"name":"Product Applications","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4009035005,"name":"Taipei","location":"Taipei, Taiwan","child_ids":[],"parent_id":4002874005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4655275005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4416857005,"location":{"name":"Shanghai, China"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Product Applications Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4655275005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2258","title":"Principal Product Applications Engineer ","company_name":"Astera Labs","first_published":"2026-03-04T22:46:36-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of cloud and AI infrastructure. Our Intelligent Connectivity Platform integrates PCIe, CXL and Ethernet semiconductor-based solutions based on a software-defined architecture that is both scalable and customizable. Inspired by trusted partnerships with hyperscalers and the data center ecosystem, we are an innovation leader with products that are flexible, interoperable, and reliable. We are headquartered in the heart of California’s Silicon Valley, with R\u0026amp;amp;D centers and offices in Texas, Taiwan, China, Canada, and Israel.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As an Astera Labs Product Applications Engineer, you will be part of a team that supports design-in of Astera Labs’ portfolio of connectivity products by the world’s leading cloud service providers and server and network OEMs. In this role, you will need to provide technical guidance to customers to overcome design challenges, generate collateral for existing and new products, and drive innovation by providing insightful feedback to other internal teams to continuously improve products and processes. You will investigate and duplicate issues reported by customers, and drive critical issues to resolution. There are opportunities to support key customers directly, and also to dive deep in the lab to address the challenges associated with leading edge semiconductor products.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong academic and technical background in electrical, electronics, or computer engineering or a closely related field. At a minimum, an engineering bachelor’s degree is required. A master’s degree is preferred.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;A minimum of 12 years’ experience working with cloud service providers or server or network OEM customers to design in complex SoC/silicon products for server, storage, and/or networking applications.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Entrepreneurial spirit, open-minded approach, and can-do attitude. Think and act with the customer in mind!\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Silicon/system bring-up and debug experience in customer systems.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong knowledge of embedded FW development and in-system debug\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Firmware development with C-language, scripting with Python or other equivalent programming languages.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong knowledge of PCIe protocol, including LTSSM, EQ, DMA, etc.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong knowledge of NRZ/PAM4 SerDes level debugging (TX/RX Equalization) in PCIe, Ethernet (25G and above), etc.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Firsthand experience with lab equipment including traffic generators, analyzers, and high-speed oscilloscopes.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Broad knowledge of NRZ/PAM4 SerDes-based protocols such as PCIe or Ethernet (25G and above).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Understanding of Data Center systems such as servers, compute nodes, JBOGs/JBODs, and networking switches/routers/interconnects, etc.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Technical writing skills and the ability to generate clear, precise documentation including datasheets, application notes, and similar guides for both internal audiences and customers.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Broad knowledge of signal processing and ECC coding for communications\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Device driver development\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Development/support for PCIe or Ethernet switch products\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Working with silicon characterization/validation teams to ensure desired device performance is readily achievable in customer systems.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of simulation/modeling, schematic capture, and PCB layout tools from Cadence, Altium and others.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of simulation tools such as Keysight ADS, SiSoft QCD, and others, for IBIS-AMI analysis.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;A strong background in high-speed board design and techniques for preserving signal integrity.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4000702005,"name":"Product Applications","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4002878005,"name":"Shanghai","location":"Shanghai, China","child_ids":[],"parent_id":4002875005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4697283005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4436728005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose (HQ)","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Product Applications Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4697283005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2561","title":"Principal Product Applications Engineer - Ethernet","company_name":"Astera Labs","first_published":"2026-05-20T10:00:29-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is seeking a Principal Product Applications Engineer to join our Taurus Ethernet Smart Cable Modules team and drive customer success at the forefront of AI infrastructure connectivity. As data centers scale to meet explosive AI workload demands, our Taurus products are enabling the high-bandwidth, low-latency Ethernet fabric connections that power next-generation GPU clusters and disaggregated computing architectures.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;In this role, you\u0026#39;ll be the technical expert customers rely on to successfully deploy Taurus Ethernet solutions in their most demanding environments. You\u0026#39;ll work hands-on with hyperscalers, OEMs, and AI system builders to debug complex physical layer challenges, deliver technical enablement, and ensure seamless product integration. Your customer insights will directly influence how we evolve our products to meet the market\u0026#39;s most pressing connectivity needs.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This is a unique opportunity to combine deep Ethernet and physical layer expertise with meaningful customer impact at a hyper-growth company defining the future of AI connectivity. You\u0026#39;ll collaborate across engineering, sales, and product teams while building relationships with the world\u0026#39;s most innovative technology companies.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Customer Technical Engagement\u0026lt;/strong\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Serve as the primary technical resource for customers evaluating and deploying Taurus Ethernet Smart Cable Modules\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deliver technical presentations, product training, and hands-on demonstrations to customer engineering teams\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Build trusted relationships with key accounts and drive successful product adoption\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;System-Level Debug \u0026amp;amp; Validation Support\u0026lt;/strong\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Lead root cause analysis and debugging of complex Ethernet physical layer and link issues in customer systems\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support customer lab bring-up, characterization, and system validation activities\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop and execute test plans to reproduce and resolve customer-reported issues\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Technical Documentation \u0026amp;amp; Enablement\u0026lt;/strong\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Create application notes, integration guides, and best practices documentation for Ethernet system implementation\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop technical collateral that accelerates customer time-to-deployment\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Contribute to product documentation including datasheets and user guides\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional Collaboration\u0026lt;/strong\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Partner with product management and engineering to translate customer feedback into product requirements\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support sales teams with technical expertise during pre-sales and post-sales engagements\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Represent voice of the customer in internal roadmap discussions and feature prioritization\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Willingness to travel for work within US and to Asia.\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, Computer Engineering, or related field\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;8+ years of experience in applications engineering, technical support, or system engineering roles\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of Ethernet physical layer specifications (100G/200G/400G/800G)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience with lab equipment including oscilloscopes, protocol analyzers, and BER test tools\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience debugging high-speed serial interfaces and signal integrity challenges\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent written and verbal communication skills with ability to convey complex technical concepts\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience with optical modules, active cables, or similar high-speed connectivity components\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with AI/ML system architectures, GPU clusters, or data center networking\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Background in signal integrity analysis and simulation\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Scripting proficiency (Python, TCL) for test automation and data analysis\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Prior experience working with hyperscale or enterprise data center customers\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of Ethernet consortium specifications and industry standards\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Salary range is $158,400 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4000702005,"name":"Product Applications","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4602854005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4391785005,"location":{"name":"San Jose, CA"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Product Management","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4602854005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"1919","title":"Principal Product Manager - Ethernet","company_name":"Astera Labs","first_published":"2025-10-24T19:00:08-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Are you passionate about creating differentiated products and working with hyperscale and AI platform providers to deploy the next generation of data center infrastructure? \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;We are seeking a highly technical and experienced product manager to join our team at Astera Labs. As a key member of our product management team, you will work closely with customers, product marketing, engineering and other internal cross-functional teams to define and deliver competitive silicon, hardware and software solutions.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;This is a unique opportunity to play a pivotal role in the success of our Taurus Ethernet Retimer portfolio. We are scaling our Taurus product management team to support our worldwide customers, offering ample opportunities for growth and advancement within the product team.\u0026amp;nbsp;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Based in San Jose, this position requires an in-person presence with travel to customers. \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Own product definition: \u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Define detailed product requirements and prioritize features, enhancements, and bug fixes based on business goals and customer feedback. \u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Lead product planning:\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Work closely with product marketing to translate product strategy into executable product plans and collaborate with Astera Labs cross-functional teams to drive products from ideation to launch. \u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Lead customer technical engagement:\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Work closely with lighthouse customers to translate their needs to competitive product requirements and secure new design wins throughout the product lifecycle. \u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Support go-to-market:\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Leverage technical and product expertise to support product marketing and corporate marketing teams on go-to-market planning and execution, sales enablement, competitive analysis, and product positioning. \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Qualifications\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Deep understanding of high-speed protocols (Ethernet is required; UAL, PCIe, CXL, and other protocols are a plus) and system architectures used in cloud and AI infrastructure \u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;10+ years of experience in product management, applications engineering or other technical product roles within the semiconductor industry\u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;Proven track record of defining and launching successful semiconductor products\u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;Strong strategic thinking and analytical skills, with the ability to translate customer pain points into competitive products \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;Excellent communication skills with the ability to articulate complex technical concepts in a clear and compelling manner \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;Proven ability to collaborate effectively with cross-functional teams and drive consensus in a fast-paced, dynamic environment \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;Experience working with customers and partners to understand their needs and drive product definition \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;5\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;Willingness to travel as needed for customer meetings, industry events, and trade shows \u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4000198005,"name":"Product Management","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4678070005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4427171005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Product Management","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4678070005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2416","title":"Principal Product Manager - Smart Cable Modules","company_name":"Astera Labs","first_published":"2026-03-26T17:39:46-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Principal Product Manager – Smart Cable Modules\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:240,\u0026amp;quot;335559739\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Astera Labs is at the center of the AI infrastructure revolution, and our Smart Cable Modules are critical to enabling the high-bandwidth, low-latency connectivity that next-generation data centers demand.\u0026amp;nbsp;We\u0026#39;re\u0026amp;nbsp;looking for a Principal Product Manager to own and drive this exciting product portfolio—working directly with\u0026amp;nbsp;hyperscalers\u0026amp;nbsp;and AI platform providers to define solutions that push the boundaries of\u0026amp;nbsp;what\u0026#39;s\u0026amp;nbsp;possible.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:240,\u0026amp;quot;335559739\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;In this role,\u0026amp;nbsp;you\u0026#39;ll\u0026amp;nbsp;be the connective tissue between our customers, engineering teams, and go-to-market functions.\u0026amp;nbsp;You\u0026#39;ll\u0026amp;nbsp;translate complex customer requirements into differentiated products, guide development from concept through launch, and help secure design wins with the world\u0026#39;s most demanding infrastructure builders. This is a high-visibility, high-impact opportunity to shape products that will power the future of AI and cloud computing.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:240,\u0026amp;quot;335559739\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Based in San Jose, this position requires an in-person presence with regular travel to customers.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:240,\u0026amp;quot;335559739\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:240,\u0026amp;quot;335559739\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;14\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:0,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Product Definition \u0026amp;amp; Strategy\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:240,\u0026amp;quot;335559739\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Define detailed product requirements for Smart Cable Modules, prioritizing features, enhancements, and bug fixes based on business goals and customer feedback\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Translate market trends and customer insights into a compelling product roadmap\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Drive competitive differentiation through deep understanding of PCIe, Ethernet, and system architectures\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;14\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:0,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Customer Engagement \u0026amp;amp; Design Wins\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:240,\u0026amp;quot;335559739\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Serve as the primary technical product interface with lighthouse customers, translating their needs into actionable product requirements\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Secure and support\u0026amp;nbsp;new design\u0026amp;nbsp;wins throughout the product lifecycle\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Build strong relationships with\u0026amp;nbsp;hyperscalers\u0026amp;nbsp;and AI platform providers to ensure Astera Labs\u0026amp;nbsp;remains\u0026amp;nbsp;their connectivity partner of choice\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;14\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559683\u0026amp;quot;:0,\u0026amp;quot;335559684\u0026amp;quot;:-2,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;hybridMultilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Cross-Functional Leadership\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:240,\u0026amp;quot;335559739\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Collaborate with engineering to drive products from ideation through launch, ensuring on-time delivery of competitive solutions\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Partner with product marketing on go-to-market planning, sales enablement, competitive analysis, and product positioning\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Work across Astera Labs functions to align priorities and drive consensus in a fast-paced environment\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Basic Qualifications\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:240,\u0026amp;quot;335559739\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, Computer Science, or related technical field\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;8+ years of experience in product management, applications engineering, or technical product roles within the semiconductor industry\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Deep understanding of high-speed protocols (PCIe, Ethernet, CXL) and system architectures used in cloud and AI infrastructure\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Proven\u0026amp;nbsp;track record\u0026amp;nbsp;of defining and launching successful semiconductor products\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Strong communication\u0026amp;nbsp;skills with the ability to articulate complex technical concepts to both technical and business audiences\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Willingness to travel for customer meetings, industry events, and trade shows\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Preferred Qualifications\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:240,\u0026amp;quot;335559739\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Master\u0026#39;s degree in Electrical Engineering, Computer Science, or related field\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience working directly with\u0026amp;nbsp;hyperscalers\u0026amp;nbsp;or large cloud infrastructure providers\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Background in cable modules,\u0026amp;nbsp;retimers, or high-speed connectivity products\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience driving products through full lifecycle from concept to high-volume production\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Strong strategic thinking and analytical skills with ability to translate customer pain points into competitive products\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:0}\u0026quot;\u0026gt;Experience speaking Mandarin\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Salary range is $158,400 to $220,000 depending on experience, level, and business\u0026amp;nbsp;need. This role may be eligible for discretionary\u0026amp;nbsp;bonus,\u0026amp;nbsp;incentives\u0026amp;nbsp;and benefits.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335551550\u0026amp;quot;:0,\u0026amp;quot;335551620\u0026amp;quot;:0,\u0026amp;quot;335559738\u0026amp;quot;:240,\u0026amp;quot;335559739\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4000198005,"name":"Product Management","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4688304005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4432042005,"location":{"name":"Aachen, North Rhine-Westphalia, Germany"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Quality Assurance","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4688304005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2480","title":"Principal Quality Engineer","company_name":"Astera Labs","first_published":"2026-04-23T13:42:03-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Principal Quality Engineer\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Role Summary\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;As Principal Quality Engineer based in Aachen, you are the technical authority\u0026amp;nbsp;for\u0026amp;nbsp;quality across our optical product line and regional quality lead for European operations. You will bridge HQ (San Jose) and the Aachen manufacturing site, drive quality integration for in-house optical manufacturing, lead supplier quality for regional semiconductor and optical vendors, and support Asia-based RMA activities for in-region products.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Quality\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;‑\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;System Integration:\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026amp;nbsp;Lead ISO 9001 alignment between San Jose HQ,\u0026amp;nbsp;Aachen,\u0026amp;nbsp;and other regional locations to\u0026amp;nbsp;harmonize\u0026amp;nbsp;procedures, audit schedules, and corrective action processes across both semiconductor and optical product lines.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Process Development \u0026amp;amp; Implementation:\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026amp;nbsp;Design, document, and roll out new quality processes, procedures, and work instructions needed to support emerging\u0026amp;nbsp;photonics\u0026amp;nbsp;products and manufacturing capabilities.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;In\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;‑\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Process Inspection \u0026amp;amp; Controls:\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026amp;nbsp;Oversee in\u0026lt;/span\u0026gt;‑\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;process inspection activities for the in\u0026lt;/span\u0026gt;‑\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;house manufacturing operation, establishing SPC, go/no\u0026lt;/span\u0026gt;‑\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;go checkpoints, and real\u0026lt;/span\u0026gt;‑\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;time defect\u0026lt;/span\u0026gt;‑\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;tracking dashboards.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Supplier Quality\u0026amp;nbsp;(Optics):\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Provide technical support and quality assurance for optical\u0026lt;/span\u0026gt;‑\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;component and optical\u0026lt;/span\u0026gt;‑\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;coating suppliers; conduct supplier audits, and drive corrective\u0026lt;/span\u0026gt;‑\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;preventive actions (CAPA).\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Supplier Quality\u0026amp;nbsp;(Semiconductor):\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Serve as the regional point of contact for semiconductor suppliers, monitoring supplier performance,\u0026amp;nbsp;assisting with supplier audits,\u0026amp;nbsp;and leading issue resolution.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Product Quality:\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026amp;nbsp;Core Semiconductor Business –\u0026amp;nbsp;Lead technical investigation of field returns, warranty claims, and reliability failures for semiconductor and optical products; coordinate 8D root-cause analysis and interface with Field Application Engineers (FAEs).\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Cross\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;‑\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Site Liaison:\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026amp;nbsp;Act as the primary conduit between the Aachen site, other European/EMEA sites, and the San\u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; \u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Jose HQ for quality information exchange, escalation handling, and best\u0026lt;/span\u0026gt;‑\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;practice sharing.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Metrics \u0026amp;amp; Reporting:\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026amp;nbsp;Define, track, and report key quality KPIs (PPM, DPMO, warranty cost, MTBF, supplier defect rate, etc.) to senior leadership across the BU and corporate HQ.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Quality Improvement:\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026amp;nbsp;Lead\u0026amp;nbsp;and demonstrate\u0026amp;nbsp;the application of advanced quality improvement techniques including\u0026amp;nbsp;Lean,\u0026amp;nbsp;Six\u0026lt;/span\u0026gt;‑\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Sigma,\u0026amp;nbsp;and\u0026amp;nbsp;other methods to\u0026amp;nbsp;reduce waste, improve yield, and enhance overall product reliability.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Education \u0026amp;amp; Experience\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;table data-tablestyle=\u0026quot;MsoNormalTable\u0026quot; data-tablelook=\u0026quot;1184\u0026quot;\u0026gt;\n\u0026lt;tbody\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td data-celllook=\u0026quot;0\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Required\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td data-celllook=\u0026quot;0\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Preferred\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td data-celllook=\u0026quot;0\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;•\u0026amp;nbsp;Bachelor\u0026#39;s in Electrical Engineering, Materials Science, Physics, or related discipline\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td data-celllook=\u0026quot;0\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;• Master\u0026#39;s or PhD in Engineering\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td data-celllook=\u0026quot;0\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;• 10+ years in quality engineering with progression to senior/principal level\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td data-celllook=\u0026quot;0\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;• 15+ years with demonstrated leadership in multi-site organizations\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td data-celllook=\u0026quot;0\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;• Minimum 5 years in semiconductor, photonics, or precision optics manufacturing\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td data-celllook=\u0026quot;0\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;• Direct experience with optical module qualification (Telcordia GR-468)\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;/tbody\u0026gt;\n\u0026lt;/table\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Technical Skills\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;table data-tablestyle=\u0026quot;MsoNormalTable\u0026quot; data-tablelook=\u0026quot;1184\u0026quot;\u0026gt;\n\u0026lt;tbody\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td data-celllook=\u0026quot;0\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Required\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td data-celllook=\u0026quot;0\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Preferred\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td data-celllook=\u0026quot;0\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;• Expert-level ISO 9001 implementation and multi-site QMS integration\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td data-celllook=\u0026quot;0\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;• Six Sigma Black Belt, ASQ CQE/CQM, or Lean certification\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td data-celllook=\u0026quot;0\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;• Advanced statistical methods: SPC, DOE, MSA, FMEA (Design \u0026amp;amp; Process)\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td data-celllook=\u0026quot;0\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;• Proficiency in Minitab, JMP, Python, or R for data analysis\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td data-celllook=\u0026quot;0\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;• Supplier quality management including audits, scorecards, CAPA/SCAR\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td data-celllook=\u0026quot;0\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;• Familiarity with JEDEC, IPC, Telcordia\u0026amp;nbsp;reliability standards\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td data-celllook=\u0026quot;0\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;• Experience with optical metrology (interferometry, power meters, spectrometers, alignment systems)\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td data-celllook=\u0026quot;0\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;• Industry 4.0 quality tools (AI-based defect\u0026amp;nbsp;detection, digital twin, automated optical inspection)\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;/tbody\u0026gt;\n\u0026lt;/table\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Core Competencies\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;table data-tablestyle=\u0026quot;MsoNormalTable\u0026quot; data-tablelook=\u0026quot;1184\u0026quot;\u0026gt;\n\u0026lt;tbody\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td data-celllook=\u0026quot;0\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Required\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td data-celllook=\u0026quot;0\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Preferred\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td data-celllook=\u0026quot;0\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;•\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Fluency in English and German\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026amp;nbsp;(written and spoken)\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td data-celllook=\u0026quot;0\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;• Additional European language\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td data-celllook=\u0026quot;0\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;• Strong cross-functional leadership and influence without authority\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td data-celllook=\u0026quot;0\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;• Experience managing quality engineers or cross-site teams\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td data-celllook=\u0026quot;0\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;• Excellent technical communication to engineering and executive audiences\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td data-celllook=\u0026quot;0\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;• Track record presenting to C-level stakeholders\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td data-celllook=\u0026quot;0\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;• Comfort with ambiguity in fast-paced, high-growth environments\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td data-celllook=\u0026quot;0\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;• Experience in startup or rapid-scale environments\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td data-celllook=\u0026quot;0\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;• Willingness to travel (up to 20–25%, including Asia and North America)\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td data-celllook=\u0026quot;0\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;• Existing relationships with European optical/semiconductor supply base\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;/tbody\u0026gt;\n\u0026lt;/table\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;Compensation\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. You will also be eligible for equity and benefits. Astera Labs is committed to fair and equitable pay practices.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;em\u0026gt;Astera Labs is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.\u0026lt;/em\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4011733005,"name":"Quality","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4056756005,"name":"Aachen","location":"Aachen, Germany","child_ids":[],"parent_id":4056755005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4666076005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4421635005,"location":{"name":"San Jose, CA "},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Hardware Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4666076005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2312","title":"Principal Signal and Power Integrity Engineer ","company_name":"Astera Labs","first_published":"2026-02-25T19:31:49-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;At Astera Labs, we seek motivated \u0026lt;strong\u0026gt;Principal Signal and Power Integrity Engineers \u0026lt;/strong\u0026gt;to work on our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role, you will execute the SI planning, design, modeling, simulation, and lab validation with various system configurations. This position will be onsite.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong academic/technical background in electrical engineering; Bachelor’s is required; Master’s preferred.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;8+ years of experience supporting or developing complex SoC/silicon products for Server and Networking applications.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;8+ years of hands-on high-speed SI/PI design, simulation, and measurement experience.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Have a proven track record with defining hardware system constraints and high-speed technology roadmaps.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Cross-functional design mentality with the electrical design community to develop systems.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Self-starting, professional, and hands-on work ethic that can execute intense research in a dynamic environment.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven track record solving problems independently, preferably as a tech lead.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Entrepreneurial, open-minded behavior, and can-do attitude.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Authorized to work in the US and start immediately.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Familiar with SI and PI design challenges for PCIe Gen5/6 and/or 224/448G Ethernet PCB and interconnects\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;2D and 3D EM simulation experience with Cadence/Ansys/ADS/etc. toolsets\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;EM modeling of BGA and connector structures\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;High-speed SERDES channel simulation, and equalization\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;PI simulations with Ansys/Cadence toolsets\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiar with VNA, TDR, real-time and sub-sampling oscilloscopes, etc.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Working knowledge of PCB fabrication limits and trade-offs\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiar with industry-standard such as PCI-SIG, and IEEE802.3, especially Electrical sections.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong debugging, analysis, and problem-solving skills with experience leading root cause and correction action teams. An inherent sense of urgency and accountability. Must have the ability to multi-task in a fast-paced environment.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Your base salary will be determined based on your experience and the pay of employees in similar positions. The base salary range is $203,000 USD - $230,000 USD for Principal level, and $237,500 USD - $250,000 USD for Senior Principal level. The actual level is to be determined by the years of experience and interview outcome.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025526005,"name":"Hardware Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4613831005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4397108005,"location":{"name":"San Jose, CA"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Hardware Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4613831005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2047","title":"Principal Silicon Validation Engineer","company_name":"Astera Labs","first_published":"2025-12-23T13:03:15-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p data-start=\u0026quot;145\u0026quot; data-end=\u0026quot;476\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Overview:\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p data-start=\u0026quot;145\u0026quot; data-end=\u0026quot;476\u0026quot;\u0026gt;The mission of this role is to develop and execute electrical validation tests that quantify parametric device performance and operating margins across all system conditions. The validation team upholds customer requirements to the highest standard and serves as the final authority in certifying a product’s parametric compliance.\u0026lt;/p\u0026gt;\n\u0026lt;p data-start=\u0026quot;478\u0026quot; data-end=\u0026quot;1077\u0026quot;\u0026gt;Astera Labs is seeking motivated \u0026lt;strong data-start=\u0026quot;511\u0026quot; data-end=\u0026quot;568\u0026quot;\u0026gt;Principal / Senior Principal Post-Silicon Validation Engineers\u0026lt;/strong\u0026gt; to support our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role, you will define comprehensive post-silicon validation plans, automate IC- and board-level testing, and design experiments to identify and root-cause unexpected behavior. You will analyze and report validation results against specifications, collaborate closely with key internal stakeholders, quantify performance margins, and ensure robust, production-ready designs.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026amp;nbsp;Strong academic and technical background in Electrical or Computer Engineering. At minimum, a Bachelor’s is required, and a Master’s is preferred.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026amp;nbsp;≥10 years experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026amp;nbsp;Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for internal meetings in advance, and to work with minimal guidance and supervision.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven track record solving problems independently, preferably as a tech lead\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Required experience\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience working on debug and bring-up of complicated SoC’s with high-speed interfaces such as PCIe/802.3 Ethernet\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong problem-solving skills, ability to solve problems independently\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Basic knowledge of key, high-speed design blocks such as PLL’s, CTLE, DFE, Tx EQ, PAM4 signaling\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong python scripting and coding ability: knowledge of object-oriented programming and basic dev ops using git for source control and collaboration\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency using high-speed lab equipment such as BERT, Oscilloscope, and VNA\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Experience:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026amp;nbsp;Experience in system testing, characterization, margin analysis and optimization of high-speed, multi-gigabit data links over long and short channels\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026amp;nbsp;Familiarity with PCIe or Ethernet especially Electrical Compliance sections\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026amp;nbsp;Hands-on experience with signal integrity, especially as it relates to PCIe/Ethernet testing and CEM/NVMe interfaces\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026amp;nbsp;Working knowledge of C or C++ for embedded FW\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026amp;nbsp;Familiarity with IEEE 802.3x Ethernet standards and both NRZ and PAM-4 signaling\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026amp;nbsp;Working knowledge of common serial data specifications such as I2C, SPI, etc\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026amp;nbsp;Knowledge of schematic capture and PCB layout tools from Cadence, Altium, etc.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026amp;nbsp;Knowledge of simulation tools such as MATLAB, Keysight ADS, or PLTS for data analysis and modeling of electrical channel and signal integrity issues\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;The base salary range is USD 203,00 - USD 250,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025526005,"name":"Hardware Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4662564005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_optional","internal_job_id":4419978005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Hardware Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4662564005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2290","title":"Principal Silicon Validation Engineer, SerDes/PAM4","company_name":"Astera Labs","first_published":"2026-02-18T17:01:14-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Overview\u0026lt;br\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;br\u0026gt;The mission of this role is to develop and execute electrical validation tests to quantify parametric device performance and margins over all system conditions. The validation team holds customers’ requirements in the highest regard and is solely responsible for certifying a product’s parametric conformance to this high bar. At Astera Labs, we are looking for motivated\u0026amp;nbsp;\u0026lt;strong\u0026gt;Principal Silicon Validation Engineers\u0026amp;nbsp;\u0026lt;/strong\u0026gt;to work on our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role you will formulate a comprehensive post-Silicon validation plan, automate the testing of ICs and board products, design experiments to root-cause unexpected behavior, report results and specification compliance, and work with key internal customers to quantify margins and ensure robustness.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong academic and technical background in Electrical or Computer Engineering. At minimum, a Bachelor’s is required, and a Master’s is preferred.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;8 + years\u0026#39; experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for internal meetings in advance, and to work with minimal guidance and supervision.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven track record solving problems independently, executing validation plans for complex SoC designs.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Experience:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience leading SoC Debug and development for high-speed interfaces such as PCIe5, PCIe6 or PAM4 802.3 Ethernet.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with Electrical Compliance section of PCIe Base Spec and CEM Spec\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Working knowledge of key, high-speed design blocks such as PLL’s, DFE, Tx EQ, CDR, etc and concepts such as PAM4\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience in PRBS testing and optimization of high-speed PCIe data links over short, med, and long channels\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong python scripting ability: knowledge of object-oriented programming and basic dev ops using git for source control and collaboration\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep background in developing bench automation techniques, preferably using Python, with emphasis on execution efficiency, repeatability, and data analysis.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency using high-speed lab equipment such as BERT, Oscilloscope, and VNA\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Experience:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with PCIe/CXL compliance standards and ability to drive electrical compliance testing at industry workshops\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience with signal integrity, especially as it relates to PCIe testing, Channel Loss budgeting, and de-embedding\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with PCIe standards and both NRZ and PAM-4 signaling\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of simulation tools such as MATLAB, Keysight ADS, or PLTS for data analysis and modeling of electrical channel and signal integrity issues\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;The base salary range is $185,000 USD - $230,000 USD. Your base salary will be determined based on your experience and the pay of employees in similar positions.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025526005,"name":"Hardware Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4649978005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4414173005,"location":{"name":"Taipei, Taiwan"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Quality Assurance","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4649978005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2206","title":"Principal Supplier Quality Engineer","company_name":"Astera Labs","first_published":"2026-01-15T03:17:34-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;line-height: 1;\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;line-height: 1;\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Job Description:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;line-height: 1;\u0026quot;\u0026gt;We are seeking an experienced leader to drive Supplier / Manufacturing Quality Engineering to anchor our global supplier quality efforts across both Astera Lab’s semiconductor and board-level products. In this role, candidates will drive leading supplier quality across key manufacturing partners including IC fabs, OSAT’s, and PCB/PCBA vendors. A strong foundation in supplier quality engineering, uniquely paired with experience in advanced data analytics (including AI and machine learning) for predictive quality, risk assessments, and product quality analytics will be highly valuable to this role.\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;line-height: 1;\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Responsibilities:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;line-height: 1;\u0026quot;\u0026gt;Supplier Quality Management\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;line-height: 1;\u0026quot;\u0026gt;· Nurture winning partnerships across all our strategic manufacturing suppliers: semiconductor wafer fabs, advanced packaging \u0026amp;amp; test (OSAT), boards \u0026amp;amp; assemblies (PCB / PCBA / SMT), substrates / interposers, probe cards, and passive components.\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;line-height: 1;\u0026quot;\u0026gt;· Develop robust supplier selection and onboarding processes in collaboration with Design, Procurement, Business \u0026amp;amp; Engineering Operations teams.\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;line-height: 1;\u0026quot;\u0026gt;· Define, build, and manage the systems to collect the data (KPI’s) needed to track supplier performance and drive continuous improvement.\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;line-height: 1;\u0026quot;\u0026gt;· Audit to assess the effectiveness of supplier process controls, manufacturing capabilities, and overall quality management system.\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;line-height: 1;\u0026quot;\u0026gt;· Coach suppliers by sharing your deep manufacturing experience and knowledge.\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;line-height: 1;\u0026quot;\u0026gt;· International travel as needed, potentially on short notice. There is no minimum amount but prepare to accommodate up to 20%.\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;line-height: 1;\u0026quot;\u0026gt;Advanced Data Analytics \u0026amp;amp; AI/ML\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;line-height: 1;\u0026quot;\u0026gt;· Create data collection methods to enable product and supplier advanced data analytics needed for monolithic, chiplet, and board products. Data sources will include manufacturing inline controls, production test (including data collection from advanced embedded agents), and failure analysis activities.\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;line-height: 1;\u0026quot;\u0026gt;· Leverage data into quality models \u0026amp;amp; methods to predict product quality issues and supply chain risks.\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;line-height: 1;\u0026quot;\u0026gt;· Integrate AI/ML tools into quality systems and dashboards (e.g., outlier screening, automated defect detection, trend analysis, real-time alerts).\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;line-height: 1;\u0026quot;\u0026gt;· Experience with AI/ML tools is a plus but not required; ability to work with technical partners on model development is key.\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;line-height: 1;\u0026quot;\u0026gt;Cross-functional Collaboration\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;line-height: 1;\u0026quot;\u0026gt;· Interface with R\u0026amp;amp;D, NPI, product engineering, ops and other engineering teams to provide supplier input into product design and DFX.\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;line-height: 1;\u0026quot;\u0026gt;· Support early supplier involvement and ensure quality requirements needed for manufacturability \u0026amp;amp; testability are achieved, and learnings are propagated appropriately to other products in production \u0026amp;amp; development.\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;line-height: 1;\u0026quot;\u0026gt;· Represent supplier quality as needed in line failure reviews, excursion management, material reviews (MRB), and CAPA processes.\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;line-height: 1;\u0026quot;\u0026gt;· Partner with engineering and manufacturing teams to conduct quarterly engineering reviews, evaluate supplier changes (PCN), and assess supplier risks.\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;line-height: 1;\u0026quot;\u0026gt;· With engineering engagement, lead quality audits, and corrective action activities using tools such as 8D, 5-why, and FMEA.\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;line-height: 1;\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Education \u0026amp;amp; Experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;line-height: 1;\u0026quot;\u0026gt;· Bachelor’s or Master’s degree in Engineering or equivalent experience.\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;line-height: 1;\u0026quot;\u0026gt;· 8+ years of career progression in supplier quality engineering in the semiconductor and/or board-level electronics industry.\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;line-height: 1;\u0026quot;\u0026gt;· 3+ years direct experience working embedded within a high-volume advanced manufacturing operation in an engineering role.\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;line-height: 1;\u0026quot;\u0026gt;· Experience with supplier development in Asia with global manufacturing supply chains.\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;line-height: 1;\u0026quot;\u0026gt;· Six Sigma or ASQ certification a plus\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;line-height: 1;\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Technical Skills\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;line-height: 1;\u0026quot;\u0026gt;· Strong knowledge of IC fabrication, packaging (including chiplet), board assembly (SMT), and test processes.\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;line-height: 1;\u0026quot;\u0026gt;· Familiarity with reliability qualification methodologies in the application of IPC, Telcordia, JEDEC requirements.\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;line-height: 1;\u0026quot;\u0026gt;· Proficiency with quality engineering tools (FMEA, APQP, PPAP, SPC, OE, etc.).\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;line-height: 1;\u0026quot;\u0026gt;· Experience using analytics tools (e.g., JMP, SQL, Excel) to support quality insights. Exposure to AI/ML frameworks is a plus, but not required.\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;line-height: 1;\u0026quot;\u0026gt;· Fluent in English and Mandarin\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4011733005,"name":"Quality","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4009035005,"name":"Taipei","location":"Taipei, Taiwan","child_ids":[],"parent_id":4002874005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4637712005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4408383005,"location":{"name":"San Jose, CA"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Engineering Operations","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4637712005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2156","title":"Principal Test Engineer","company_name":"Astera Labs","first_published":"2025-12-19T14:25:25-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p data-renderer-start-pos=\u0026quot;26\u0026quot;\u0026gt;\u0026lt;strong data-renderer-mark=\u0026quot;true\u0026quot;\u0026gt;Job Description\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;43\u0026quot;\u0026gt;We are looking for Principal Test Engineers with proven experience in developing and supporting complex mixed-signal silicon SoC products to lead ATE Test solutions. The ideal candidate will develop and oversee SoC test strategy, interact with manufacturing partners, define, and implement ATE programs and own the product from design, initial samples all the way through high volume production ramp. The candidate should have working knowledge of communication/interface protocols such as PCI-Express (Gen-4/5/6), Ethernet, Infiniband, DDR, NVMe, USB, etc.\u0026lt;/p\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;574\u0026quot;\u0026gt;\u0026lt;strong data-renderer-mark=\u0026quot;true\u0026quot;\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;598\u0026quot;\u0026gt;Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, and a Master’s is preferred.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;742\u0026quot;\u0026gt;≥8-year experience releasing complex SoC/silicon products to high volume manufacturing.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;833\u0026quot;\u0026gt;Working knowledge of high-speed protocols like PCIe, Ethernet, Infiniband, DDR, NVMe, USB, etc.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;932\u0026quot;\u0026gt;Professional attitude with ability to execute on multiple tasks with minimal supervision.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;1025\u0026quot;\u0026gt;Strong team player with good communication skills to work alongside a team of high caliber engineers.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;1130\u0026quot;\u0026gt;Entrepreneurial, open-mind behavior and can-do attitude.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong data-renderer-mark=\u0026quot;true\u0026quot;\u0026gt;Required Experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;1213\u0026quot;\u0026gt;Hands-on experience with high-speed mixed signal SoC test program/hardware development on multiple high-speed test platforms.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;1342\u0026quot;\u0026gt;Collaboration with design team to define test strategy, create and own test plan.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;1427\u0026quot;\u0026gt;Tester platform selection, design, and development of ATE hardware for wafer sort and final test.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;1528\u0026quot;\u0026gt;Familiar with high-speed load board design techniques.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;1586\u0026quot;\u0026gt;Proven track record of implementing ATE patterns to optimize tester resources and minimize ATE test time while maintaining product quality.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;1729\u0026quot;\u0026gt;Strong knowledge and development of DFT techniques implemented in silicon that provide maximum defect and parametric device coverage – SCAN, MEMBIST, SerDes and other functional tests.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;1917\u0026quot;\u0026gt;Skilled in control interfaces – I2C, I3C, SPI, MDIO, JTAG etc.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;1983\u0026quot;\u0026gt;Expertise in production test of high speed SerDes operating at 16Gbps and higher.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;2068\u0026quot;\u0026gt;Skilled in ATE programming, silicon/ATE bring-up, bench-ATE correlation and debug.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;2154\u0026quot;\u0026gt;Experience with lab equipment including protocol analyzers and oscilloscopes.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;2235\u0026quot;\u0026gt;Experience with using Advantest 93k ATE platform.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;2290\u0026quot;\u0026gt;Proficiency in, at least, one modern programming language such as C/C++, Python.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong data-renderer-mark=\u0026quot;true\u0026quot;\u0026gt;Preferred Experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;2398\u0026quot;\u0026gt;Fluent in data processing using high level programming languages.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;2398\u0026quot;\u0026gt;Experience in running External loopback at wafer sort.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;2467\u0026quot;\u0026gt;Familiarity with modern databases\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;p\u0026gt;The base salary range is $209,000.00 USD – $230,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.\u0026amp;nbsp;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4681921005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4428985005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Finance \u0026 Accounting","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4681921005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2448","title":"Product Cost Manager","company_name":"Astera Labs","first_published":"2026-04-06T20:54:46-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Overview\u0026lt;/strong\u0026gt;\u0026lt;br\u0026gt;This role will be reported to the Sr. Cost Accounting and Inventory Manager and will be primarily responsible for overseeing and managing Astera Labs’ cost accounting processes, ensuring accurate financial reporting and providing insights to support business decision-making. The ideal candidate has semiconductor experience and a strong understanding of GAAP and internal controls structures.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;br\u0026gt;• Develop, implement, and maintain product cost accounting frameworks, cost accounting systems, processes, and internal controls to support a growing and evolving product portfolio.\u0026amp;nbsp;\u0026lt;br\u0026gt;• Own the month-end close process for cost accounting, including preparation of journal entries and reconciliations related to cost of sales, inventory, manufacturing variances, overhead absorption, accruals, reserves, and cost allocations.\u0026amp;nbsp;\u0026lt;br\u0026gt;• Lead detailed analysis of product costs, including material costs, subcontractor manufacturing costs, and other direct and indirect manufacturing costs.\u0026amp;nbsp;\u0026lt;br\u0026gt;• Analyze and monitor manufacturing and inventory variances, and partner with Business Operations to identify cost drivers, trends, and opportunities for improvement.\u0026amp;nbsp;\u0026lt;br\u0026gt;• Manage and enhance the standard cost process, including cost roll-ups, BOM/routing validation, cost component review, and quarterly standard cost updates; ensure standard costs accurately reflect current product structures and manufacturing assumptions.\u0026amp;nbsp;\u0026lt;br\u0026gt;• Partner cross-functionally with Operations, Supply Chain, Engineering, and FP\u0026amp;amp;A to evaluate the cost impact of new products, manufacturing process changes, supplier changes, and manufacturing transitions.\u0026lt;br\u0026gt;• Support new product introduction (NPI) and lifecycle cost management by reviewing initial product cost assumptions, validating costed BOMs, and ensuring timely setup of standard costs in the ERP system.\u0026amp;nbsp;\u0026lt;br\u0026gt;• Support gross margin analysis by providing product cost insights, variance explanations, and bridge analyses for forecast, close, and management reporting.\u0026amp;nbsp;\u0026lt;br\u0026gt;• Drive cost improvement initiatives by partnering with cross-functional teams to identify and evaluate opportunities for cost reduction and optimization, efficiency improvements, yield enhancement, and supply chain savings. \u0026lt;br\u0026gt;\u0026lt;br\u0026gt;\u0026lt;strong\u0026gt;Qualifications\u0026lt;/strong\u0026gt;\u0026lt;br\u0026gt;• 7+ years of experience in Finance or Accounting, including 5+ years of direct experience in product costing, standard cost accounting, and inventory control, preferably in the semiconductor industry.\u0026amp;nbsp;\u0026lt;br\u0026gt;• Strong expertise in standard costing, cost roll-ups, BOM/routing structures, inventory valuation, cost of sales, and manufacturing variance analysis.\u0026amp;nbsp;\u0026lt;br\u0026gt;• Solid understanding of semiconductor supply chain and manufacturing flows, including subcontract manufacturing, wafer/test/assembly processes, and related cost structures strongly preferred.\u0026amp;nbsp;\u0026lt;br\u0026gt;• Thorough knowledge of US GAAP and related inventory and cost accounting principles, including reserves, capitalization, and cost recognition.\u0026amp;nbsp;\u0026lt;br\u0026gt;• Excellent organizational, communication, and cross-functional collaboration skills.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Base salary range is $150,000 to $180,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4000199005,"name":"Finance","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4697682005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4436861005,"location":{"name":"Aachen, North Rhine-Westphalia, Germany"},"metadata":[{"id":12122734005,"name":"Country","value":"Germany","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Aachen","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"CTO Organization","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4697682005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2568","title":"Production Director","company_name":"Astera Labs","first_published":"2026-05-21T16:49:36-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;em\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot; data-ogsc=\u0026quot;red\u0026quot; data-olk-copy-source=\u0026quot;MessageBody\u0026quot;\u0026gt;AsteraLabs Germany GmbH, located in Aachen, is part of the connectivity group and specialized in the design and production of highly scalable fiber-to-the-chip connector solutions, based on micro-optical components.\u0026lt;/span\u0026gt;\u0026lt;/em\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;em\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;As head of the entire production department, the \u0026lt;strong\u0026gt;Director Production \u0026lt;/strong\u0026gt;is responsible for the overarching definition and control of all production processes\u0026amp;nbsp;\u0026lt;span data-ogsc=\u0026quot;red\u0026quot;\u0026gt;for the micro-optical connector units\u0026amp;nbsp;\u0026lt;/span\u0026gt;as well as the management of the entire production team with the aim of safe, on-time, quality- and cost-efficient series production.\u0026lt;/span\u0026gt;\u0026lt;/em\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Location: On-Site - Aachen, North Rhine-Westphalia, Germany.\u0026lt;/p\u0026gt;\n\u0026lt;table\u0026gt;\n\u0026lt;thead\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Area of responsibility\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Job Description\u0026amp;nbsp;\u0026amp;nbsp; \u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;/thead\u0026gt;\n\u0026lt;tbody\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Operational production control\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Ensuring a smooth production process in compliance with labor regulations as well as relevant quality, safety and environmental standards.\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Ensuring the relevant documentation of work results, deviations and corrective actions.\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Determination and analysis of relevant production key figures as well as initiation and monitoring of relevant control measures.\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Organization and resource planning\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Operational production planning as well as efficient resource and deployment planning of machines, systems, raw materials and auxiliary materials.\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Establishment of production regulations and maintenance schedules.\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Ensuring the necessary work preparation, including scheduling and logistics, as well as relevant maintenance.\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Personnel management and department development\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Disciplinary management of employees.\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Conducting feedback meetings, approving vacations, and monitoring absenteeism\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Planning of operational division development and participation in investment decisions for plants and operating resources.\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Personnel planning as well as employee selection and conducting interviews.\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Quality assurance and continuous improvement\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Participation in the preparation of work and test instructions.\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Continuous improvement of production processes using lean management and CIP methods.\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Support in supplier selection and management as well as customer and supplier complaints.\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Training \u0026amp;amp; Communication\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Ensuring all necessary employee training (e.g. occupational safety, process changes)\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Regular presence on the production lines, exchange and support of team leaders and employees on site.\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Identification of development needs.\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;/tbody\u0026gt;\n\u0026lt;/table\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Requirements\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Completed technical studies (e.g. mechanical engineering, production technology, industrial engineering) or further training as a technician/master craftsman with appropriate professional experience\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Several years of professional experience in a leading position in large-scale/series production, in optics, medical or semiconductor.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience in employee management and development as well as capacity and deployment planning\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong communication and assertiveness skills\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep understanding and long-term experience in high precision and highly automated production and testing processes\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Very good understanding of processes as well as analytical and result-oriented thinking, using statistical quality and process data to be used for problem solving and continuous improvement.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Confident handling of MES / ERP systems and MS Office\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;High quality awareness, organizational strength and willingness to take responsibility with hands-on mentality\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Very good written and spoken English skills\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Advantageous\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience with production in cleanrooms.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Extended knowledge and experience in the field of lean production and/or Six Sigma\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Interfaces\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Head of Operations (reporting line)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Development, maintenance, quality assurance, occupational safety\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Human Resources\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;External service providers and authorities\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4140921005,"name":"Optical","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4056756005,"name":"Aachen","location":"Aachen, Germany","child_ids":[],"parent_id":4056755005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4697687005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4436863005,"location":{"name":"Aachen, North Rhine-Westphalia, Germany"},"metadata":[{"id":12122734005,"name":"Country","value":"Germany","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Aachen","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"CTO Organization","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4697687005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2569","title":"Production Planner, Senior","company_name":"Astera Labs","first_published":"2026-05-21T16:51:58-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Senior Production Planning\u0026lt;/strong\u0026gt;\u0026amp;nbsp;is responsible for the efficient planning, control and preparation of the manufacturing processes as well as the availability of the necessary production material in the sense of on-time and economical production.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Responsibilities and tasks\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;table\u0026gt;\n\u0026lt;thead\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td width=\u0026quot;167\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Area of responsibility\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td width=\u0026quot;432\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Job Description\u0026amp;nbsp;\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;/thead\u0026gt;\n\u0026lt;tbody\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td width=\u0026quot;167\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;Production and work planning\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td width=\u0026quot;432\u0026quot;\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Planning, control and monitoring of production orders, taking into account deadlines, capacities and resources\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Detailed and rough planning of production capacities (machines, personnel, materials)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Coordination of appointments with sales, purchasing, logistics and production\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td width=\u0026quot;167\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;Documentation and master data maintenance\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td width=\u0026quot;432\u0026quot;\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Creation and maintenance of work plans, parts lists and production documents\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support in the introduction and further development of ERP/PPS systems\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td width=\u0026quot;167\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;Material planning and logistics\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td width=\u0026quot;432\u0026quot;\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Ensuring material availability in coordination with purchasing and sales on the basis of the quantity forecast.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Implementation of risk-based material requirements planning and adapted supplier strategy.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Participation in supplier selection and management as well as make-or-buy decisions.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Planning and organization of the in-house material flow in cooperation with production.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;tr\u0026gt;\n\u0026lt;td width=\u0026quot;167\u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;Continuous improvement\u0026lt;/p\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;td width=\u0026quot;432\u0026quot;\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Analysis of production key figures (e.g. capacity utilization, throughput time, delivery reliability)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Participation in the optimization of production processes in terms of costs, quality and throughput times.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaboration in improvement and lean projects (e.g. CIP, Six Sigma, shop floor management)\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/td\u0026gt;\n\u0026lt;/tr\u0026gt;\n\u0026lt;/tbody\u0026gt;\n\u0026lt;/table\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Requirements\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Prerequisites\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Completed technical or commercial education (e.g. industrial mechanic, technician, master craftsman, industrial clerk)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Alternatively: Degree in industrial engineering, mechanical engineering, production technology, or similar\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Professional experience in production planning, work preparation or production control for large-scale/series production\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Very good understanding of production processes and manufacturing procedures\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience in dealing with ERP systems\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Confident handling of MS Office, especially Excel\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Analytical and structured way of working\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Organizational and communication skills\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Resilience and assertiveness\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ability to work in a team and independently\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Advantageous\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience with Business Central or Oracle\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with the production of precision components, possibly also in a clean room.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge and experience in the field of lean production and/or Six Sigma\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Very good written and spoken English skills\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Interfaces\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Head of Operations (reporting line)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Purchasing, Quality Assurance\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;External service providers and suppliers\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4140921005,"name":"Optical","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4056756005,"name":"Aachen","location":"Aachen, Germany","child_ids":[],"parent_id":4056755005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4693337005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_optional","internal_job_id":4434511005,"location":{"name":"Suzhou Qu, Gansu, China"},"metadata":[{"id":12122734005,"name":"Country","value":"China","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Suzhou","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Hardware Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4693337005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2518","title":"Production/Test Engineer","company_name":"Astera Labs","first_published":"2026-05-12T02:24:10-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs Inc. is a fabless semiconductor company who is a leader in developing purpose-built connectivity solutions that remove performance bottlenecks in compute-intensive workloads such as artificial intelligence and machine learning. To support rapid international business growth, we are hiring \u0026lt;strong\u0026gt;Production/Test Engineer \u0026lt;/strong\u0026gt;who is based in Suzhou area and have experience supporting the development and manufacturing in semiconductor products for high-speed communication protocols like PCIe, Ethernet, Infiniband, DDR, NVMe, USB, etc.\u0026lt;/p\u0026gt;\n\u0026lt;h3\u0026gt;Job Description:\u0026lt;/h3\u0026gt;\n\u0026lt;p\u0026gt;As the Production/Test Engineer, you will report to Head of PCBA manufacturing. In this role, you will be responsible for PCBA / outsourcing manufacture production management, testing and validation, troubleshooting and issue resolution in production lines. Collaborate with quality organization, engineering team on manufacturing process management and functional validation.\u0026lt;/p\u0026gt;\n\u0026lt;h3\u0026gt;Basic qualifications:\u0026lt;/h3\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;BS in manufacturing, operations, electrical engineering (or other disciplines directly related to manufacturing). Master’s degree is\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Minimum of 5 years’ experience working or managing in manufacturing process (SMT, Assembly, testing, sustaining, PCBA debugging, and functional test)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience working with/managing world-class CMs\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Customer-oriented, Goal-driven, Self-motivated, be able to work independently and be able to travel frequently (25% travel).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Fluent in Mandarin and English\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h3\u0026gt;Required experience:\u0026lt;/h3\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of CM manufacturing processes\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of production quality control processes\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of manufacturing and functional test\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience collaborating with remote design team and manufacturing for production management\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience w/ Agile, Arena, or other PLM tools\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h3\u0026gt;Preferred qualification:\u0026lt;/h3\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Prior experience in NPI/Test/Quality/Supply Chain or other relevant disciplines\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Expertise in Arena PLM\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Working knowledge of reading / understanding schematics, layout files\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience w/ MFG outside Asia\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025526005,"name":"Hardware Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4009038005,"name":"Suzhou","location":"Suzhou, China","child_ids":[],"parent_id":4002875005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4695147005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4435718005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose (HQ)","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Quality Assurance","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Early Career","value_type":"single_select"}],"id":4695147005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2546","title":"Product Quality Engineer (NCG)","company_name":"Astera Labs","first_published":"2026-05-13T16:43:51-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;div class=\u0026quot;my-2\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is seeking a Quality Engineer to join our Product Quality Engineering team in San Jose, CA. This is an exciting opportunity for an early-career engineer to dive into the heart of AI infrastructure connectivity, working hands-on with cutting-edge semiconductor devices that power the world\u0026#39;s most advanced data centers.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;div class=\u0026quot;my-2\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;In this role, you will be instrumental in driving root-cause analysis of failures across circuit, package, firmware, and protocol layers — directly impacting the reliability and quality of our PCIe and Ethernet connectivity solutions. You\u0026#39;ll work with state-of-the-art lab instrumentation, build infrastructure to accelerate failure analysis, and collaborate across engineering disciplines to ensure Astera Labs continues to deliver best-in-class silicon to hyperscale customers. If you\u0026#39;re passionate about high-speed SERDES, signal integrity, and solving complex hardware problems at the intersection of AI and connectivity, this is the role for you.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;div class=\u0026quot;my-2\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;div class=\u0026quot;my-2\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Failure Analysis \u0026amp;amp; Root-Cause Infrastructure\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Enable and develop infrastructure such as databases to optimize and reduce time to root-cause failures in circuit, package, firmware, or protocol-level iterations\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Participate in the new product development process to enable improvements and capabilities for failure analysis\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Document product quality engineering processes and methodologies to ensure repeatability and scalability\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Lab Measurement \u0026amp;amp; Debug\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Perform measurements on high-speed SERDES, PCIe, and Ethernet devices to characterize and debug quality issues\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Set up and use advanced lab instrumentation including BERT, high-bandwidth oscilloscopes, protocol analyzers, VNAs, TDR, and spectrum analyzers to support debug and root-cause activities\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional Collaboration\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Collaborate with design, validation, hardware, and system engineering teams to resolve quality issues and drive continuous improvement\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Support cross-functional efforts to improve product reliability and manufacturing quality\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;div class=\u0026quot;my-2\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;div class=\u0026quot;my-2\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, Computer Engineering, or a related field\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Understanding of high-speed serial interfaces (PCIe, Ethernet, SERDES)\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Familiarity with lab instrumentation such as oscilloscopes, BERT, TDR, or spectrum analyzers\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Strong analytical and problem-solving skills\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Excellent documentation and communication skills\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;div class=\u0026quot;my-2\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;div class=\u0026quot;my-2\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Internship or project experience in semiconductor quality, product engineering, or hardware validation\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Exposure to signal integrity concepts and high-speed measurement techniques\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience with database tools or scripting languages (Python, SQL) for data analysis and infrastructure development\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Familiarity with failure analysis methodologies in a semiconductor environment\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Knowledge of PCIe or Ethernet protocol specifications\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;div class=\u0026quot;my-2\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;The salary range for this position is $120,000 to $140,000 depending on experience and education level. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4011733005,"name":"Quality","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4670952005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_optional","internal_job_id":4423706005,"location":{"name":"Taipei, Taiwan"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Sales","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Internship","value_type":"single_select"}],"id":4670952005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2350","title":"Sales Intern","company_name":"Astera Labs","first_published":"2026-03-09T22:26:54-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;div\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Astera Labs is seeking highly motivated Interns to join the Sales team in the TW team.\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;If you are:\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;A Junior going into Senior year or Senior graduating by the end of this year\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Have strong academics and technical background in Electrical Engineering\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Someone with a professional attitude, ability to prioritize a dynamic list of multiple tasks and work with minimal guidance and supervision\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong in analytical skills, self-motivated and a challenge taker\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;What we are looking for:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Develop regional sales analysis and planning materials by identifying market segments, opportunity sizing, and internal execution strategies\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support sales initiatives by partnering closely with FAEs and internal stakeholders to prepare product information, roadmap materials, technology training content, and internal documentation\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Consolidate and analyze input from internal teams to support product planning, roadmap alignment, and internal issue tracking\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Coordinate cross-functional information flow among sales, operations, and supply-related teams to support quarterly revenue planning and mid-term demand projections\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Assist in market and ecosystem research across CPU, GPU, FPGA, Networking, Memory, and BMC segments to identify co-development and strategic opportunity areas\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;If the above position excites you, we would love to hear from you.\u0026lt;/p\u0026gt;\n\u0026lt;/div\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4000197005,"name":"Sales","child_ids":[],"parent_id":null}],"offices":[{"id":4009035005,"name":"Taipei","location":"Taipei, Taiwan","child_ids":[],"parent_id":4002874005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4682576005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4429308005,"location":{"name":"Taipei, Taiwan"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Sales Operations","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4682576005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2455","title":"Sales Operations Specialist","company_name":"Astera Labs","first_published":"2026-04-08T23:56:44-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p class=\u0026quot;x_xxmsonormal\u0026quot;\u0026gt;\u0026lt;strong data-olk-copy-source=\u0026quot;MessageBody\u0026quot;\u0026gt;Department:\u0026lt;/strong\u0026gt; Sales Operations\u0026lt;br\u0026gt;\u0026lt;strong\u0026gt;Reports To:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Sales Operations Director\u0026lt;br\u0026gt;\u0026lt;strong\u0026gt;Location:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Taiwan\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;x_xxmsonormal\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Employment Type:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;Full-Time\u0026lt;/p\u0026gt;\n\u0026lt;div class=\u0026quot;x_MsoNormal\u0026quot;\u0026gt;\u0026lt;hr width=\u0026quot;100%\u0026quot;\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;p class=\u0026quot;x_xxmsonormal\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Position Overview:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;x_xxmsonormal\u0026quot;\u0026gt;We are seeking a highly organized and detail-oriented entry-level candidate to support our sales operations in a fast-paced, high-tech environment. This role is responsible for processing customer purchase orders for Astera Labs product portfolio—ensuring compliance with internal policies, licensing terms, and revenue recognition guidelines. You will collaborate closely with Sales, Legal, Finance, Quality, Supply Chain and Logistics teams to ensure orders are booked, billed, and delivered accurately and on time.\u0026lt;/p\u0026gt;\n\u0026lt;div class=\u0026quot;x_MsoNormal\u0026quot;\u0026gt;\u0026lt;hr width=\u0026quot;100%\u0026quot;\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;p class=\u0026quot;x_xxmsonormal\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul type=\u0026quot;disc\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;x_xxmsonormal\u0026quot;\u0026gt;Review and enter orders into the order management system (e.g., Oracle ERP) including customer purchase orders (POs), samples and RMAs\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xxmsonormal\u0026quot;\u0026gt;Validate orders for accuracy, contract terms, licensing details, and revenue recognition compliance (SOX compliance and ISO)\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xxmsonormal\u0026quot;\u0026gt;Coordinate with Sales, Legal, and Finance to resolve order discrepancies, billing issue, payment term/incoterm compliance or missing documentation\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xxmsonormal\u0026quot;\u0026gt;Track order status, fulfillment timelines, and escalate delivery or provisioning issues when needed\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xxmsonormal\u0026quot;\u0026gt;Generate order confirmations, invoices, and shipping documents where applicable\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xxmsonormal\u0026quot;\u0026gt;Support month-end and quarter-end order processing deadlines in coordination with Finance\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xxmsonormal\u0026quot;\u0026gt;Maintain accurate records of all orders including qty, customer communications, and contract terms in CRM/ERP systems\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xxmsonormal\u0026quot;\u0026gt;Drive RMA approval process and manage RMA request from customer communication, system handling to fulfillment.\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xxmsonormal\u0026quot;\u0026gt;Act as a liaison between Sales, Product Marketing, Supply Chain, and Customers to manage and support sample requests—particularly for NPI products and development boards.\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xxmsonormal\u0026quot;\u0026gt;Ensure fast-turnaround on sample process and maintain accurate records of all sample-related activities in sample tracking system.\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xxmsonormal\u0026quot;\u0026gt;Contribute to process improvements and automation initiatives to increase operational efficiency\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;div class=\u0026quot;x_MsoNormal\u0026quot;\u0026gt;\u0026lt;hr width=\u0026quot;100%\u0026quot;\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;p class=\u0026quot;x_xxmsonormal\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Qualifications:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul type=\u0026quot;disc\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;x_xxmsonormal\u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Business Administration, Finance, or related field (or equivalent experience)\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xxmsonormal\u0026quot;\u0026gt;2+ years of experience in order administration or sales operations, preferably in the high-tech industry\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xxmsonormal\u0026quot;\u0026gt;Familiarity with CRM and ERP systems (Salesforce, Oracle, CPQ, SAP, or similar)\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xxmsonormal\u0026quot;\u0026gt;Understanding of supply chain, forecasting, billing terms, incoterms and revenue recognition principles\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xxmsonormal\u0026quot;\u0026gt;Strong analytical, organizational, and problem-solving skills\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xxmsonormal\u0026quot;\u0026gt;High attention to detail and ability to work independently under tight deadlines\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xxmsonormal\u0026quot;\u0026gt;Excellent written and verbal communication skills\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xxmsonormal\u0026quot;\u0026gt;Customer-facing experience with the ability to communicate professionally with external customers and internal cross-functional teams\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xxmsonormal\u0026quot;\u0026gt;Strong Excel and data analysis skills; experience with PPT and BI tools (e.g., PowerBI) is a plus\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;div class=\u0026quot;x_MsoNormal\u0026quot;\u0026gt;\u0026lt;hr width=\u0026quot;100%\u0026quot;\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;p class=\u0026quot;x_xxmsonormal\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Preferred Skills:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul type=\u0026quot;disc\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;x_xxmsonormal\u0026quot;\u0026gt;Experience working with cross-functional teams in a global technology company\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xxmsonormal\u0026quot;\u0026gt;Knowledge of semiconductor industry and experience in customer interfacing role.\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xxmsonormal\u0026quot;\u0026gt;Understanding of SOX compliance and f audit requirements\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xxmsonormal\u0026quot;\u0026gt;Prior experience with quote-to-cash workflows\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;div class=\u0026quot;x_MsoNormal\u0026quot;\u0026gt;\u0026lt;hr width=\u0026quot;100%\u0026quot;\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;p class=\u0026quot;x_xxmsonormal\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Working Environment:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul type=\u0026quot;disc\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;x_xxmsonormal\u0026quot;\u0026gt;On-site work environment\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xxmsonormal\u0026quot;\u0026gt;Fast-paced, deadline-driven high-tech setting\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xxmsonormal\u0026quot;\u0026gt;May require extended hours during fiscal close periods\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4000201005,"name":"Business Operations","child_ids":[],"parent_id":null}],"offices":[{"id":4009035005,"name":"Taipei","location":"Taipei, Taiwan","child_ids":[],"parent_id":4002874005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4654351005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4416406005,"location":{"name":"Vietnam"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Analog/Mixed-Signal","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4654351005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2248","title":"Senior Analog Mixed-Signal CAD Engineer ","company_name":"Astera Labs","first_published":"2026-01-27T17:24:40-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Job Summary:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;We are seeking a highly motivated and detail-oriented \u0026lt;strong\u0026gt;Analog Mixed-Signal CAD Engineer\u0026lt;/strong\u0026gt; to join our design automation team. In this role, you will develop, maintain, and support CAD tools and design flows for analog and mixed-signal IC design. You will work closely with circuit designers, layout engineers, and EDA vendors to ensure efficient and robust design environments.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Develop and maintain analog/mixed-signal design flows using industry-standard EDA tools (Cadence Virtuoso, Spectre, etc.).\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Automate design tasks using scripting languages (e.g., Python, SKILL, Tcl, Perl).\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support schematic, layout, simulation, and verification environments.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with design teams to understand requirements and improve design productivity.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Integrate and validate PDKs (Process Design Kits) and technology files.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Provide documentation, training, and support for CAD tools and flows.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Interface with EDA vendors to evaluate and deploy new tools and features.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Monitor and resolve CAD tool issues, ensuring high availability and performance.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Qualifications:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;3+ years of experience in analog/mixed-signal CAD or EDA tool development.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong knowledge of analog/mixed-signal IC design methodologies.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency in scripting languages such as SKILL, Python, Tcl, or Perl.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with Cadence Virtuoso, Spectre, and AMS simulation environments.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with PDK integration and technology file management.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent problem-solving, communication, and teamwork skills.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications:\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience with digital-on-top (DoT) or mixed-signal verification flows.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of version control systems (e.g., Git, Perforce).\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with Unix/Linux environments and shell scripting.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Exposure to advanced process nodes (e.g., 7nm, 5nm).\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4135671005,"name":"SerDes","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4053943005,"name":"Vietnam","location":"Ho Chi Minh City, Ho Chi Minh City, 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Engineer","company_name":"Astera Labs","first_published":"2026-03-10T16:40:44-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;We are seeking an experienced Analog/Mixed-Signal (AMS) Circuit Design Engineer to join our high-performance design team working on next-generation transceiver IPs targeting the TSMC 5/3nm technology node. In this role, you will design high-speed analog and mixed-signal circuits used in multi-gigabit transceivers, collaborating with layout, verification, and system teams to ensure robust performance, power efficiency, and successful silicon validation at advanced process nodes.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Design critical AMS blocks such as PLLs, CDRs, LDOs, bias generators, and ADC/DAC components for wireline transceivers.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Perform transistor-level design, simulation, and optimization for performance, power, and area across process, voltage, and temperature (PVT) corners.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work closely with layout engineers to guide floorplanning, matching-sensitive layout, and parasitic-aware design. • Perform design verification using pre- and post-layout simulations (transient, AC, noise, Monte Carlo, corner sweep).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ensure robust operation under variation, jitter, power supply noise, and crosstalk conditions.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Create and maintain design documentation, design reviews, and specifications\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with system architects, digital design, and firmware teams to define and optimize mixed-signal interface behavior.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support silicon bring-up, lab measurement correlation, and debug of design issues.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Use industry-standard tools (e.g., Virtuoso, Spectre, HSPICE, ADE, MATLAB, Python) for design and analysis.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s or Master’s degree in Electrical Engineering, Microelectronics, or related field.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;5+ years of experience in analog/mixed-signal circuit design in deep-submicron or FinFET technologies.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong experience with:\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Transistor-level design and simulation in advanced nodes (≤ 5nm).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Designing analog blocks for high-speed transceivers (e.g., clocking, bias, analog front ends).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;SPICE simulation tools and AMS verification environments.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep understanding of noise, jitter, linearity, bandwidth, gain, impedance matching, and power trade-offs.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with layout interaction and parasitic-aware circuit optimization.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Solid debugging, problem-solving, and documentation skills.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Benefits\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Competitive salary\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;13th month salary\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Performance bonus each year\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Flexible working time\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Health check each year\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Insurance for engineer and family\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lunch Allowance\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Company trips.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4135671005,"name":"SerDes","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4053943005,"name":"Vietnam","location":"Ho Chi Minh City, Ho Chi Minh City, Vietnam","child_ids":[4061062005,4053944005],"parent_id":null}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4649872005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4414108005,"location":{"name":"Israel"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Digital Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4649872005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2204","title":"Senior ASIC Design Engineer","company_name":"Astera Labs","first_published":"2026-01-15T19:43:19-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is establishing a strategic R\u0026amp;amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical \u0026#39;data bottlenecks\u0026#39; enabling the future of AI at scale. As we expand our presence in Israel, we\u0026#39;re seeking a talented\u0026lt;strong\u0026gt; \u0026lt;span class=\u0026quot;TextRun Underlined SCXW209305118 BCX0\u0026quot; lang=\u0026quot;EN-US\u0026quot; data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;NormalTextRun SCXW209305118 BCX0\u0026quot;\u0026gt;Senior ASIC Design Engineer\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026amp;nbsp;\u0026lt;/strong\u0026gt;to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful product ownership in a new site, designing the digital blocks that sit at the heart of our most ambitious connectivity projects.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As a\u0026lt;strong\u0026gt; \u0026lt;span class=\u0026quot;TextRun Underlined SCXW209305118 BCX0\u0026quot; lang=\u0026quot;EN-US\u0026quot; data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;NormalTextRun SCXW209305118 BCX0\u0026quot;\u0026gt;Senior ASIC Design Engineer\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;, you won\u0026#39;t just build chips—you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world\u0026#39;s largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving challenging problems in deep-submicron processes and want to contribute to the digital design foundation for AI infrastructure connectivity, this is your opportunity.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Design Ownership \u0026amp;amp; Implementation\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Serve as the point of contact for your logic blocks, interacting with Architecture, Verification, and Backend teams\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Quality Assurance \u0026amp;amp; Design Optimization\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Utilize industry-leading EDA tools (Lint, CDC, Synthesis, Timing, Power) and in-house quality assurance tools to ensure designs are robust, scalable, and power-efficient\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Apply design techniques to meet PPA (Power, Performance, Area) targets\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Contribute to design quality through verification and validation activities\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Methodology Innovation \u0026amp;amp; Collaboration\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Participate in design methodology improvements and tool automation initiatives\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Leverage AI assistance tools and contribute to in-house automation development to make engineering workflows faster and smarter\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Collaborate effectively across teams to ensure seamless integration\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering or related technical field\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;3+ years of experience in logic design at semiconductor companies\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Knowledge and experience in Verilog and/or SystemVerilog\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Excellent communication skills with ability to work effectively across teams\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Understanding of digital design principles and RTL coding best practices\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Master\u0026#39;s degree in Electrical Engineering or related field\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Knowledge of DDR and PCIe protocols and implementation\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Understanding of power management techniques for low-power design\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Familiarity with Clock Domain Crossing, simulation, debugging, synthesis, and timing analysis\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Proficiency in scripting languages such as Python or Perl\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience with high-speed serial interface designs or connectivity protocols\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4008937005,"name":"Israel","location":"Israel","child_ids":[4061058005,4052111005,4056876005],"parent_id":null}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4702305005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4438941005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose (HQ)","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Sales Operations","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4702305005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2616","title":"Senior Business Systems Analyst","company_name":"Astera Labs","first_published":"2026-06-03T13:20:49-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-olk-copy-source=\u0026quot;MessageBody\u0026quot;\u0026gt;About Astera Labs\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) is a pioneering fabless semiconductor company headquartered in Silicon Valley, driving the evolution of AI and cloud infrastructure through purpose-built connectivity solutions. As a leader in rack-scale architecture, Astera Labs is enabling the shift to AI Infrastructure 2.0, where compute is optimized at the rack level to support next-generation workloads. Our portfolio spans high-performance silicon, software, and system-level solutions that address critical bottlenecks in data movement across compute, memory, and networking domains. We are committed to open standards, continuous innovation, and building a collaborative environment to solve complex challenges at scale.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Astera Labs is seeking a hands-on Senior Business System Analyst to own and scale our CRM and business operations systems. This role is responsible for system administration, workflow automation, integrations, and continuous enhancements to support Sales, Operations, Finance, Product, and IT teams.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;In addition to core Salesforce platform ownership, this role will help drive business process improvements and system enablement across broader operational workflows. The ideal candidate combines strong technical expertise with business process understanding and can translate requirements into scalable Salesforce and business operations solutions that improve efficiency, visibility, and execution across the organization.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;A Day in the Life\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;In this role, you will work at the intersection of business process design and system execution, helping teams operate more efficiently through scalable tools, workflows, and data visibility. You will spend time partnering with stakeholders across Sales, Operations, Finance, Product, and IT to understand requirements, improve workflows, and ensure systems support the needs of a growing organization.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Your day may include gathering requirements for a new workflow, configuring Salesforce enhancements, troubleshooting system or integration issues, coordinating testing and release activities, or improving approval and reporting processes. You may also help connect Salesforce with other enterprise systems and support broader business operations initiatives that require stronger automation, better controls, and cleaner data.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;This is a highly cross-functional role with strong ownership, where technical judgment, responsiveness, and process thinking are critical to scaling internal operations effectively.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul type=\u0026quot;disc\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Own end-to-end Salesforce platform management, including system configuration, user access, data integrity, performance monitoring, and ongoing enhancements\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Design, build, and optimize business workflows, including pipeline/opportunity and pricing approval processes, improving efficiency, scalability, and auditability\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Lead integrations between Salesforce and enterprise systems (e.g., Jira, Confluence, Outlook/email, customer ticketing platforms), ensuring secure, scalable, and maintainable architecture\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Manage access control, roles, profiles, and permission sets, enforcing governance, compliance, and least-privilege security principles\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Partner cross-functionally with Sales, Operations, Finance, Product, and IT teams to gather requirements, drive enhancements, and standardize processes across the organization\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Support operational workflows and process improvements across business systems, including areas such as planning, approvals, visibility, and execution tracking\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Troubleshoot system issues, workflow failures, and integration errors, and proactively identify opportunities for system optimization and automation\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Manage release processes, including testing, deployment, change management, and documentation of system configurations and business processes\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Support data governance initiatives, including data quality standards, validation rules, and regular audits to ensure accuracy and consistency\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Provide end-user support, training, and documentation to improve adoption and effective use of Salesforce and business systems across teams\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Maintain a prioritized Salesforce and business operations systems roadmap, balancing business needs, technical scalability, and resource constraints\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Collaborate with IT and security teams to ensure compliance with internal policies, audit requirements, and best practices for system integrations and access\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul type=\u0026quot;disc\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Bachelor’s degree in Business, Information Systems, Computer Science, or a related field\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;5+ years of Salesforce administration or platform management experience\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Strong knowledge of Salesforce configuration (objects, workflows, validation, approvals)\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Experience with system integrations (APIs, middleware, or external systems)\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Solid understanding of Salesforce security model (roles, profiles, permission sets)\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Experience building and optimizing approval workflows\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Strong communication skills and ability to work cross-functionally\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Ability to gather business requirements and translate them into scalable system and process solutions\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Experience supporting cross-functional business systems in a fast-paced environment\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul type=\u0026quot;disc\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Experience supporting CRM and business operations systems in a high-growth environment\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Experience with workflow automation, release management, and system change governance\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Familiarity with operational workflows across Sales, Operations, Finance, and Product teams\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Experience with Jira, Confluence, Outlook/email integrations, or customer support platforms\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Experience improving business process efficiency, controls, and reporting visibility\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Semiconductor, hardware, or enterprise technology industry experience is a plus\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Why Join Us?\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul type=\u0026quot;disc\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Be part of a high-growth company scaling systems and operations for the AI infrastructure era\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Play a key role in improving the tools, workflows, and controls that enable cross-functional execution\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Work closely with stakeholders across Sales, Operations, Finance, Product, and IT\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4000197005,"name":"Sales","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4640055005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4409537005,"location":{"name":"Haifa, Israel"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Firmware Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4640055005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2163","title":"Senior Data Science Engineer","company_name":"Astera Labs","first_published":"2025-12-11T13:18:26-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Job Description\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera labs is seeking a skilled and motivated Data Scientist. This individual will play a pivotal role in identifying key data points for collection, developing strategies to accumulate data and deriving actionable insights an anomaly based on a solid foundation of relevant know-how. Also, will also be responsible for creating, testing, and deploying scripts and methods for data collection and analysis to support decision-making. The Engineer will collaborate with cross-functional teams to identify critical data sources to determine the most effective data collection strategies, will develop automated and scalable data collection pipelines, will ensure data quality, integrity, and consistency across all sources and may use AI techniques to refine the results toward failures predictions.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s degree in computer science, Data Science, Engineering, Mathematics, or a related field.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Advanced degrees in data science or Machine learning / AI - Advance.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency in programming languages such as Python, R, or MATLAB.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of data manipulation and analysis tools (e.g., Pandas, NumPy, SQL).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Understanding of high speed interfaces such as Ethernet, PCI-E , WiFi.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with data visualization tools such as Tableau, Matplotlib, Graphana.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong analytical and critical-thinking skills to identify patterns and outliers.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Customer-obsession, Think and act with the customer in mind!\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Goal-driven, Self-motivated, be able to work independently and with teams with people around the globe.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Entrepreneurial, open-minded behavior and can-do attitude.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience with data manipulation and analysis tools (e.g., Pandas, NumPy, SQL).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Machine learning and AI techniques and frameworks (e.g., TensorFlow, Scikit-learn).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven ability to manage multiple tasks and meet deadlines.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Embedded Firmware development with C-language, scripting with Python or other equivalent programming languages.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Master’s degree in a relevant field.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with cloud platforms (e.g., AWS, Azure, GCP) for data storage and processing.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with big data technologies (e.g., Hadoop, Spark).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of engineering design tools and processes.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025528005,"name":"Software Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4052111005,"name":"Haifa","location":"Haifa, Israel","child_ids":[],"parent_id":4008937005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4654280005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4416391005,"location":{"name":"Vietnam"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Design Verification","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4654280005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2246","title":"Senior Design Verification Engineer","company_name":"Astera Labs","first_published":"2026-01-27T16:47:46-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Job Summary: We are seeking a talented Senior Design Verification Engineer to join our team. The ideal candidate will play a key role in verifying the functionality and performance of our digital and mixed-signal designs. You will work closely with the design and development teams to create and execute comprehensive verification plans, ensuring the robustness and reliability of our products.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Key Responsibilities:\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Develop and implement test plans and testbenches for verification of sub-blocks in high-speed Ethernet, UALink, PCIE PHY (64b/66b Encoder/Decoder, FEC encoder/decoder, DSP, FFE, DFE, MLSD).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Identify, document, and debug functional issues found during verification, collaborating with design engineers for resolution.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop and apply coverage models to ensure thorough validation of the design.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work closely with architects, designers, and software teams to comprehend the design architecture and contribute to high-level verification strategy.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Stay up-to-date with industry best practices and emerging tools for design verification.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Qualifications:\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s in Electrical Engineering, Computer Engineering, or a related field.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;2+ year of experience in DV.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong proficiency in verification languages such as System Verilog, UVM (Universal Verification Methodology).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with simulation tools (e.g., Cadence Xcelium, Synopsys VCS, or Mentor Graphics QuestaSim).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with scripting languages such as Python, Perl, or Shell scripting for automation purposes.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;In-depth understanding of digital design principles, verification methodologies, and industry-standard protocols.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent analytical, debugging, and problem-solving skills.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong teamwork and communication abilities.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Pay and Benefits\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Competitive salary.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Performance bonus each year.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Flexible working time.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Health check each year.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Insurance for engineer and family.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lunch Allowance.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Company trips.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4135671005,"name":"SerDes","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4053944005,"name":"Ho Chi Minh City","location":"Ho Chi Minh City, Ho Chi Minh City, Vietnam","child_ids":[],"parent_id":4053943005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4701333005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4438397005,"location":{"name":"Tel Aviv-Yafo, Tel Aviv District, Israel"},"metadata":[{"id":12122734005,"name":"Country","value":"Israel","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Tel-Aviv","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Design Verification","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4701333005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2601","title":"Senior Design Verification Engineer ","company_name":"Astera Labs","first_published":"2026-06-01T05:43:30-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is establishing a strategic R\u0026amp;amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical \u0026#39;data bottlenecks\u0026#39; enabling the future of AI at scale. As we expand our presence in Israel, we\u0026#39;re seeking a talented\u0026amp;nbsp;\u0026lt;strong\u0026gt;Senior Design Verification Engineer\u0026lt;/strong\u0026gt;\u0026amp;nbsp;to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, developing the verification environments that ensure our next-generation AI silicon performs flawlessly.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As a\u0026amp;nbsp;\u0026lt;strong\u0026gt;Senior Design Verification Engineer\u0026lt;/strong\u0026gt;, you will be a vital contributor to the quality and reliability of our Israel R\u0026amp;amp;D center. You will work on the front lines of functional verification, developing testbenches and environments that validate high-performance digital blocks, subsystems, and full-chip designs. You will tackle complex verification challenges that ensure our connectivity solutions meet the rigorous demands of the world\u0026#39;s largest AI clusters. If you thrive on solving technical puzzles and want to play a key role in delivering cutting-edge AI infrastructure connectivity, this is your opportunity.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Verification Environment Development\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Contribute to the design and development of ASIC verification environments, focusing on unit-level and subsystem functional blocks\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Develop and maintain SystemVerilog/UVM-based components including traffic generators, monitors, and checkers to ensure robust testing\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Execute detailed verification plans for challenging digital designs, ensuring all functional requirements are met and verified\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Coverage \u0026amp;amp; Quality Assurance\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Implement functional coverage models and analyze results to identify gaps in the verification process\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Drive designs toward 100% verification closure through comprehensive test development\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Contribute to verification methodology improvements and best practices\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Debug \u0026amp;amp; Cross-Functional Collaboration\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Work closely with design engineers to identify, root-cause, and resolve complex hardware bugs early in the development cycle\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Apply analytical skills and debugging techniques to solve intricate verification challenges\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Collaborate effectively in a fast-paced, team-oriented R\u0026amp;amp;D environment\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering or related technical field\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;3+ years of proven experience in ASIC verification within the semiconductor industry\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Hands-on experience developing components within complex verification environments using SystemVerilog\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Strong working knowledge of standard verification methodologies, specifically UVM\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Sharp analytical mind with passion for debugging and technical problem-solving\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Excellent communication skills with ability to thrive in collaborative R\u0026amp;amp;D environments\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Master\u0026#39;s degree in Electrical Engineering or related field\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Familiarity with Formal Verification or Emulation flows\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Basic proficiency in scripting languages such as Python or Tcl to automate verification tasks\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Exposure to industry-standard protocols such as AMBA, PCIe, Ethernet, or CXL\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience with assertion-based verification and constrained-random testing\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Background in connectivity or networking silicon verification\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4052111005,"name":"Haifa","location":"Haifa, Israel","child_ids":[],"parent_id":4008937005},{"id":4056876005,"name":"Tel Aviv","location":"Tel Aviv, Israel","child_ids":[],"parent_id":4008937005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4649842005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4414084005,"location":{"name":"Israel"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Physical Design/DFT","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4649842005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2200","title":"Senior DFT Engineer","company_name":"Astera Labs","first_published":"2026-01-15T18:57:49-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is establishing a strategic R\u0026amp;amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical \u0026#39;data bottlenecks\u0026#39; enabling the future of AI at scale. As we expand our presence in Israel, we\u0026#39;re seeking a visionary\u0026lt;strong\u0026gt; Senior DFT Engineer\u0026amp;nbsp;\u0026lt;/strong\u0026gt;to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world\u0026#39;s largest AI clusters.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As a \u0026lt;strong\u0026gt;Senior DFT Engineer\u0026lt;/strong\u0026gt; at Astera Labs, you will be at the intersection of architecture, design, and production. You won\u0026#39;t just run tools—you will be a foundational member of the team responsible for the entire lifecycle of our silicon\u0026#39;s reliability. From defining initial DFT architecture to supporting post-silicon bring-up, your work ensures that the backbone of AI infrastructure connectivity is flawless and scalable. If you thrive on solving complex challenges in deep-submicron processes and want to establish world-class DFT methodologies, this is your opportunity.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;DFT Architecture \u0026amp;amp; Strategy\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Own the DFT journey from high-level architecture definition and RTL design to backend implementation and post-production support\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Develop comprehensive Design-for-Testability (DFT) strategies for next-generation connectivity platforms, ensuring chips meet the highest quality standards\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Define DFT architectures including JTAG/iJTAG, MBIST, Scan, and ATPG methodologies\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Test Pattern Development \u0026amp;amp; Optimization\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Generate and optimize high-quality test and debug patterns for production\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Perform Static Timing Analysis (STA) for DFT modes and conduct gate-level simulations to ensure robust performance\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Drive test coverage and quality metrics to meet stringent manufacturing requirements\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional Collaboration \u0026amp;amp; Methodology Innovation\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Act as a multidisciplinary bridge, collaborating closely with Architecture, Verification, and Backend teams to ensure seamless integration and optimal QoR\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Participate in developing and maintaining cutting-edge DFT implementation flows\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Automate and improve methodologies using advanced scripting and tools\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering or related technical field\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;3+ years of hands-on experience in DFT roles at semiconductor companies\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Deep expertise in DFT flows and architectures including JTAG/iJTAG, MBIST, Scan, and ATPG\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Proficiency with industry-standard EDA tools from Synopsys (TestMAX) or Mentor (Tessent)\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Strong understanding of logic design, verification, debug, and Static Timing Analysis (STA)\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Scripting proficiency in Tcl, Perl, Python, or Shell for automation and innovation\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Master\u0026#39;s degree in Electrical Engineering or related field\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Knowledge of high-speed interface protocols (PCIe, Ethernet, CXL, UALink) and their specific test requirements\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience in chip bring-up and mass production activities\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Background in advanced process technologies (7nm and below)\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Excellent communication skills with ability to work effectively in global team environments\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4008937005,"name":"Israel","location":"Israel","child_ids":[4061058005,4052111005,4056876005],"parent_id":null}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4695219005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4435751005,"location":{"name":"Taipei, Taiwan"},"metadata":[{"id":12122734005,"name":"Country","value":"Taiwan","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Taipei","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Hardware Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4695219005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2552","title":"Senior Diagnostic Platform Software Engineer","company_name":"Astera Labs","first_published":"2026-05-14T05:47:27-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;div\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at\u0026amp;nbsp;\u0026lt;a id=\u0026quot;menur64a\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;https://nam02.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.asteralabs.com%2F\u0026amp;amp;data=05%7C02%7Clori.zielinski%40asteralabs.com%7Cd09d9bcc97d041239f3708ddb8ef2ac9%7Cf47c88fd08a94016b4883f361c03ff2e%7C0%7C0%7C638870059538319538%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C\u0026amp;amp;sdata=BauZlULXzw5HeuuXG6T2bvjHSrf8OH5%2BoEDddHCuPp4%3D\u0026amp;amp;reserved=0\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;\u0026lt;u\u0026gt;www.asteralabs.com\u0026lt;/u\u0026gt;\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Job Description:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As member of Astera Labs Hardware Engineering team you will be responsible for building diagnostics and manufacturing software to allow design, test, and manufacture cutting edge high speed datacenter products.\u0026amp;nbsp; You will be working on project from conception to the final production stage at contract manufacturer.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;The role requires strong and broad software background and good understanding of hardware design and manufacturing practices.\u0026amp;nbsp; At the same time we welcome candidates with deep experience in smaller areas and desire to learn.\u0026amp;nbsp; Depending on your experience you may be focusing on design/validation or automation/manufacturing.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Design, implement \u0026amp;amp; test production-grade diagnostics for high-speed digital boards and ASICS to help with hardware validation.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Design, implement \u0026amp;amp; test manufacturing tests to validate mass production of digital boards used in data center networking product\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Bring-up newly manufactured boards.\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Isolate and perform root-cause analysis of reported failures\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support new platform software and hardware features\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Coordinate with the hardware engineering team on bring-up schedules and feature delivery\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Participate proactively in design discussions, design review, and project management\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work independently as well as in team roles, mentor younger team members\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Business travel to China will be required as needed\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications/Required Experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s in CS/CE or equivalent experience.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;2+ years of Experience in subset of diag, hardware bring-up, test or manufacturing automation\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of modern software development\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency in Python\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience working with datacenter-level complex electronic equipment bring-up/diagnostic/manufacturing\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ability to read schematic/layout\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;System debug experience\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Embedded programming and good knowledge of OS internals (Linux/Unix)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Has knowledge of common inter connecting buses and interfaces \u0026amp;nbsp;such as \u0026amp;nbsp;PCIe, I2C, XAUI, 10G Ethernet drivers, FPGA, Switch chips, SSL offload, TCAM programming.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with DDR5\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/div\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025526005,"name":"Hardware Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4009035005,"name":"Taipei","location":"Taipei, Taiwan","child_ids":[],"parent_id":4002874005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4644970005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4411892005,"location":{"name":"San Jose, CA"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Digital Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4644970005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2180","title":"Senior Digital Design Engineer (AI Fabric)","company_name":"Astera Labs","first_published":"2025-12-30T17:30:44-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Overview\u0026lt;/strong\u0026gt;\u0026lt;br\u0026gt;Join our team as \u0026lt;strong\u0026gt;Senior Digital Design Engineer\u0026lt;/strong\u0026gt; to contribute to the design and implementation of next-generation digital designs for high-performance connectivity solutions. You\u0026#39;ll work on complex blocks from micro-architecture through silicon bring-up, collaborating with verification, PD, and DFT teams to deliver high-performance products in a fast-paced, collaborative environment.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Own the RTL implementation of complex digital designs from micro-architecture through sign-off.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with verification teams to review test plans and debug issues.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support efforts to achieve timing closure and implement Design-for-Test (DFT) features.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Scripting and automation for ASIC methodology improvement.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Accountable for quality and overall design success with the support of senior engineers.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Qualifications\u0026lt;/strong\u0026gt;\u0026lt;br\u0026gt;\u0026lt;strong\u0026gt;Education \u0026amp;amp; Experience:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s degree in electrical engineering or equivalent\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;3-8 years of experience developing SoC/silicon products in Server, Storage, and/or Networking markets\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Digital Design Expertise:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Expertise in RTL coding with SystemVerilog and synthesis with Synopsys or Cadence.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Track record of delivering high quality digital designs from definition to production.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with functional and formal verification at block and chip level.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Understanding of clocking, CDC and RDC\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with CMOS nodes (≤7nm)\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Protocols \u0026amp;amp; Integration:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with high-speed protocols—PCIe, Ethernet, DDR, or similar\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with IP development and integration\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Tools \u0026amp;amp; Methodologies:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Proven SystemVerilog and Python expertise in a production environment\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with Synopsys and/or Cadence digital design flows\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Basic understanding of UVM-based verification methodologies\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Professional Attributes:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong eagerness to learn and grow with the ability to balance multiple priorities in a dynamic environment\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Good communication and collaboration skills; comfortable working cross-functionally with global teams\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Self-directed learner who adapts quickly to changing requirements\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Customer-focused mindset with the ability to prioritize and work independently to deliver high quality designs.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience with embedded firmware development or standard embedded processor subsystems (RISC-V, Arm, etc.) is a plus\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with design methodology, CAD automation, or design infrastructure that have improved team productivity or design quality is a plus\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;p\u0026gt;Base salary range is $160,000 USD-$195,000 USD, and will be determined based on the candidate\u0026#39;s capabilities and employees in similar positions.\u0026lt;/p\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4687603005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4431700005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Digital Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4687603005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2474","title":"Senior Digital Design Engineer, IP and Methodology","company_name":"Astera Labs","first_published":"2026-04-21T19:27:13-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;Join Astera Labs as a\u0026amp;nbsp;\u0026lt;strong\u0026gt;Senior Digital Design Engineer\u0026lt;/strong\u0026gt; to drive the design and implementation of next-generation digital designs for high-performance AI connectivity solutions. In this role, you\u0026#39;ll focus on CPU subsystem development and security architecture, working on complex blocks from micro-architecture through silicon bring-up.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;You\u0026#39;ll collaborate closely with verification, physical design, and DFT teams to deliver industry-leading products that power the world\u0026#39;s most advanced data centers. This is an opportunity to shape the security and compute foundations of connectivity solutions enabling rack-scale AI infrastructure at hyperscale.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;RTL Design \u0026amp;amp; Implementation\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Own the RTL implementation of complex digital designs from micro-architecture through sign-off\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Design and implement CPU subsystems and embedded processor interfaces\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Develop security-focused digital blocks including secure boot, cryptographic engines, and trusted execution environments\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Verification \u0026amp;amp; Quality\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Collaborate with verification teams to review test plans and debug issues\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Support efforts to achieve timing closure and implement Design-for-Test (DFT) features\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Accountable for quality and overall design success with the support of senior engineers\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Methodology \u0026amp;amp; Automation\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Scripting and automation for ASIC methodology improvement\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Contribute to design infrastructure that improves team productivity and design quality\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering or equivalent\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;3+ years of experience developing SoC/silicon products in Server, Storage, and/or Networking markets\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Expertise in RTL coding with SystemVerilog and synthesis with Synopsys or Cadence\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience with CPU subsystem design or embedded processor integration (RISC-V, ARM, or similar architectures)\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Understanding of security fundamentals in silicon design (secure boot, root of trust, cryptographic implementations)\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience with clocking, CDC, and RDC methodologies\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Proficiency in SystemVerilog and Python in a production environment\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience designing or integrating security IP (cryptographic accelerators, secure enclaves, key management)\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Familiarity with high-speed protocols—PCIe Gen 6/7, Ethernet, UALink, or UCI\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience with CMOS nodes (≤7nm)\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Exposure to embedded firmware development or secure firmware boot flows\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience with functional and formal verification at block and chip level\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Familiarity with UVM-based verification methodologies\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Base salary range is $135,000 to $195,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4661550005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4419495005,"location":{"name":"San Jose, CA"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"System Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4661550005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2283","title":"Senior Director System Validation Engineer ","company_name":"Astera Labs","first_published":"2026-02-20T21:02:24-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;Astera Labs is seeking an exceptional \u0026lt;strong\u0026gt;Senior Director System Validation\u0026lt;/strong\u0026gt; to lead our AI Fabric Validation organization. Connectivity is a critical component of every AI accelerator deployment and hyperscale data center architecture. As part of the AI Fabric Engineering group, you will play a key role in ensuring that Astera Labs’ fabric solutions perform at scale and deliver system-level performance across the most demanding AI and ML workloads. This role offers a unique opportunity to shape validation strategy for cutting-edge connectivity silicon and gain deep insight into next-generation AI infrastructure platforms. Your primary responsibility will be to build and lead a world-class validation organization tasked with validating all silicon, firmware, and system-level solutions at scale, ensuring performance, reliability, and production readiness across customer deployments.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Job Description\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Seeking a strong technical leader who has delivered multiple SoC products.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead and scale the system validation organization for Astera Labs\u0026#39; AI fabric portfolio, building a high-performing team across multiple concurrent product programs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Understand the performance and functionality requirements of our AI fabric switches to enable customers to develop Data Center systems using Astera Labs\u0026#39; connectivity products for AI and ML applications.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Own comprehensive validation strategies for AI fabric switch products. Drive execution through scalable automation platforms and data-centric testing with automated reporting and specification compliance verification.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate cross-functionally with Architecture, Hardware, Firmware, and Software teams to influence product requirements and ensure validation excellence.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ensure timely bring‑up of new silicon and platforms, driving root‑cause analysis and cross‑functional debug of hardware, firmware, and system issues.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deliver high‑confidence validation results that support product qualification, customer sampling, and mass production readiness.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Engage directly with key customers to understand their requirements and highlight the unique capabilities of Astera Labs\u0026#39; solutions.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;The ideal candidate brings deep expertise in silicon/system validation, a strong architectural mindset, and a proven ability to scale organizations in fast‑moving, high‑performance computing environments.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work closely with silicon design, architecture, Firmware, software engineering teams to ensure cohesive validation strategies.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive a culture of technical excellence, accountability, and continuous improvement.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Manage resource planning, and vendor/partner relationships.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong academic background in Electrical or Computer Engineering. Bachelor\u0026#39;s required, Master\u0026#39;s preferred.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;≥15 years\u0026#39; experience supporting or developing complex SoC/silicon products for Server, Storage, Networking applications and high‑performance hardware companies.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;≥5 years hands-on experience with Silicon/System bring-up, validation, and debug, including in customer systems.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;≥5 years building high performance Engineering teams and validation methodologies.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep understanding of CPU, GPU, SoC, or AI/ML accelerator architectures, including memory subsystems, I/O, power management, and firmware interactions.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Expertise in validation methodologies: pre‑silicon simulation/emulation, post‑silicon bring‑up, system validation, stress testing, and performance characterization.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong background in debug methodologies, lab infrastructure, and automation frameworks.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent communication skills and ability to influence executives and cross‑functional partners.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;≥8 years leading validation teams planning, execution and maintaining project visibility.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;≥10 years hands-on experience with Silicon/System bring-up, validation, and debug, including in customer systems.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Thorough knowledge of high-speed protocols like PCIe, CXL, NVMe, or Ethernet.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep understanding of High-Speed Signaling Principles and x86/ARM architecture, UEFI/Linux boot sequence.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;The base salary range is $240,000 USD - $300,000 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025528005,"name":"Software Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4703734005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4439574005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose (HQ)","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Firmware Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4703734005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2621","title":"Senior Embedded Software Engineer - Ethernet Retimers","company_name":"Astera Labs","first_published":"2026-06-05T18:38:56-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs\u0026#39; Taurus product line includes Ethernet retimers and gearboxes deployed in active electrical cables and in-system applications at the heart of AI infrastructure. As AI clusters scale to tens of thousands of GPUs connected by high-speed Ethernet fabrics, the firmware running on these connectivity devices is mission-critical — and so is the ability to debug it fast when something breaks.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;We\u0026#39;re looking for a \u0026lt;strong\u0026gt;Firmware Engineer\u0026lt;/strong\u0026gt; who can bridge our system validation team and firmware development organization. When something goes wrong in the lab or in the field, you won\u0026#39;t be waiting on others to dig into the firmware. You\u0026#39;ll be the person in the room who understands both sides — can pull up the code, identify the problem, and fix it. If you\u0026#39;ve worked at a networking company, know how Ethernet actually works from the MAC down through the PHY, have debugged real link failures, and have written or modified firmware or low-level drivers, this role was designed for you.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Your primary focus will be debug and system integration. You will be an integral part of the firmware team and work on new feature development, but you will be the point person in the lab helping to unblock other teams — triaging failures, understanding what the firmware is doing, and making targeted fixes without requiring a long handoff loop. Beyond that, you\u0026#39;ll contribute to feature development and help bring new products from initial bringup into customer deployment.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Debug \u0026amp;amp; System Integration\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Work directly with the system validation team to debug firmware behavior across different Ethernet configurations, link states, and failure modes\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Investigate and fix firmware issues in embedded C, leveraging deep understanding of how Layer 1 PHY, SERDES, FEC/PCS, MAC, and retimer components interact\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Serve as the connective tissue between firmware and system validation teams, triaging issues and driving them to resolution without long handoff loops\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Customer Bring-Up \u0026amp;amp; Field Support\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Support customer bring-up and integration activities, including triaging field issues and coordinating fixes with internal teams\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Partner with field applications engineers to diagnose and resolve deployment issues quickly\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Firmware Feature Development\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Contribute to firmware feature development for SERDES configuration, link training, equalization, and diagnostics\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Partner with SoC, field applications, and platform teams across the full product lifecycle\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Help bring new Taurus products from initial silicon bringup through customer deployment\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;5+ years of experience in firmware development or embedded systems engineering\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Hands-on experience with Ethernet at the system or device level: Layer 1 PHY, SERDES, retimers, gearboxes, NICs, switches, or related devices\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Solid embedded C/C++ skills and comfort working in a firmware codebase on real hardware\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Ability to debug across the hardware/software boundary: register accesses, embedded SDKs, link state machines, PHY telemetry, debug print logs\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Familiarity with Linux development tools: gcc/clang, make, bash, gdb, git\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Strong communication skills and comfort working in a fast-moving environment where the problem in front of you may not have a clean solution\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience with switch or NIC management software, SAI, or OpenBMC\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Knowledge of PMA, FEC, or other PHY-layer subsystems beyond the SERDES\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Background with retimer or gearbox firmware or SDK/API development\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Python scripting for debug, test automation, or data analysis\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience with lab equipment: BERT, oscilloscopes, Viavi/Lecroy/Exfo/Keysight/Tektronix or similar\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Understanding of signal integrity: equalization, jitter, eye diagrams, link margin\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Prior experience mentoring engineers or leading debug efforts across teams\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Salary range is $133,200 to $185,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025528005,"name":"Software Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4649850005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4414096005,"location":{"name":"Israel"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Design Verification","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4649850005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2201","title":"Senior Emulation Engineer","company_name":"Astera Labs","first_published":"2026-01-15T19:52:32-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is establishing a strategic R\u0026amp;amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical \u0026#39;data bottlenecks\u0026#39; enabling the future of AI at scale. As we expand our presence in Israel, we\u0026#39;re seeking a talented \u0026lt;strong\u0026gt;Senior\u0026lt;/strong\u0026gt; \u0026lt;strong\u0026gt;Emulation Engineer\u0026lt;/strong\u0026gt; to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, implementing the emulation strategy for chips that power the world\u0026#39;s largest AI clusters.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As an \u0026lt;strong\u0026gt;Senior Emulation Engineer\u0026lt;/strong\u0026gt;, you will be a core technical driver of our Israel R\u0026amp;amp;D center, working at the intersection of hardware and software to ensure our silicon meets extreme quality and performance targets. You will execute end-to-end emulation flows, bridge the gap between RTL and functional validation, and partner with cross-functional teams to enable seamless hardware-software integration. If you thrive on solving complex technical challenges and want to play a key role in validating cutting-edge AI infrastructure connectivity solutions, this is your opportunity.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Emulation Flow Execution \u0026amp;amp; Implementation\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Execute end-to-end emulation flow from high-level model generation and RTL synthesis to complex system-level testing and silicon-accurate debugging\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Work directly with next-generation emulation platforms (Zebu, Palladium, or Veloce) to implement cutting-edge methodologies\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Maintain and evolve emulation flows to reduce compile times and increase execution speed, directly impacting time-to-market\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;System-Level Debug \u0026amp;amp; Validation\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Drive initial model bring-up process in high-stakes environment, identifying and resolving complex bugs\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Ensure rapid cycles from RTL to functional stability through systematic debug approaches\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Own technical blocks and drive them to completion independently\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional Collaboration\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Partner with Firmware, Software, and Validation teams to debug complex system-level scenarios\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Ensure seamless hardware-software integration for AI infrastructure connectivity\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Collaborate with Design and Verification teams to optimize emulation strategies\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, Computer Engineering, or related technical field\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;3+ years of hands-on experience in Emulation at semiconductor companies\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Deep expertise in emulation flows for large-scale chips using industry-standard emulators (Zebu, Palladium, or Veloce)\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Strong background in SystemVerilog for developing, testing, and debugging complex SoC designs\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience developing and maintaining execution flows for building, running, and debugging emulation models\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\u0026quot;Can-do\u0026quot; approach with ability to own technical blocks and drive them to completion independently\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Master\u0026#39;s degree in Electrical Engineering, Computer Engineering, or related field\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Familiarity with EDA tools for Lint, Clock Domain Crossing (CDC), simulation, and synthesis\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Proficiency in scripting languages such as Python or TCL for automation and flow enhancement\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience with standard debug environments (e.g., Verdi)\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Knowledge of high-speed interface protocols (PCIe, Ethernet, CXL, UALink)\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Background in hardware-software co-verification methodologies\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4008937005,"name":"Israel","location":"Israel","child_ids":[4061058005,4052111005,4056876005],"parent_id":null}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4678683005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4427498005,"location":{"name":"Ho Chi Minh City, Vietnam"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"IC Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4678683005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2424","title":"Senior Engineer, Analog Mixed Signal Layout","company_name":"Astera Labs","first_published":"2026-03-31T02:08:39-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;The company seeks a highly motivated and team-oriented individual to work with both layout and design engineers across multiple time zones\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As an Integrated Circuit Designer - Layout, you will be part of a key team designing and developing sophisticated advanced node CMOS products.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Key Job Duties:\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;The design and development of the layout for integrated circuits according to electronics engineering principles, using software to create design schematics and diagrams. This will include [floor planning, creating layouts of building blocks and integrating layouts for circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs in advanced CMOS nodes. Your focus will include minimizing parasitic and skew, matching, EMIR, and antenna rules on top of DRC and LVS]\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;The management of manufacturing process of the products, including technology yield and performance of the products.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;The development of test programmes and procedures to ensure the products meet their performance specifications.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;The provision of advice on aspects of semiconductor process technology and maintain and repair semiconductor process equipment.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Basic Qualifications:\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;At least a bachelor’s degree in electrical engineering\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Required Experience:\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;4+ years of experience in the development of layouts for highspeed analog IC designs in fin FET technology.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with layout extraction tools and to analyzing layout parasitic to achieve high quality layout for highspeed circuits.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;EMIR and antenna DRC rules aware layout practices.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience writing SKILL and TCL scripts is highly recommended\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Pay and Benefits\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Competitive salary.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;13th month salary.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Performance bonus each year.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Long Term Incentive (LTI)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Health check each year.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Insurance for engineer and family.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lunch Allowance.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Company trips.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4135671005,"name":"SerDes","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4053944005,"name":"Ho Chi Minh City","location":"Ho Chi Minh City, Ho Chi Minh City, Vietnam","child_ids":[],"parent_id":4053943005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4695626005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4435939005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose (HQ)","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Firmware Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4695626005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2554","title":"Senior Firmware Engineer","company_name":"Astera Labs","first_published":"2026-05-15T13:45:47-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;h4\u0026gt;Job Description\u0026lt;/h4\u0026gt;\n\u0026lt;p\u0026gt;The mission of this role is to architect and develop firmware and microcontroller subsystems for Astera Labs’ SoC and systems products. Firmware is responsible for implementing the major differentiating features of Astera Labs’ products. As such, firmware is considered equally important to the hardware, and the firmware team is often customer-facing accordingly to ensure the needs of the customer are fully comprehended.\u0026lt;/p\u0026gt;\n\u0026lt;h4\u0026gt;Basic Qualifications\u0026lt;/h4\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong academic and technical background in electrical engineering. At a minimum, a Bachelor’s in EE or Computer Science is required, and a Master’s is preferred.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;5+ years of experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience developing firmware to execute in on-chip microcontrollers as well as C-language software development kits (SDKs) to execute on system management controllers (e.g. BMC).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience working with logic designers to architect and verify HW-SW interfaces on complex SoCs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer meetings in advance, and to work with minimal guidance and supervision.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h4\u0026gt;Required Experience\u0026lt;/h4\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience developing embedded firmware for PCIe products.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;MQX RTOS or ThreadX Development or enablement.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;High level of proficiency in C (preferred) or C++, including development of C-based SDKs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;High level of proficiency in Python for automating pre-processors/post-processors and FW QC.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Working knowledge of software/firmware build environments, gcc/Make, Doxygen, and GitHub.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience with Server, Storage, and/or Networking equipment (e.g. Network Switches).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with SoC interfaces to common IP blocks such as PCIe Controllers, NVME Controllers, AMBA/AHB interfaces, on-chip memory interfaces, and other similar interfaces\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Direct experience working on products with high-speed interfaces common in Data Center equipment: PCI- Express (Gen-3 and above), 100/400G Ethernet, Infiniband, NVMe, etc\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;h4\u0026gt;Preferred Experience\u0026lt;/h4\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience developing firmware to execute in on-chip microcontrollers as well as C-language SDKs to execute on system management controllers (e.g. BMC)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with industry forums and collaboration workgroups such as OCP and OpenBMC\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;The base salary range is $160,000.00 USD – $190,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025528005,"name":"Software Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4701247005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4438345005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose (HQ)","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Firmware Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4701247005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2598","title":"Senior Firmware Engineer","company_name":"Astera Labs","first_published":"2026-05-29T20:45:32-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is seeking a \u0026lt;strong\u0026gt;Senior Firmware Engineer\u0026lt;/strong\u0026gt; to develop and deliver core firmware for our next-generation connectivity, chiplet, and system products. Firmware is a core differentiator for Astera Labs’ products and is treated as a first-class engineering discipline, on par with hardware and silicon design.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Architect, develop, and maintain bare-metal and low-level firmware running on embedded microcontrollers within Astera Labs SoCs and systems.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Design and implement device drivers, core firmware services, and hardware abstraction layers for high-speed connectivity products.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Define and implement HW-SW interfaces in close collaboration with RTL, PD, and Architecture teams.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead bring-up, debug, and validation of firmware on silicon and system platforms.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop and maintain C/C++ firmware codebases, SDKs, and supporting infrastructure.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Build automation, tooling, and diagnostics using Python and scripting frameworks.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Participate in system-level debug involving PCIe, Ethernet, memory subsystems, and interconnect fabrics.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support customer enablement, integration, and escalations as needed.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field (Master’s preferred).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong fundamentals in embedded systems, computer architecture, and low-level software.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven experience developing firmware for complex SoC or silicon-based products in Server, Storage, Networking, or Accelerator environments.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency in C (required); C++ experience is a plus.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ability to work cross-functionally in a fast-paced, highly technical environment.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bare-metal or RTOS-based firmware development (e.g., ThreadX, MQX, or equivalent).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Firmware development for on-chip microcontrollers and supporting SDKs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong debugging skills across hardware, firmware, and system layers.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with firmware build systems and tooling (gcc, Make, Git, Doxygen).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Python scripting for automation, validation, or tooling.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience with server, storage, or networking systems.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Experience / Nice to Have\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Firmware development for PCIe or Ethernet switch products.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Exposure to BMCs, OpenBMC, or system management firmware.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with high-speed interfaces such as:\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;PCIe (Gen3+)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ethernet (100G / 400G+)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;NVMe, Infiniband\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Participation in industry forums or ecosystems (e.g., OCP, OpenBMC).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Customer-facing or field-enablement experience.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Salary range is\u0026amp;nbsp;$160,000 to $195,000 depending on experience, level, and business need. This role is eligible for discretionary bonus, incentives, and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025528005,"name":"Software Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4692812005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4434214005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose (HQ)","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Firmware Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4692812005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2510","title":"Senior Firmware Engineer - PCIe/CXL Memory Solutions","company_name":"Astera Labs","first_published":"2026-05-09T15:07:11-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;Astera Labs is seeking experienced \u0026lt;strong\u0026gt;Senior\u0026lt;/strong\u0026gt; \u0026lt;strong\u0026gt;Firmware Engineer PCIe/CXL Memory Solution \u0026lt;/strong\u0026gt;to lead the design and development of embedded firmware for cutting-edge \u0026lt;strong\u0026gt;PCIe/CXL memory expansion products\u0026lt;/strong\u0026gt; tailored for AI and Cloud infrastructure. This role is pivotal in enabling next-generation memory devices that power high-performance computing platforms. This position will be required onsite.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Experience:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s degree in Electrical Engineering, Computer Science, or a related technical field.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;5+ years of hands-on experience in embedded firmware development using C.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep expertise in low-level firmware for hardware bring-up, traffic enablement, and RAS (Reliability, Availability, Serviceability) feature implementation.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven track record working with high-speed interfaces and protocols such as PCIe, CXL, DDR, and I2C.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands on experience in CPU to Device, Device to Device flows like MMIO, DMA, PCIe P2P.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities \u0026amp;amp; Skills:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Firmware development, bring-up, and validation of PCIe/CXL/DDR interfaces at PHY and Link layers.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Interpret technical specifications and develop robust, low-level C code in RTOS environments.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate effectively with cross-functional teams and external partners to deliver weekly firmware releases and feature demonstrations.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong debugging skills and ability to triage and resolve issues in complex embedded systems.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with server I/O and memory workflows, performance tuning for latency and bandwidth optimization is a plus.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with pre-silicon validation in emulation environments is desirable.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;p\u0026gt;The base salary range is 147,000 USD - 165,000 USD for Senior, 175,000 USD - 195,000 USD for Staff, 203,000 USD - 230,000 USD for Principal.\u0026amp;nbsp;Your base salary will be determined based on your relevant experience and the pay of employees in similar positions. This role may be eligible for discretionary bonus, equity, and employee benefits.\u0026lt;/p\u0026gt;\n\u0026lt;/div\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025528005,"name":"Software Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4700342005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4438091005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose (HQ)","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Engineering Operations","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4700342005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2596","title":"Senior Foundry Engineer, Silicon Technology","company_name":"Astera Labs","first_published":"2026-06-04T12:30:26-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;div data-ogsc=\u0026quot;black\u0026quot;\u0026gt;\u0026lt;strong data-ogsc=\u0026quot;\u0026quot; data-olk-copy-source=\u0026quot;MessageBody\u0026quot;\u0026gt;Job Description\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;div data-ogsc=\u0026quot;black\u0026quot;\u0026gt;We are seeking a \u0026lt;strong\u0026gt;Senior Foundry Engineer, Silicon Technology \u0026lt;/strong\u0026gt;to support foundry engagement, silicon-to-model correlation, tapeout readiness, and yield improvement for advanced semiconductor products. This person will work closely with internal design, CAD layout, product engineering, test, reliability, operations teams and external foundry partners to identify risks, assess product impact, and drive timely resolution of process, PDK, model, DRC/DFM, and silicon-related issues.\u0026lt;/div\u0026gt;\n\u0026lt;div data-ogsc=\u0026quot;black\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/div\u0026gt;\n\u0026lt;div data-ogsc=\u0026quot;black\u0026quot;\u0026gt;\u0026lt;strong data-ogsc=\u0026quot;\u0026quot;\u0026gt;Responsibilities Include\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-ogsc=\u0026quot;black\u0026quot;\u0026gt;Silicon, process and yield correlation\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-ogsc=\u0026quot;black\u0026quot;\u0026gt;Analyze process inline data, silicon test data, process drift and process correlation data\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li data-ogsc=\u0026quot;black\u0026quot;\u0026gt;Fine tune processes to optimize power, performance and yield\u0026lt;/li\u0026gt;\n\u0026lt;li data-ogsc=\u0026quot;black\u0026quot;\u0026gt;Help identify process related contributors to parametric drift, yield loss, leakage, reliability risk\u0026lt;/li\u0026gt;\n\u0026lt;li data-ogsc=\u0026quot;black\u0026quot;\u0026gt;Work with foundry and internal teams to investigate yield issues and process excursions\u0026lt;/li\u0026gt;\n\u0026lt;li data-ogsc=\u0026quot;black\u0026quot;\u0026gt;Perform layout analysis where needed to understand process sensitivity, failures\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li data-ogsc=\u0026quot;black\u0026quot;\u0026gt;Tapeout and DFM support\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-ogsc=\u0026quot;black\u0026quot;\u0026gt;Support product tapeouts, tapeout readiness reviews from a PDK, DRC/DFM, device model and reliability perspective\u0026lt;/li\u0026gt;\n\u0026lt;li data-ogsc=\u0026quot;black\u0026quot;\u0026gt;Run or coordinate DFM checks on products and summarize findings for design and layout teams\u0026lt;/li\u0026gt;\n\u0026lt;li data-ogsc=\u0026quot;black\u0026quot;\u0026gt;Coordinate between foundry and physical design teams to disposition waivers taking performance, leakage, manufacturability and reliability in mind\u0026lt;/li\u0026gt;\n\u0026lt;li data-ogsc=\u0026quot;black\u0026quot;\u0026gt;Document known PDK, model, DRC, DFM or process risks before tapeout\u0026lt;/li\u0026gt;\n\u0026lt;li data-ogsc=\u0026quot;black\u0026quot;\u0026gt;Maintain an internal PDK qualification database across foundries and process nodes to reduce tapeout risk from unnoticed PDK or model changes\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li data-ogsc=\u0026quot;black\u0026quot;\u0026gt;Foundry and PDK support\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-ogsc=\u0026quot;black\u0026quot;\u0026gt;Support technical interactions with foundry partners on PDK, device models, process assumptions, design rules, DRC/DFM decks and reliability collateral\u0026lt;/li\u0026gt;\n\u0026lt;li data-ogsc=\u0026quot;black\u0026quot;\u0026gt;Track PDK versions, model updates, DRC/DFM runset changes, and foundry signoff recommendations\u0026lt;/li\u0026gt;\n\u0026lt;li data-ogsc=\u0026quot;black\u0026quot;\u0026gt;Compare PDK changes across versions and summarize potential design, layout, model or signoff impact\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li data-ogsc=\u0026quot;black\u0026quot;\u0026gt;Device model and circuit model evaluation\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-ogsc=\u0026quot;black\u0026quot;\u0026gt;Validate model behavior across voltage bias, temperature, process corners, and relevant operating conditions\u0026lt;/li\u0026gt;\n\u0026lt;li data-ogsc=\u0026quot;black\u0026quot;\u0026gt;Compare silicon measurements against SPICE/model predictions and help identify model gaps\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;div data-ogsc=\u0026quot;black\u0026quot;\u0026gt;\u0026lt;strong data-ogsc=\u0026quot;\u0026quot;\u0026gt;Basic Qualifications:\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-ogsc=\u0026quot;black\u0026quot;\u0026gt;B.S or M.S in Electrical Engineering, Material science, Semiconductor engineering or a related technical field\u0026lt;/li\u0026gt;\n\u0026lt;li data-ogsc=\u0026quot;black\u0026quot;\u0026gt;5+ years of experience in semiconductor device engineering, foundry interface, silicon technology, process integration, yield/process correlation\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;div data-ogsc=\u0026quot;black\u0026quot;\u0026gt;\u0026lt;strong data-ogsc=\u0026quot;\u0026quot;\u0026gt;Required Experience:\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-ogsc=\u0026quot;black\u0026quot;\u0026gt;Working knowledge of semiconductor process flows, device physics, manufacturability, reliability and yield drivers\u0026lt;/li\u0026gt;\n\u0026lt;li data-ogsc=\u0026quot;black\u0026quot;\u0026gt;Experience supporting tapeouts, PDK validation, models, DRC/DFM, silicon bring up\u0026lt;/li\u0026gt;\n\u0026lt;li data-ogsc=\u0026quot;black\u0026quot;\u0026gt;Experience analyzing silicon, wafer-level, process monitors, product test, characterization, or reliability data\u0026lt;/li\u0026gt;\n\u0026lt;li data-ogsc=\u0026quot;black\u0026quot;\u0026gt;Prior experience at a foundry, IDM, fabless semiconductor company or a PDK/enablement organization\u0026lt;/li\u0026gt;\n\u0026lt;li data-ogsc=\u0026quot;black\u0026quot;\u0026gt;Familiarity with SPICE models, process corners, device behavior, layout effects and silicon-to-model correlation\u0026lt;/li\u0026gt;\n\u0026lt;li data-ogsc=\u0026quot;black\u0026quot;\u0026gt;Ability to communicate technical issues clearly across design, CAD, layout, test, products engineering and external foundries\u0026lt;/li\u0026gt;\n\u0026lt;li data-ogsc=\u0026quot;black\u0026quot;\u0026gt;Familiarity with using TSMC as a foundry\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;div data-ogsc=\u0026quot;black\u0026quot;\u0026gt;\u0026lt;strong data-ogsc=\u0026quot;\u0026quot;\u0026gt;Preferred Experience:\u0026lt;/strong\u0026gt;\u0026lt;/div\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-ogsc=\u0026quot;black\u0026quot;\u0026gt;Experience with advanced FinFET, gate-all-around/nanosheet technologies and BiCMOS technologies\u0026lt;/li\u0026gt;\n\u0026lt;li data-ogsc=\u0026quot;black\u0026quot;\u0026gt;Experience with SRAM, analog/mixed signal, RF, Serdes, low power design constraints\u0026lt;/li\u0026gt;\n\u0026lt;li data-ogsc=\u0026quot;black\u0026quot;\u0026gt;Experience benchmarking foundry nodes using spice models on representative circuits\u0026lt;/li\u0026gt;\n\u0026lt;li data-ogsc=\u0026quot;black\u0026quot;\u0026gt;\n\u0026lt;div data-ogsc=\u0026quot;\u0026quot;\u0026gt;Experience using foundry models to simulate junction breakdowns, SOA, ESD, aging, reliability or device operating limits\u0026lt;/div\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4678168005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4427225005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Human Resources","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4678168005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2419","title":"Senior HR Business Partner, Business and G\u0026A","company_name":"Astera Labs","first_published":"2026-03-27T11:10:19-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is seeking a \u0026lt;strong\u0026gt;Senior HR Business Partner\u0026lt;/strong\u0026gt; to join our People team in San Jose, CA. In this high-impact role, you will partner directly with leaders across our Business and G\u0026amp;amp;A functions—including Finance, Legal, Operations, and other corporate teams—serving as a trusted advisor on all things people strategy.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This is an exceptional opportunity for someone who thrives on working closely with senior stakeholders, navigating real complexity, and helping organizations scale thoughtfully during a period of hypergrowth.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As a key member of our HR team, you will operate with support from HR Operations and Centers of Excellence while driving meaningful impact on organizational effectiveness, talent development, and leadership capability across the company.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Strategic Business Partnership\u0026lt;/strong\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Act as a trusted partner to senior leaders, advising on organizational design, leadership effectiveness, workforce planning, and succession planning\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Help leaders translate business priorities into clear people strategies and actionable plans\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Build strong, credible relationships where leaders rely on your judgment—not just your availability\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Organizational Effectiveness \u0026amp;amp; Talent Strategy\u0026lt;/strong\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Support org effectiveness\u0026lt;/span\u0026gt;, role clarity, and succession planning for critical and leadership roles\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Partner with leaders on headcount planning and trade-offs, balancing execution needs, and long-term capability building\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead talent reviews, retention planning, and hotspot analysis, ensuring insights turn into action\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Coach managers and senior leaders on performance management, development conversations, and leadership effectiveness\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Performance, Rewards \u0026amp;amp; Employee Relations\u0026lt;/strong\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Advise leaders through performance cycles, calibration, and compensation reviews, ensuring fair, consistent, and well-reasoned outcomes\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Handle employee relations matters—including performance issues, conflict, and conduct concerns—using sound judgment and strong documentation\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Partner closely with Employment Counsel, Legal, and HR Operations on complex or high-risk situations\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Provide leaders with clear, empathetic, and practical guidance on sensitive people matters\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Operational Excellence \u0026amp;amp; Scalability\u0026lt;/strong\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Identify people or structural risks early and work with leaders to address them proactively\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Help shape how HR practices scale by partnering with HR Ops and Centers of Excellence to simplify, standardize, or move work to the right owners\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Take initiative to spot gaps, propose solutions, and drive progress—operating with an owner\u0026#39;s mindset\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor\u0026#39;s degree in Human Resources, Business Administration, Organizational Development, or related field\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;8+ years of experience as an HR Business Partner supporting senior leaders in complex, fast-growing technology organizations\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Demonstrated experience partnering across both product/engineering and corporate functions\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven ability to operate in ambiguous environments where not everything is fully defined\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Clear, confident communicator who can influence at all levels of the organization\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience in semiconductor, hardware, or AI infrastructure industries\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Track record of supporting organizations through rapid scaling or hypergrowth phases\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong analytical skills with experience using people data to drive decisions\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Salary range is $133,200 to $185,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4000202005,"name":"HR","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4679389005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4427874005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Human Resources","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4679389005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2431","title":"Senior HR Business Partner, Engineering","company_name":"Astera Labs","first_published":"2026-03-30T20:25:36-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Role Overview\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Astera Labs is seeking a\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Senior HR Business Partner\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026amp;nbsp;to join our People team in San Jose, CA. In this high-impact role, you will partner directly with engineering organizations—serving as a trusted advisor, coach, and strategic partner to engineering leaders, managers, and employees across our technical teams.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;You will bring deep HRBP/Generalist experience, strong employee relations expertise, and substantial knowledge of US labor and employment law to ensure our people practices are both effective and compliant as we scale. This role is critical to supporting the talent strategies, people leader development, and organizational health that enable our engineering teams to deliver world-class AI infrastructure connectivity products.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;1. Engineering Partnership \u0026amp;amp; Coaching\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Serve as a trusted partner to engineering\u0026amp;nbsp;people leaders, providing hands-on coaching on people management, team dynamics, and leadership effectiveness\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Build strong relationships across all levels\u0026amp;nbsp;ensuring employees and managers have accessible, credible HR support\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Coach engineering managers on performance conversations, career development discussions, feedback delivery, and navigating difficult team situations\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Help translate the unique challenges of semiconductor product development into practical people strategies\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;2. Employee Relations \u0026amp;amp; Compliance\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Serve as the primary point of contact for employee relations matters across supported engineering groups, handling investigations, performance issues, interpersonal conflict, and conduct concerns with professionalism and care\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Apply strong knowledge of\u0026amp;nbsp;North America\u0026amp;nbsp;labor and employment law—including federal, state, and local regulations—to advise leaders and ensure compliant, defensible people decisions\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Conduct thorough, fair, and well-documented workplace investigations, partnering with Employment Counsel and Legal on complex or high-risk matters\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Proactively\u0026amp;nbsp;identify\u0026amp;nbsp;compliance risks and partner with HR Operations to ensure policies, practices, and manager actions align with legal requirements\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Stay current on evolving employment legislation and regulatory changes, advising leaders on implications and necessary adjustments\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Provide clear, empathetic, and legally sound guidance to managers navigating terminations, leaves of absence, accommodations, and other sensitive situations\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;3. Talent Strategy \u0026amp;amp; Organizational Effectiveness\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Partner with engineering leaders on organizational design, role clarity, and team structure to support product roadmap execution\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Lead talent reviews, retention planning, and succession planning for critical technical roles\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Support headcount planning and workforce decisions, balancing near-term delivery needs with long-term capability building\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Identify\u0026amp;nbsp;talent risks and hotspots early, working proactively with leaders to address retention and engagement challenges\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;4. Performance Management\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Guide leaders and managers through performance cycles, calibration sessions, and compensation reviews with fair, consistent, and well-reasoned recommendations\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Ensure performance management practices are applied consistently and in compliance with company policy and legal standards\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Partner with Compensation and HR Operations to support\u0026amp;nbsp;equitable\u0026amp;nbsp;pay decisions and address compensation-related concerns\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;5. Operational Excellence \u0026amp;amp; Scalability\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Identify\u0026amp;nbsp;gaps in people processes or manager capability and proactively propose solutions\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Partner with HR Ops and Centers of Excellence to simplify, standardize, and scale HR practices as the engineering organization grows\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Operate with an owner\u0026#39;s mindset—taking accountability for outcomes, not just recommendations\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Basic Qualifications\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Human Resources, Business Administration, Organizational Development, or related field\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;8+ years of HR Business Partner\u0026amp;nbsp;experience\u0026amp;nbsp;supporting engineering or technical organizations\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Demonstrated experience in\u0026amp;nbsp;supporting engineering organizations\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Strong knowledge of\u0026amp;nbsp;North America\u0026amp;nbsp;employment\u0026amp;nbsp;and labor law, including federal and California state regulations (wage and hour, leaves, accommodations, terminations, harassment/discrimination)\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Proven\u0026amp;nbsp;track record\u0026amp;nbsp;handling complex employee relations matters, workplace investigations, and sensitive personnel issues\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Demonstrated ability to coach managers and build trusted relationships with technical employees at all levels\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;7\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Strong judgment and comfort\u0026amp;nbsp;operating\u0026amp;nbsp;in fast-paced, ambiguous environments\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;8\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Clear, confident communicator who can influence and advise engineering leaders effectively\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Preferred Qualifications\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; 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data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience supporting organizations through rapid scaling or hypergrowth phases\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; 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data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Strong analytical skills with experience using people data to inform talent decisions\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Track record\u0026amp;nbsp;of developing manager capability and building coaching cultures within engineering organizations\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience in AI, data center, or connectivity-focused technology companies\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233279\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:0,\u0026amp;quot;335559740\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Salary range is $133,200 to $185,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4000202005,"name":"HR","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4699439005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4437669005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose (HQ)","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Quality Assurance","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4699439005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2588","title":"Senior Lab Validation Engineer","company_name":"Astera Labs","first_published":"2026-06-03T18:45:24-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;As an Astera Labs \u0026lt;strong\u0026gt;Senior\u0026amp;nbsp;Lab Validation Engineer\u0026lt;/strong\u0026gt;, you will take a hands-on role to find the root cause of any customer quality concerns and develop corrective actions.\u0026amp;nbsp; You will:\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Directly root-cause failures to the circuit, package, firmware, or protocol-level interactions. \u0026amp;nbsp;Collaborate with design, validation, and system engineering teams as needed.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Modify device firmware to test out engineering theories leading to potential fixes or production screens.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Investigate failures such as link training issues, lane margining failures, eye closure, jitter sensitivity, protocol errors, and interoperability problems.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Debug retimer specific failures, including pass-through path issues, clock forwarding problems, equalization settings, and link bring-up reliability.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Analyze high speed link failures, including lane mapping, bifurcation errors, hot-plug issues, compliance test failures, and error propagation across multiple ports.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Use advanced lab instrumentation (BERT, high-bandwidth oscilloscopes, protocol analyzers, VNAs, TDR, spectrum analyzers) to characterize and isolate failures.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop and run stress tests and margining experiments to identify weak design or process corners.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Provide feedback on system-level integration challenges for retimers and PCIe switches (e.g., board layout, equalization tuning, firmware interactions).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive physical failure analysis to isolate and image defects using methods such as fault isolation, probing, de-processing, FIB, thermal/voltage stress testing.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Document debug findings, propose design/process/test improvements, and contribute to FA methodologies.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Participate in new product development process to ensure readiness for customer returns before products are launched. Collaborating in the development of evaluation hardware (boards and sockets, including FA friendly sockets) and scripts.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic qualifications:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Minimum of a Bachelor’s in Electrical Engineering while a Master’s degree is preferred.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Minimum of 5 years relevant experience of which 5 years’ is hands-on mixed high-speed lab experience working with equipment such as protocol analyzers, BERT, real-time scopes, sampling scopes, TDR, and VNA.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Python programming.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep understanding of PCIe protocol (up through Gen6), retimer architecture, and SerDes signal integrity.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience debugging retimers (equalization tuning, pass-through mode, clocking, reset/link sequencing).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience debugging PCIe switches (lane bifurcation, hot-plug, multi-port link stability, compliance failures).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong background in NRZ/PAM4 architectures, investigating issues with jitter, CDR/PLL behavior, equalization (DFE, CTLE, FFE), crosstalk, and power integrity.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience in post-silicon validation and bring-up of high-speed PHYs or retimers.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Solid problem-solving and analytical skills with ability to narrow down complex multi-layer failures.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong written and verbal communication skills.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred experience (ideal candidate has some of this, but OJT is also possible)\u0026lt;/strong\u0026gt;:\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;C (not C++).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with optics.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with chip-level security and RAS features.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;ATE (Automated Test Equipment) Advantest V93K.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Understanding of system-level architecture for servers, storage, and AI/ML platforms where PCIe retimers/switches are deployed.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Based in San Jose, this position requires an in-person presence, offering a unique opportunity to impact our global operations directly.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;The base salary range is $160,000 USD - $195,000 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4011733005,"name":"Quality","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4678056005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4427164005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Business Operations","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4678056005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2415","title":"Senior Manager of Corporate Development","company_name":"Astera Labs","first_published":"2026-03-28T15:36:13-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Are you passionate about driving strategic growth through impactful corporate development initiatives in the AI and cloud infrastructure space? Astera Labs is seeking a Senior Manager of Corporate Development to lead and support strategic transactions including acquisitions, investments, and strategic partnerships that will shape the future of AI connectivity.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;In this high-visibility role, you will report to the Head of Corporate Development and work closely with cross-functional teams including engineering, product management, and executive leadership to identify and evaluate opportunities that align with Astera Labs\u0026#39; long-term growth strategy. You will be at the forefront of emerging AI infrastructure technologies, developing new business models and driving transactions that accelerate our position as the leader in purpose-built connectivity solutions.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This is a unique opportunity to join a hyper-growth company at the intersection of semiconductors and AI infrastructure, where your work will directly influence strategic decisions and contribute to building the connectivity backbone powering the next generation of data centers.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Strategic Transaction Leadership\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Lead and support corporate development transactions through all phases of the transaction lifecycle, from target identification through close\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Partner with executive and engineering leaders to evaluate opportunities that address strategic gaps and conduct build/buy/partner analysis\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Lead deal-oriented project management throughout the entire deal lifecycle, ensuring timely execution and stakeholder alignment\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Financial \u0026amp;amp; Strategic Analysis\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Conduct detailed financial analyses including valuation, pro forma modeling, and investment assessments to evaluate deal alignment\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Develop executive presentation materials to provide recommendations to the leadership team and board\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Research adjacent and new market opportunities, including opportunity sizing, target landscaping, and competitive analysis\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional Collaboration \u0026amp;amp; Integration\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Collaborate with cross-functional teams to drive diligence and validate key assumptions and value drivers\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Oversee post-merger integration to ensure deals deliver long-term success and structural enhancement for the company\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Define and continually enhance the company\u0026#39;s strategy to acquire new business opportunities and partnerships\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Market Intelligence\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Develop deep expertise in emerging AI infrastructure technologies, companies, and business models\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Monitor industry trends and competitive dynamics to inform corporate development strategy\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Business Administration, Electrical Engineering, Computer Science, or related field\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;8+ years of experience in corporate development, investment banking, private equity, venture capital, or related roles\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience in the semiconductor, high-tech, or AI infrastructure industry\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Demonstrated experience leading strategic transactions and working with executive leadership\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Strong analytical skills with expertise in valuation, financial modeling, and strategic analysis\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Excellent communication and presentation skills with the ability to convey complex concepts clearly to diverse audiences\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;MBA or advanced degree\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Direct experience with M\u0026amp;amp;A transactions in the semiconductor or data center infrastructure space\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Knowledge of AI/ML infrastructure, PCIe, CXL, or Ethernet technologies\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Proven ability to collaborate effectively across engineering and business functions\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience with post-merger integration planning and execution\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Willingness to travel as needed for deals, company training, industry events, and conferences\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Salary range is $170,500 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4144039005,"name":"Corporate Development","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4660309005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4418969005,"location":{"name":"Singapore"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Physical Design/DFT","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4660309005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2278","title":"Senior Physical Design Engineer","company_name":"Astera Labs","first_published":"2026-02-10T17:20:42-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;About the Role\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;We are seeking a Senior Physical Design Engineer to join our high-performance design team working on next-generation transceiver IPs targeting the TSMC 5nm, 3nm technology node.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;In this role, you will take ownership of physical implementation from RTL to GDSII, ensure timing and power closure for ultra-high-speed designs, and collaborate closely with cross-functional teams to resolve challenges unique to advanced nodes and multi-gigabit transceiver architectures.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt; \u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Perform full-chip and block-level physical implementation including floor planning, placement, clock tree synthesis (CTS), routing, and physical verification for high-speed designs in TSMC 3nm.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with RTL and STA teams to ensure clean handoffs and convergent timing, area, and power.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work on advanced physical design techniques to support multiple voltage/frequency domains, hierarchical design, and physical-aware synthesis.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Handle advanced physical design topics:\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;EM/IR analysis and power grid optimization\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Congestion analysis and mitigation\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Clock domain crossing and skew optimization\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;RC extraction-aware placement and routing\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;Integrate IPs and top-level blocks with attention to physical interfaces, constraints, and timing alignment.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Participate in defining floorplan strategy and chip partitioning for multi-gigabit transceivers.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Perform ECO implementation and support tapeout signoff activities.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ensure DRC/LVS/ANT/CELL/ERC clean database using industry-standard physical verification tools.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Use industry-standard tools (e.g., ICC2, Innovus, Voltus, RedHawk, Calibre) for implementation and signoff.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop and maintain automation scripts (Tcl, Python, Perl) for physical design flows and regressions.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt; \u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, or related field.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;4+ years of experience in physical design with advanced technology nodes (preferably ≤ 5nm).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong experience with:\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Floor planning, placement, CTS, routing, and IR drop mitigation\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Signoff checks (DRC/LVS/ANT/ERC) and debugging\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Timing closure collaboration with STA team\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience with tools such as Synopsys ICC2, Cadence Innovus, Calibre, Voltus.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience in integrating high-speed IPs (e.g., SerDes, PHYs) into SoC or chiplet environments.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience in high frequence data path, DSP designs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Solid scripting skills for automation and productivity enhancement.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4135671005,"name":"SerDes","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4050465005,"name":"Singapore","location":"Singapore","child_ids":[4061059005,4052115005],"parent_id":null}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4702286005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4438937005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose (HQ)","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Sales Operations","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4702286005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2615","title":"Senior Pricing Manager","company_name":"Astera Labs","first_published":"2026-06-03T13:19:33-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-olk-copy-source=\u0026quot;MessageBody\u0026quot;\u0026gt;About Astera Labs\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) is a pioneering fabless semiconductor company headquartered in Silicon Valley, driving the evolution of AI and cloud infrastructure through purpose-built connectivity solutions. As a leader in rack-scale architecture, Astera Labs is enabling the shift to AI Infrastructure 2.0, where compute is optimized at the rack level to support next-generation workloads. Our portfolio spans high-performance silicon, software, and system-level solutions that address critical bottlenecks in data movement across compute, memory, and networking domains. We are committed to open standards, continuous innovation, and building a collaborative environment to solve complex challenges at scale.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Astera Labs is seeking a Senior Pricing Manager to lead pricing strategy, governance, and execution across our product portfolio. This role will define how we price products and solutions, improve revenue and margin outcomes, and influence cross-functional decision-making through market insight, analytics, and commercial leadership.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;The ideal candidate brings deep pricing expertise and the ability to lead complex pricing initiatives, guide cross-functional stakeholders across Sales, Marketing, Operations, Product, and Finance, and turn market and financial data into strategic pricing decisions.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;A Day in the Life\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;In this role, you will operate at the center of Astera Labs’ commercial decision-making, helping shape how we price products, structure offers, and balance growth with profitability. You will work across Product Management, Sales, Finance, Revenue Operations, and Operations to evaluate new pricing opportunities, support product launches, and improve pricing consistency across the business. Your day may include building pricing models, analyzing discounting patterns, reviewing competitive and market signals, and preparing recommendations for executive decisions. You may also partner with Sales on customer negotiations, assess deal performance and price realization, and help operationalize pricing changes so they are scalable and measurable. This is a highly cross-functional role that requires strong judgment, analytical rigor, and the ability to bring structure and transparency to complex pricing decisions while enabling teams to move faster with clearer trade-offs.\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul type=\u0026quot;disc\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Own and evolve pricing strategy for products, solutions, and commercial programs\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Build and maintain pricing models, business cases, and scenario analyses\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Partner with Product Management, Operations, and Finance on new product pricing, packaging, and margin targets\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Analyze customer, market, and competitive data to identify pricing opportunities and risks\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Evaluate discounting patterns, deal performance, and price realization to improve commercial discipline\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Lead or support customer price negotiations in partnership with Sales, balancing revenue growth, margin goals, and strategic account priorities\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Develop recommendations for list pricing, promotional pricing, segmentation, and policy changes\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Support executive reviews with clear analysis, insights, and recommendations\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Establish pricing governance, processes, and performance tracking\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Work closely with Sales and Revenue Operations to ensure pricing changes are operationalized effectively\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Monitor pricing performance against revenue, margin, win rate, and adoption goals\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul type=\u0026quot;disc\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Bachelor’s degree in Business, Finance, Economics, Engineering, or a related field\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;6+ years\u0026lt;/strong\u0026gt;\u0026amp;nbsp;of experience in pricing, strategy, finance, product marketing, or business analytics\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Strong analytical and financial modeling skills\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Experience with pricing strategy, segmentation, packaging, and discount analysis\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Ability to synthesize data into actionable business recommendations\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Strong Excel and presentation skills; experience with BI and analytics tools\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Excellent cross-functional communication and stakeholder management skills\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Comfortable working in a fast-paced environment with evolving priorities\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul type=\u0026quot;disc\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Experience in AI infrastructure, semiconductor, hardware, or enterprise technology\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Familiarity with AI market dynamics, semiconductor pricing considerations, cost-to-serve, value-based pricing, and competitive pricing frameworks\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Experience supporting product launches or go-to-market decisions\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;MBA or advanced degree is a plus\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Why Join Us?\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul type=\u0026quot;disc\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Help define and scale pricing strategy for a company at the forefront of AI infrastructure\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Influence high-impact commercial decisions across product lines and strategic accounts\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Partner closely with senior stakeholders across Sales, Product, Finance, Operations, and Revenue Operations\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Drive measurable impact on revenue, margin, pricing consistency, and decision quality\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_xmsonormal\u0026quot;\u0026gt;Competitive compensation, equity, and benefits\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4000197005,"name":"Sales","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4672620005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4424476005,"location":{"name":"San Jose, CA"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Digital Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4672620005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2361","title":"Senior Principal Digital Design Engineer ","company_name":"Astera Labs","first_published":"2026-03-12T15:00:10-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;br\u0026gt;Astera Labs is seeking a \u0026lt;strong\u0026gt;Senior Principal Digital Design Engineer\u0026lt;/strong\u0026gt; to drive the architecture and implementation of next-generation digital designs powering AI infrastructure connectivity. This is a high-impact technical leadership role where you\u0026#39;ll define micro-architecture strategies for better power, performance and area tradeoff, own complex chip-level design decisions, and guide multiple blocks from concept through silicon bring-up for industry-leading products supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As a senior technical leader, you\u0026#39;ll shape design methodologies, mentor engineering teams, and collaborate cross-functionally with verification, physical design, DFT, and post-silicon teams to deliver high-performance, production-quality silicon. You\u0026#39;ll also influence roadmap decisions and drive design excellence across the organization, ensuring Astera Labs continues to set the standard for AI connectivity solutions.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Architecture \u0026amp;amp; Technical Leadership\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Define and drive micro-architecture for complex digital blocks and subsystems across multiple product lines\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Establish architectural standards and best practices that scale across the design organization\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Provide technical guidance and decision-making on critical design trade-offs impacting performance, power, and area\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Design Execution \u0026amp;amp; Ownership\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Lead RTL implementation of complex designs from architecture definition through GDS and silicon bring-up\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive timing constraints and closure strategies and implement robust Design-for-Test (DFT) methodologies\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Own accountability for design quality, schedule, and successful production delivery\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional Collaboration\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Partner with verification teams to develop comprehensive test plans, achieve coverage closure, and debug complex issues\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with physical design, DFT, and post-silicon teams to ensure seamless integration and bring-up\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work with firmware and software teams to optimize hardware-software interfaces\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Mentorship \u0026amp;amp; Process Excellence\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Mentor and develop junior and senior engineers, elevating team technical capabilities\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive continuous improvement of silicon development processes, CAD automation, and design infrastructure\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Contribute to organizational knowledge sharing and technical reviews\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering or equivalent\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;12+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Demonstrated expertise in architecture definition, micro-architecture development, RTL coding, synthesis, and timing closure\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep knowledge of at least one high-speed protocol: PCIe, CXL, Ethernet, DDR, or similar\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Production experience with advanced CMOS nodes (≤7nm)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency with Cadence and/or Synopsys digital design flows\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Track record of delivering multiple high-performance designs to production\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Master\u0026#39;s degree in Electrical Engineering or related field\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with multiple high-speed protocols (PCIe Gen 5/6, CXL, UALink, Ethernet, DDR4/DDR5)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on collaboration with embedded firmware teams and familiarity with RISC-V or Arm subsystems\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven contributions to design methodology, CAD automation, or infrastructure improvements\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience leading technical teams or driving cross-functional initiatives in data center environments\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Salary range is $205,000 to $255,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4687560005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4431679005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Program Management","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4687560005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2473","title":"Senior Principal Engineering Program Manager","company_name":"Astera Labs","first_published":"2026-04-22T19:36:13-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is looking for a \u0026lt;strong\u0026gt;Senior Principal Engineering Program Manager\u0026lt;/strong\u0026gt; to lead end-to-end execution of advanced-node ASIC products from concept through production. This is a high-visibility role with direct accountability for delivering revenue-critical silicon on time, on spec, and at scale.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Program Ownership \u0026amp;amp; Execution\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Own full ASIC lifecycle execution: architecture, RTL, verification, physical design, tapeout, validation, customer sampling, qualification, and RTM\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Serve as the single point of ownership for assigned ASIC programs\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Drive program planning, schedules, budgets, resources, and risk management\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional Leadership \u0026amp;amp; Issue Resolution\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Lead cross-functional teams across design, validation, product, test, firmware, software, and operations\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Resolve complex pre-silicon and post-silicon issues through strong technical judgment\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Stakeholder Management \u0026amp;amp; Alignment\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Manage scope, schedule, and cost trade-offs and communicate clearly with executives and stakeholders\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Champion program execution while aligning engineering delivery with business and customer goals\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;BS or MS in Electrical, Electronics, or Computer Engineering\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;10+ years of ASIC product development experience in a semiconductor environment\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Strong understanding of ASIC development flows, with hands-on experience in RTL, DSP, or Physical Design\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience delivering ASICs in advanced nodes (\u0026amp;lt;10nm)\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Proven ability to lead in a matrixed, high-pressure environment\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Strong program management skills; familiarity with MS Project, Jira, Atlassian tools, Scrum/WBS\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;5 or more years of experience as an ASIC Program Manager\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience with PCIe, memory, or high-speed data communication ASICs\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Salary range is $205,000 to $250,000 depending on experience, level, and business need. This role is eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4043426005,"name":"Program Management","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4692577005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4434114005,"location":{"name":"United States, Remote"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose (HQ)","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"CTO Organization","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4692577005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2508","title":"Senior Principal Hardware System Architect","company_name":"Astera Labs","first_published":"2026-05-19T19:38:49-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;The AI infrastructure landscape is evolving at breakneck speed, and Astera Labs is at the center of it — delivering the intelligent connectivity solutions that enable the most demanding AI and cloud workloads on the planet. As server platforms grow increasingly complex with multi-socket architectures, accelerator-dense configurations, and high-speed interconnect fabrics, the need for world-class hardware architects who can define and deliver these systems end-to-end has never been more critical.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;The AI Platform Solutions Group is seeking a \u0026lt;strong\u0026gt;Senior Principal Hardware / System Architect\u0026lt;/strong\u0026gt; to lead the architecture, design, and development of next-generation x86 and accelerator-based server platforms. You will own system-level architecture decisions spanning compute, memory, storage, and interconnect subsystems — driving hardware platform development from concept through bring-up and validation. This role sits at the intersection of silicon, board design, FPGA/ASIC development, and platform integration, with direct impact on how AI infrastructure scales at the rack and cluster level.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This is a high-impact technical leadership role where you will partner across hardware, firmware, and platform engineering teams while collaborating with customers, silicon vendors, and hyperscalers to deliver custom, high-performance compute solutions. If you thrive on solving the hardest hardware architecture challenges and want to shape the platforms that power the next wave of AI, this is the opportunity.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;System Architecture \u0026amp;amp; Platform Design\u0026lt;/strong\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Lead end-to-end system architecture and design for server platforms including x86 multi-socket and accelerator-based systems\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Define and maintain multi-platform design standards and architectures that scale across product lines\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive hardware platform development including board design, system bring-up, and validation\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Oversee system-level integration across compute, storage, and interconnect subsystems — including PCIe Gen5/6 and high-speed fabric connectivity\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;FPGA \u0026amp;amp; Hardware Development Leadership\u0026lt;/strong\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Lead FPGA architecture and development including simulation, synthesis, validation, and common framework definition\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive signal integrity analysis, functional validation, and defect resolution across complex hardware systems\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Own hardware debug and bring-up in lab environments, ensuring seamless integration with firmware and software stacks\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional \u0026amp;amp; Customer Engagement\u0026lt;/strong\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Provide technical leadership and mentorship to distributed engineering teams across hardware, firmware, and platform disciplines\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Coordinate cross-functional activities to ensure alignment between hardware design, firmware integration, and system validation\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with customers and stakeholders on custom system solutions, technical briefings, and field issue resolution\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Partner with silicon vendors, OEMs, and hyperscalers to drive platform innovation aligned with Astera Labs\u0026#39; connectivity ecosystem\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, Computer Engineering, or a related field\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;12+ years of experience in hardware development or system architecture\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep expertise in x86 server architecture, including multi-processor systems\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with FPGA and/or ASIC design including simulation, synthesis, and validation\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong knowledge of high-speed interconnects (PCIe, UPI/QPI, Ethernet) and signal integrity principles\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven experience with system bring-up, debug, and validation in lab environments\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience leading complex hardware programs and cross-functional engineering teams\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong knowledge of memory subsystems, cache coherency, and PCB design\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Master\u0026#39;s degree in Electrical Engineering, Computer Engineering, or Computer Science\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with accelerator-based systems (GPU, AI/ML workloads) or AI training cluster hardware\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with heterogeneous computing architectures or composable infrastructure\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with EDA tools such as Cadence, Allegro, Quartus, or Xilinx environments\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Programming experience in C, Python, or scripting languages for hardware automation and validation\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Background in enterprise server, data center hardware, or custom system development\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience working with global development teams and customer-facing engineering engagements\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of fault-tolerant design or secure communication systems\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4141010005,"name":"Platform Architecture","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4055745005,"name":"Remote - United States","location":"Remote-United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4692960005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4434299005,"location":{"name":"United States, Remote"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Remote","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"CTO Organization","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4692960005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2511","title":"Senior Principal Hardware Systems Engineer ","company_name":"Astera Labs","first_published":"2026-05-19T19:39:02-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;The explosive growth of AI workloads is fundamentally reshaping how server platforms are designed — demanding unprecedented bandwidth, accelerator density, and intelligent connectivity at every layer of the stack. Astera Labs is powering this transformation with purpose-built connectivity solutions that enable the world\u0026#39;s most advanced AI and cloud infrastructure, and we need exceptional hardware systems engineers to help architect what comes next.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;The AI Platform Solutions Group is seeking a \u0026lt;strong\u0026gt;Senior Principal Hardware Systems Engineer\u0026lt;/strong\u0026gt; to lead the architecture and delivery of high-performance compute platforms with deep focus on PCIe subsystem design, GPU/accelerator integration, high-speed Ethernet networking, and system-level platform development. You will own the end-to-end system design from architecture definition through bring-up and validation, working at the critical intersection of compute, networking, storage, and Astera Labs\u0026#39; connectivity portfolio — including our PCIe retimers, switches, and fabric controllers.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This role combines hands-on engineering depth with system-level architectural thinking. You will drive complex platform development across hardware, firmware, and system management domains while collaborating with silicon vendors, hyperscalers, and cross-functional engineering teams. If you want to architect the AI platforms that are defining the future of data center compute, this is your opportunity.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;System Architecture \u0026amp;amp; PCIe Platform Design\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Lead system architecture and design for high-performance compute platforms optimized for AI and accelerator-driven workloads\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Design and integrate PCIe-based subsystems including GPU, accelerator, and high-speed I/O components leveraging PCIe Gen5/6 technologies\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Define and implement GPU-enabled server platforms for AI training, inference, and HPC workloads\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Architect and optimize high-speed Ethernet networking interfaces (25G/100G/400G+) within platform designs\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Hardware Development \u0026amp;amp; Validation\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Drive system-level integration across compute, networking, and storage subsystems\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop and validate FPGA-based solutions for system control, monitoring, and acceleration\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead system bring-up, debug, and validation in lab environments\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Troubleshoot complex hardware and performance issues across high-speed signaling, power, thermal, and interconnect domains\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Platform Management \u0026amp;amp; Cross-Functional Leadership\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Define and implement platform management solutions including BMC integration, telemetry, health monitoring, and system-level diagnostics\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with cross-functional teams spanning hardware, firmware, BIOS, and OS to ensure seamless platform integration\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Partner with silicon vendors, OEMs, and hyperscalers on custom platform development aligned with Astera Labs\u0026#39; connectivity ecosystem\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive performance optimization across PCIe topology, accelerator interconnects, and memory subsystems\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, Computer Engineering, or a related field\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;12+ years of experience in hardware engineering, system design, or platform architecture\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong expertise in PCIe architecture and subsystem design\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience with GPU integration and accelerator-based system development\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with high-speed Ethernet networking architecture (10G/25G/100G or higher)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience with FPGA design including architecture, simulation, and validation\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven experience with system bring-up, hardware debugging, and platform validation\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Solid understanding of high-speed signaling, interconnects, power, and thermal optimization\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with system management frameworks (BMC, telemetry, monitoring)\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Master\u0026#39;s degree in Electrical Engineering, Computer Engineering, or a related field\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience in AI/ML infrastructure, GPU clusters, or hyperscale data center server platforms\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of PCIe Gen5/Gen6, RDMA, RoCE, or similar high-performance networking technologies\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with custom platform development or customer-specific hardware designs\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with Astera Labs\u0026#39; connectivity solutions (retimers, switches, fabric controllers) or similar high-speed interconnect products\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience working with global hardware development teams\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Exposure to platform lifecycle management and fleet-level system diagnostics\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4141010005,"name":"Platform Architecture","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4055745005,"name":"Remote - United States","location":"Remote-United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4699876005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4437871005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose (HQ)","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Business Operations","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4699876005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2593","title":" Senior Principal Product Manager - Cosmos","company_name":"Astera Labs","first_published":"2026-05-28T13:31:58-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Astera Labs is seeking a Senior Principal Product Manager to lead the strategic direction and execution of a unified management and configuration suite that sits at the critical interface between host software, firmware, and silicon across our entire portfolio of connectivity products. This is not a traditional software PM role — it requires deep technical fluency in how software communicates with and runs on chips, how firmware orchestrates silicon behavior, and how all of it comes together inside modern AI server platforms.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;As the owner of the product roadmap, you will drive standardization of the full-stack software and firmware experience across all Astera products, ensuring that every touchpoint — from chip-level firmware execution to the host drivers and management tools running on the server — delivers a cohesive, powerful, and scalable experience for hyperscaler and enterprise customers.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;This role sits at the heart of Astera\u0026#39;s hyper-growth trajectory. As AI clusters scale from thousands to hundreds of thousands of accelerators, the need for intelligent, unified connectivity management has never been greater.\u0026amp;nbsp;You\u0026#39;ll\u0026amp;nbsp;define how the industry\u0026#39;s most advanced PCIe, CXL, and Ethernet connectivity silicon gets configured, monitored, and orchestrated — from embedded software running directly on the chip all the way up to the data center management plane.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Product Strategy \u0026amp;amp; Roadmap\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Define and own the end-to-end product roadmap for the platform, spanning embedded software running on silicon, firmware interfaces, host drivers, and server-level management tools\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Drive standardization of firmware APIs, host software interfaces, and management paradigms across all Astera product lines (Aries, Leo, Taurus, and beyond)\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; 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data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Conduct competitive analysis and\u0026amp;nbsp;identify\u0026amp;nbsp;opportunities to differentiate Astera\u0026#39;s full-stack manageability story\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; 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data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Engage directly with\u0026amp;nbsp;hyperscaler\u0026amp;nbsp;and enterprise platform teams — including firmware engineers, system architects, and BMC/manageability owners — to gather requirements and\u0026amp;nbsp;validate\u0026amp;nbsp;priorities\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; 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data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Represent Astera Labs at industry events, standards bodies, and customer technical reviews\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; 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data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Collaborate with firmware and embedded software teams to define how software runs on Astera silicon and how it\u0026amp;nbsp;interfaces with\u0026amp;nbsp;host systems\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Work with host software and driver teams to ensure seamless communication between server OS environments and Astera chips\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Partner with hardware architecture teams to influence chip features that enable superior programmability and software-driven manageability\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Coordinate with marketing on positioning, messaging, and go-to-market strategies for releases\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Operational Excellence\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Define and track product adoption metrics, customer integration success indicators, and firmware/software quality KPIs\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Manage release planning and feature prioritization across embedded software, firmware, driver, and tool workstreams simultaneously\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;o\u0026quot; data-font=\u0026quot;Courier New\u0026quot; data-listid=\u0026quot;1\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:1440,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Courier New\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[9675],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;o\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;2\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Build scalable product processes that support Astera\u0026#39;s rapid growth and expanding product portfolio\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Basic Qualifications\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, Computer Science, or a related technical field\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;2\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;12+ years of experience in product management, technical marketing, firmware engineering, or systems engineering in the semiconductor or data center infrastructure industry\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;3\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Proven experience managing or defining software products that run on and directly communicate with silicon (embedded software, firmware, chip-level tools)\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;4\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Strong understanding of the full-stack interaction model: host software (drivers, OS-level tools) ↔ firmware ↔ embedded software running on chip\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;5\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Deep familiarity with data center server architectures, platform firmware (BIOS/UEFI, BMC), and infrastructure management frameworks\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;2\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;6\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience engaging directly with\u0026amp;nbsp;hyperscaler\u0026amp;nbsp;or enterprise platform/firmware teams on technical requirements\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Preferred Qualifications\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; 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data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;7\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;MS in Electrical Engineering or Computer Science\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4000198005,"name":"Product Management","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4690490005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4433028005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Firmware Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4690490005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2492","title":"Senior Principal System Validation Engineer","company_name":"Astera Labs","first_published":"2026-04-29T14:31:54-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Job Description\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Develop and perform system validation tests using leading-edge Data Center equipment and scalable automation platforms. The validation team holds customers’ system requirements in the highest regard and is solely responsible for certifying a product’s conformance to this high bar.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Understand the performance and functionality requirements our ICs must deliver to enable customers developing Data Center systems using Astera Labs’ game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Formulate a comprehensive validation plan, automate the testing of ICs and board products in a data-centric manner, design experiments to root-cause unexpected behavior, report results and specification compliance in an automated fashion.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work with key customers directly to understand their care-abouts and highlight the unique capabilities and performance of Astera Labs’ solutions.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic qualifications\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong academic and technical background in Electrical or Computer Engineering. At a minimum, a Bachelor’s is required, and a Master’s is preferred.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;≥12 years\u0026#39; experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Basic understanding of x86/ARM architecture, UEFI/Linux boot sequence.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer/internal meetings in advance, and to work with minimal guidance and supervision.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Entrepreneurial, open-mind behavior and can-do attitude. Think and act with the customer in mind!\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required experience\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Hands-on, thorough knowledge of high-speed protocols like CXL, PCIe, NVMe, or Ethernet.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with Silicon/System bring-up, validation, and debug experience, including in customer systems.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;A strong background in developing bench automation techniques, especially using Python,\u0026amp;nbsp;with emphasis on\u0026amp;nbsp;execution efficiency, repeatability, data analysis and reporting.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with lab equipment including protocol analyzers, in-circuit debuggers, and CPU-based tool suites.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred experience\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Working knowledge of C or C++ for embedded FW and device drivers.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Working knowledge of SerDes architecture including Tx/Rx equalization, adaptation, CDR, block level requirements and SerDes link jitter budget. Experience with PAM4 SerDes is a huge bonus!\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with PCIe compliance standards and ability to follow and be involved in compliance consortiums to adapt the tests to be run from X86/ARM based platforms.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of schematic capture and PCB layout tools from Cadence Allegro, Altium, etc.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of simulation tools such as Keysight ADS, Mathworks QCD, etc. for IBIS-AMI analysis.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;The base salary range is $205,000.00 USD – $255,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025528005,"name":"Software Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4696478005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"internal_job_id":4436346005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose (HQ)","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"CTO Organization","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4696478005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2559","title":"Senior Principal Technologist – Memory","company_name":"Astera Labs","first_published":"2026-05-18T14:23:06-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Are you\u0026amp;nbsp;passionate about pushing the boundaries of\u0026amp;nbsp;system,\u0026amp;nbsp;memory,\u0026amp;nbsp;software,\u0026amp;nbsp;and\u0026amp;nbsp;chip\u0026amp;nbsp;architecture? Do you\u0026amp;nbsp;thrive when\u0026amp;nbsp;pitching\u0026amp;nbsp;cutting-edge technology solutions to\u0026amp;nbsp;customers\u0026amp;nbsp;and\u0026amp;nbsp;industry\u0026amp;nbsp;partners? We are seeking\u0026amp;nbsp;a creative customer facing\u0026amp;nbsp;Technologist\u0026amp;nbsp;to help facilitate\u0026amp;nbsp;Astera’s development\u0026amp;nbsp;of\u0026amp;nbsp;data center\u0026amp;nbsp;memory\u0026amp;nbsp;solutions.\u0026amp;nbsp;In this role, you will play a pivotal role in driving the\u0026amp;nbsp;architecture and definition\u0026amp;nbsp;of future products by leveraging your expertise in\u0026amp;nbsp;system architecture,\u0026amp;nbsp;SOC\u0026amp;nbsp;memory sub-system\u0026amp;nbsp;architecture, PCIe/CXL\u0026amp;nbsp;technologies,\u0026amp;nbsp;DRAM/memory architecture,\u0026amp;nbsp;and\u0026amp;nbsp;hardware-software\u0026amp;nbsp;co-design. You will have the opportunity to directly engage with customers,\u0026amp;nbsp;influence product features and roadmap,\u0026amp;nbsp;and help drive innovation to better solve our\u0026amp;nbsp;customers’\u0026amp;nbsp;bottlenecks in hyperscale data centers.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:2,\u0026amp;quot;335559740\u0026amp;quot;:300}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;This role is fully in person, in\u0026amp;nbsp;San Jose.\u0026amp;nbsp;Some travel may be required.\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:2,\u0026amp;quot;335559740\u0026amp;quot;:300}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Basic qualifications\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt; \u0026lt;/span\u0026gt; \u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;BS in Electrical or computer engineering, MS or PhD preferred. \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:2,\u0026amp;quot;335559740\u0026amp;quot;:300}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;≥10 year’s experience developing memory-related solutions and integrating them into systems/racks for data centers\u0026amp;nbsp;\u0026lt;/span\u0026gt; \u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep experience with PCIe 5/6, and CXL including protocol level depth\u0026amp;nbsp; \u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Expertise in OS software integration including memory allocation/management \u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Recent experience with silicon architecture and development especially SOCs with memory controllers (DDR*, LPDDR*, HBM, etc) \u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep expertise and understanding of memory components (DRAM, etc) \u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of datacenter system architecture and design challenges \u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of “full stack” solutions from silicon to application integration \u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience working in a customer-facing role with the ability to articulate technical concepts, influence decision-making, and build business cases \u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ability to dig deeply into technical challenges and use cases\u0026amp;nbsp; \u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent communication and interpersonal skills with the ability to collaborate effectively with internal teams and external partners. \u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Demonstrated leadership capabilities with a track record of driving cross-functional technical initiatives and delivering results in a fast-paced environment. \u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Willingness to travel occasionally for customer meetings and industry events.\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:2,\u0026amp;quot;335559740\u0026amp;quot;:300}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Preferred experience\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt; \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:2,\u0026amp;quot;335559740\u0026amp;quot;:300}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Expertise in\u0026amp;nbsp;JEDEC-defined memory interface specifications\u0026lt;/span\u0026gt; \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;Expertise in memory ECC and error handling \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;Experience in product integration with BIOS, kernel, OS, tooling, and BMCs \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;Experience with board and system design \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;Existing engagement and robust network within industry organizations such as PCI-SIG, OCP, JEDEC, CXL, etc.\u0026amp;nbsp; \u0026lt;/li\u0026gt;\n\u0026lt;li data-leveltext=\u0026quot;\u0026quot; data-font=\u0026quot;Symbol\u0026quot; data-listid=\u0026quot;3\u0026quot; data-list-defn-props=\u0026quot;{\u0026amp;quot;335552541\u0026amp;quot;:1,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559991\u0026amp;quot;:360,\u0026amp;quot;469769226\u0026amp;quot;:\u0026amp;quot;Symbol\u0026amp;quot;,\u0026amp;quot;469769242\u0026amp;quot;:[8226],\u0026amp;quot;469777803\u0026amp;quot;:\u0026amp;quot;left\u0026amp;quot;,\u0026amp;quot;469777804\u0026amp;quot;:\u0026amp;quot;\u0026amp;quot;,\u0026amp;quot;469777815\u0026amp;quot;:\u0026amp;quot;multilevel\u0026amp;quot;}\u0026quot; data-aria-posinset=\u0026quot;1\u0026quot; data-aria-level=\u0026quot;1\u0026quot;\u0026gt;Hands-on silicon development experience \u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:2,\u0026amp;quot;335559740\u0026amp;quot;:300}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:true,\u0026amp;quot;134233118\u0026amp;quot;:true,\u0026amp;quot;201341983\u0026amp;quot;:2,\u0026amp;quot;335559740\u0026amp;quot;:300}\u0026quot;\u0026gt;Salary range is $205,000 to $255,000 depending on experience, level, and business need. This role is eligible for discretionary bonus, incentives and benefits.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4133890005,"name":"CTO","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4646293005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4412453005,"location":{"name":"San Jose, CA"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Firmware Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4646293005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2187","title":"Senior Principal Validation Engineer ","company_name":"Astera Labs","first_published":"2026-01-22T16:40:18-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p data-start=\u0026quot;145\u0026quot; data-end=\u0026quot;476\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;Overview:\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As a \u0026lt;strong\u0026gt;Senior\u0026lt;/strong\u0026gt; \u0026lt;strong\u0026gt;Principal Validation Engineer\u0026lt;/strong\u0026gt;, you will join a cutting-edge mixed-signal design team and lead the end-to-end post‑silicon validation and characterization effort. You will own the development and execution of comprehensive validation plans, design and implement test methodologies, and drive hands‑on lab work to verify silicon against specification and performance targets.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;You will collaborate closely with design, firmware, and system teams to translate architectural goals into measurable test strategies, build automated test frameworks, and analyze complex analog and digital interactions. Your work will include defining test requirements, creating characterization flows, debugging silicon anomalies, and delivering clear, data‑driven recommendations that influence product direction.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This role requires deep technical expertise in mixed‑signal systems, strong problem‑solving skills, and the ability to mentor engineers across disciplines. You will be expected to champion best practices for validation, optimize test coverage and throughput, and ensure that products meet reliability, yield, and performance objectives before production.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Design, develop, and execute validation plans.\u0026lt;/strong\u0026gt; Own end‑to‑end post‑silicon characterization and validation strategies, translating product requirements into measurable test objectives, pass/fail criteria, and schedules.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Drive design reviews and specification alignment.\u0026lt;/strong\u0026gt; Participate in architecture and design‑spec reviews to ensure testability, trace requirements to verification plans, and influence design tradeoffs to meet performance and reliability targets.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Lead hands‑on test execution and bring‑up.\u0026lt;/strong\u0026gt; Perform silicon bring‑up, functional and parametric testing, interop checks, and performance benchmarking; rapidly iterate on test flows to accelerate time‑to‑data.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Build and maintain automation frameworks.\u0026lt;/strong\u0026gt; Develop scalable test automation, data capture, and analysis pipelines to increase throughput, reproducibility, and coverage across mixed‑signal test benches.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Debug and optimize system performance.\u0026lt;/strong\u0026gt; Diagnose complex failures and performance bottlenecks across analog, digital, firmware, and protocol layers; propose and validate corrective actions to improve stability, yield, and power/performance tradeoffs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Root‑cause cross‑domain failures.\u0026lt;/strong\u0026gt; Trace issues to circuit, package, firmware, or protocol interactions using lab measurements, waveform analysis, and system‑level tests; coordinate with design, package, and firmware teams to implement fixes.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Collaborate with cross‑functional teams.\u0026lt;/strong\u0026gt; Work closely with mixed‑signal design, firmware, system engineering, and manufacturing to deliver detailed results, root‑cause analyses, optimization recommendations, and formal validation/compliance reports.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Document findings and improve methodologies.\u0026lt;/strong\u0026gt; Produce clear debug reports, formal characterization summaries, and recommendations for design/process/test improvements; contribute to failure analysis (FA) best practices and knowledge base.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Develop test software and platform integrations.\u0026lt;/strong\u0026gt; Write robust Python test scripts and control interfaces to configure, monitor, and collect status from multiple DSP and hardware platforms, improving firmware stability and automating regression suites.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Measure and communicate impact.\u0026lt;/strong\u0026gt; Define key validation metrics, track coverage and defect trends, and present data‑driven conclusions to stakeholders to influence product direction and release decisions.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Education\u0026lt;/strong\u0026gt; — Bachelor of Science in Electrical Engineering required; Master’s degree preferred to demonstrate advanced technical depth and specialization.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Experience\u0026lt;/strong\u0026gt; — At least ten years of hands‑on experience in mixed‑signal, high‑speed lab environments, executing characterization and validation with industry instruments such as protocol analyzers, BERTs, real‑time oscilloscopes, sampling scopes, TDRs, and VNAs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Software Skills\u0026lt;/strong\u0026gt; — Strong programming ability in Python and C/C++ for test automation, data analysis, and firmware interaction.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Retimer Expertise\u0026lt;/strong\u0026gt; — Practical experience bringing up and debugging retimers, including equalization tuning, pass‑through operation, clocking strategies, and reset and link sequencing.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;High‑Speed Signaling Knowledge\u0026lt;/strong\u0026gt; — Deep understanding of NRZ and PAM4 architectures and the ability to investigate jitter sources, CDR and PLL behavior, equalization techniques such as DFE, CTLE, and FFE, as well as crosstalk and power integrity issues.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Post‑Silicon Validation\u0026lt;/strong\u0026gt; — Proven track record in post‑silicon validation and bring‑up of high‑speed PHYs or retimers, with experience developing characterization flows and validating silicon against specifications.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Circuit Block Familiarity\u0026lt;/strong\u0026gt; — Solid working knowledge of key high‑speed building blocks including PLLs, CTLE, DFE, transmitter equalization, and PAM4 signaling fundamentals.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Analytical Problem Solving\u0026lt;/strong\u0026gt; — Exceptional troubleshooting skills with the ability to isolate and narrow complex, multi‑layer failures across analog, digital, firmware, and package domains.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Communication\u0026lt;/strong\u0026gt; — Excellent written and verbal communication skills for clear documentation of findings, presentation of root cause analyses, and collaboration with cross‑functional teams.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Experience:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Mixed‑signal system testing and validation\u0026lt;/strong\u0026gt; — Demonstrated experience in end‑to‑end mixed‑signal system testing, characterization, validation, and compliance activities, including developing test plans, executing characterization flows, and producing formal compliance reports.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Signal integrity instrumentation and techniques\u0026lt;/strong\u0026gt; — Hands‑on proficiency with signal integrity test equipment and methodologies, including BERTs, VNAs, oscilloscopes, sampling scopes, TDRs, and advanced probing techniques for channel and package analysis.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Ethernet standards familiarity\u0026lt;/strong\u0026gt; — Working knowledge of IEEE 802.3 family standards and practical experience validating Ethernet PHYs, link training, autonegotiation, and compliance testing across relevant speeds and media types.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Serial protocol expertise\u0026lt;/strong\u0026gt; — Practical understanding of common serial interfaces such as I2C, I3C, SPI, UART, and other control/status buses used for device bring‑up, firmware interaction, and system integration.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Cross‑discipline collaboration\u0026lt;/strong\u0026gt; — Proven ability to translate SI/PI simulation results into testable lab plans, collaborate with design and firmware teams to close the loop on issues, and document findings that drive design or process improvements.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Based in San Jose, this position requires an in-person presence, offering a unique opportunity to impact our global operations directly.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;The base salary range is USD 205,00 - USD 255,000. \u0026lt;/span\u0026gt;Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4135671005,"name":"SerDes","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4588342005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4384501005,"location":{"name":"San Jose, CA"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Design Verification","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4588342005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"1837","title":"Senior SoC Verification/Validation Engineer ","company_name":"Astera Labs","first_published":"2025-08-20T13:47:33-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Job Description\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;We are looking for\u0026lt;strong\u0026gt; Senior SoC Verification/Validation Engineer\u0026amp;nbsp;\u0026lt;/strong\u0026gt;who are passionate about bringing next-generation SoCs to life on industry-leading emulation platforms. You will play a critical role in validating complex SoCs for AI connectivity and cloud infrastructure, ensuring functionality and performance well before silicon tape-out.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;\u0026lt;span id=\u0026quot;content-1755655491226\u0026quot; class=\u0026quot;fui-Primitive ___1omhnq5 fqtknz5 fyvcxda\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Play a key role in developing complex SOCs for AI connectivity and cloud infrastructures\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Bring up and validate high-speed serial interfaces such as PCIe, Ethernet and UALink, and overall SoC functionality\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate closely with Architecture, Design, Verification,\u0026amp;nbsp;and SW/FW teams to define and execute functional/performance validation plans\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop C/C++ FW and tests to validate and execute all test plan items\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Build tools and methodologies to validate and debug all HW and SW/FW issues on the emulation platform\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Qualification\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;BS/MS in Electrical Engineering, Computer Engineering or related field.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;5+ years of hands-on experience in pre-silicon verification/validation.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong hands-on experience in running and debugging SOC simulation.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Protocol knowledge in high-speed protocols such as PCIe, UALink and/or Ethernet is essential\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency in programming and scripting languages (System Verilog, C/C++, Python)\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong debugging\u0026amp;nbsp;and analytical skills\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent communication skills and ability to\u0026amp;nbsp;work independently with minimal supervision.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Currently based locally or open to relocation.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Experience:\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bring up and validation experience using the industry standard emulation platforms (Palladium or Zebu)\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience in running and debugging SOC simulation and emulation platforms.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;The base salary range is $165,000 USD - $195,000 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4674527005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4425429005,"location":{"name":"Israel"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Physical Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4674527005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2379","title":"Senior/ Staff Chip Top Physical Design  Engineer","company_name":"Astera Labs","first_published":"2026-03-18T12:56:17-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is establishing a strategic R\u0026amp;amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical \u0026#39;data bottlenecks\u0026#39; enabling the future of AI at scale. As we expand our presence in Israel, we\u0026#39;re seeking a highly skilled \u0026lt;strong\u0026gt;Chip Top Physical Design Engineer\u0026lt;/strong\u0026gt; focusing on implementation to join our local engineering powerhouse from the ground up.\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;br\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;If you thrive on solving complex, unnamed challenges in deep-submicron processes, your place is with us.\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335559685\u0026amp;quot;:720,\u0026amp;quot;335559738\u0026amp;quot;:240,\u0026amp;quot;335559739\u0026amp;quot;:240}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As a Physical Design Engineer, you will be a key hands-on member of our PD Team in the Israel R\u0026amp;amp;D center. You will execute the physical design of the SoC Top level for chips that drive the world’s largest AI clusters. You will be deeply involved in all PD disciplines of the chip, driving the tape-out (T.O.) GDS to meet strict signoff criteria (Timing, LVS, EMIR, DRC, PV, etc.), ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,0,0\u0026quot;\u0026gt;Execute SoC Top-level physical design and actively drive full-chip convergence\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,1,0\u0026quot;\u0026gt;Perform Top-Level physical implementation, including floor-planning, Place \u0026amp;amp; Route (P\u0026amp;amp;R), Clock Tree Synthesis (CTS), Power/Clock distribution, Power Integrity, and Timing/Physical signoff\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,2,0\u0026quot;\u0026gt;Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power, Performance, and Area (PPA). This involves participating in feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,3,0\u0026quot;\u0026gt;Resolve complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,4,0\u0026quot;\u0026gt;Collaborate closely with the Package team on Bump-map-to-Ballout design, taking all signal integrity aspects into consideration\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,0,0\u0026quot;\u0026gt;B.Sc. or M.Sc. in Electrical Engineering\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,1,0\u0026quot;\u0026gt;5+ years of hands-on experience in Chip Top Physical Design/Backend at leading semiconductor companies, working on advanced process technologies (5nm, 3nm, and below)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,2,0\u0026quot;\u0026gt;Proven experience executing complex block or chip-level projects with a proactive, \u0026quot;can-do\u0026quot; approach and excellent communication skills\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,3,0\u0026quot;\u0026gt;Deep hands-on expertise in RTL2GDS flows, including P\u0026amp;amp;R, STA, Physical Verification (DRC/LVS), Formal Verification, low-power implementation (UPF/CPF), and EMIR\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,4,0\u0026quot;\u0026gt;Mastery of industry-standard EDA tools (Synopsys Fusion Compiler/ICC2 or Cadence Innovus)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,5,0\u0026quot;\u0026gt;Practical experience handling both complex macro/subsystem-level designs and Full-Chip integration\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p data-path-to-node=\u0026quot;10\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;11,0,0\u0026quot;\u0026gt;Deep understanding of Power \u0026amp;amp; Noise analysis (EM/IR)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;11,1,0\u0026quot;\u0026gt;Experience with DFT (Design for Test) integration into the physical design flow\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;11,2,0\u0026quot;\u0026gt;Background in high-speed interfaces or data center protocols\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4008937005,"name":"Israel","location":"Israel","child_ids":[4061058005,4052111005,4056876005],"parent_id":null}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4567359005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4374135005,"location":{"name":"San Jose, CA"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Hardware Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4567359005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"1781","title":"Senior/Staff Electronics Engineer - Board Validation","company_name":"Astera Labs","first_published":"2025-05-20T18:23:27-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;As a \u0026lt;strong\u0026gt;Senior/Staff Electronics Engineer \u0026lt;/strong\u0026gt;you will join the Hardware Electrical Validation team at Astera Labs, linking between the Hardware Electrical Design teams and Post-Silicon Electrical Validation teams, among others.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Note: This role is not post-silicon electrical validation; it is electrical validation of PCBAs and related\u0026amp;nbsp;hardware products.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Support the Hardware Electrical Design teams with de-risking circuits and modules from project kick-off to gerber out.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop comprehensive hardware electrical validation plans using correct test methods and processes.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Bring up the PCBAs upon arrival in the lab, and execute the electrical validation plans to validate all circuits on the board.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Debug complex multi-point failures in hardware - power regulators, DPMs, clock synthesizers, digital control paths, I2C, SPI, etc.\u0026amp;nbsp; \u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Rework components on the PCBAs to unblock debugging activities.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Pre-empt and de-risk system validation architectures - collaborate with the System Validation teams.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support hardware activities in auxiliary teams - Post-Silicon Electrical Validation, Product Apps, System Validation, FAEs, etc.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support the new designs using knowledge of existing products to de-risk new features and requirements.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Self-informed of new industry test standards and equipment to introduce modern testing methodologies.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Specify test equipment, develop test fixtures, help improve hardware lab functions.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Skills\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Demonstrated strong skills in electronic circuit analysis, comprehensive testing and debug\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Bachelor degree in EE with 3+ years of experience in hardware test or design\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Expert understanding of design and test for power regulators, PDNs, Bode, clock generators\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ability to produce test description from a schematic design, and execute and document results\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Demonstrated knowledge of the full hardware product lifecycle from Project Kick-off to RTM\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lab equipment for hardware test - oscilloscopes, e-loads, VNA, TDR, environmental chambers, etc.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Automating lab equipment to optimize test processes, Python preferred\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Skills\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Measurements of high-speed interfaces - PCIe, DDR, 25/50G/100G SERDES, etc.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;EMI/EMC compliance\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Technical writing skills - ECOs, Bug Reports, Rework WIs, MCOs, etc.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;PLM, Arena or equivalent\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Understanding of the ASIC/silicon product development process\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;p\u0026gt;Base salary ranges are $135,000–$165,000 USD for Senior-level candidates and $160,000–$195,000 USD for Staff-level candidates. Compensation will be determined based on the candidate’s experience, scope of impact, and alignment with employees in similar positions.\u0026lt;/p\u0026gt;\n\u0026lt;/div\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025526005,"name":"Hardware Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4675017005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4425641005,"location":{"name":"Israel"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Physical Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4675017005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2390","title":"Senior/ Staff Front-End CAD Engineer","company_name":"Astera Labs","first_published":"2026-03-19T11:38:30-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;EOP SCXW38165641 BCX0\u0026quot; data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:160}\u0026quot;\u0026gt;Astera Labs is establishing a strategic R\u0026amp;amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical \u0026#39;data bottlenecks\u0026#39; enabling the future of AI at scale. As we expand our presence in Israel, \u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;we\u0026#39;re seeking a highly skilled\u0026lt;strong\u0026gt; Front-End CAD Engineer\u0026amp;nbsp;\u0026lt;/strong\u0026gt;to join our local engineering powerhouse from the ground up.\u0026lt;/p\u0026gt;\n\u0026lt;p data-path-to-node=\u0026quot;4\u0026quot;\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;As a Front-End CAD Engineer, you will be the backbone of our chip design ecosystem. You won’t just be using tools; you’ll be architecting the methodologies, automation scripts, and design flows that enable our hardware teams to push the limits of silicon performance. Your work directly impacts the productivity of the design team and the time-to-market for our next-generation processors.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;br\u0026gt;Key Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Develop, maintain, and optimize RTL generation tools, building automated IPs and SoC schemes\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Create robust applications using Python and Tcl to automate models build, regression and analysis tools and other assisting tools for all disciplines in front-end flows\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Evaluate and integrate Electronic Design Automation (EDA) tools from vendors like Cadence, Synopsys, and Mentor Graphics\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Define the methodologies of usage and integrate AI tools in this fast-growing field impacting all VLSI development flows\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;br\u0026gt;\u0026lt;/span\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;8,0,0\u0026quot;\u0026gt;Bachelor’s degree in Electrical Engineering or a related technical field\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;8,1,0\u0026quot;\u0026gt;5+ years of hands-on professional experience in relevant industries\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;8,1,0\u0026quot;\u0026gt;Proven experience in\u0026amp;nbsp;\u0026lt;strong\u0026gt;Python\u0026lt;/strong\u0026gt; and \u0026lt;strong\u0026gt;Tcl\u0026lt;/strong\u0026gt; within a Linux/Unix environment\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;8,1,0\u0026quot;\u0026gt;Knowledge and experience in Verilog and/or System Verilog\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;8,1,0\u0026quot;\u0026gt;Very good communication skills\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Preferred Experience\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of the VLSI design cycle, familiarity with clock domain crossing, simulation, debugging, synthesis and timing analysis\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience with industry-standard tools for lint, synthesis, simulation\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with version control systems (Git) and compute cluster management (LSF/SGE)\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4008937005,"name":"Israel","location":"Israel","child_ids":[4061058005,4052111005,4056876005],"parent_id":null}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4674501005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4425414005,"location":{"name":"Israel"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Physical Design/DFT","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4674501005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2375","title":"Senior/ Staff Package Design Engineer","company_name":"Astera Labs","first_published":"2026-03-18T12:56:50-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is establishing a strategic R\u0026amp;amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical \u0026#39;data bottlenecks\u0026#39; enabling the future of AI at scale. As we expand our presence in Israel, we\u0026#39;re seeking a visionary\u0026amp;nbsp;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Package Design Engineer\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;strong\u0026gt;\u0026amp;nbsp;\u0026lt;/strong\u0026gt;to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, Driving the physical implementation strategy for chips that power the world\u0026#39;s largest AI clusters.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:160}\u0026quot;\u0026gt;As a Package Design Engineer, you will be a core technical contributor in the development of advanced IC packaging solutions for high-performance connectivity silicon. You will execute the package flow, design, and qualification from concept through production, working closely with silicon, signal integrity, power integrity, mechanical, manufacturing, and external OSAT partners. You will be responsible for implementing package technologies that meet aggressive electrical, thermal, mechanical, and cost targets, enabling Astera Labs’ products to operate reliably in the world’s most demanding AI and cloud environments.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,0,0\u0026quot;\u0026gt;Execute end-to-end IC package design, from early feasibility and detailed design through to qualification and high-volume manufacturing\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,1,0\u0026quot;\u0026gt;Implement package architecture and utilize advanced technologies (organic substrates, advanced laminate, interposers, multi-die/chiplet packaging, CoWoS - 2.5D/3D integration)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,2,0\u0026quot;\u0026gt;Drive signal integrity (SI), power integrity (PI), and thermal considerations at the package level for high-speed, high-power devices\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,3,0\u0026quot;\u0026gt;Perform package layout, substrate routing, bump/ball maps, stack-ups, materials selection, and apply mechanical constraints\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,4,0\u0026quot;\u0026gt;Collaborate closely with silicon design, SerDes, system, SI/PI, and reliability teams to optimize overall product performance\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,5,0\u0026quot;\u0026gt;Interface directly with OSATs, substrate vendors, and manufacturing partners to ensure design-for-manufacturability (DFM), yield, and cost targets are met\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,6,0\u0026quot;\u0026gt;Conduct package-related risk assessments, failure analysis, and corrective actions during bring-up and production ramp\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,7,0\u0026quot;\u0026gt;Support NPI, qualification, and product sustainment activities, including vendor technical reviews\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,0,0\u0026quot;\u0026gt;5+ years of hands-on IC package design experience for high-performance semiconductor products, with full technical ownership from concept through tape-out\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,1,0\u0026quot;\u0026gt;Expert proficiency in IC package design tools (Cadence APD / SiP or equivalent) and hands-on experience designing complex packages (BGA, FCBGA, FCCSP)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,2,0\u0026quot;\u0026gt;Strong package integration expertise, including stack-ups, ball/bump maps, constraints, SMT integration, and package BOM ownership\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,3,0\u0026quot;\u0026gt;Deep understanding of signal, power, and thermal integrity at the package level, with the ability to execute design tradeoffs based on analysis\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,4,0\u0026quot;\u0026gt;Proven manufacturing and release experience, including running DRC/LVS/DFM, OSAT engagement, and delivering production-ready package designs\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;11,0,0\u0026quot;\u0026gt;Experience with AI, networking, PCIe, CXL, or other high-speed data center interfaces\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;11,1,0\u0026quot;\u0026gt;Familiarity with package reliability standards and qualification (JEDEC, IPC, thermal cycling, HTOL, etc.)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;11,2,0\u0026quot;\u0026gt;Experience supporting chiplet-based architectures and heterogeneous integration\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;11,3,0\u0026quot;\u0026gt;Demonstrated track record of complete technical package ownership on high-volume products\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4008937005,"name":"Israel","location":"Israel","child_ids":[4061058005,4052111005,4056876005],"parent_id":null}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4674511005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4425420005,"location":{"name":"Israel"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Physical Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4674511005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2376","title":"Senior/ Staff Physical Design CAD Engineer -  Automation \u0026 Signoff","company_name":"Astera Labs","first_published":"2026-03-18T12:57:23-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;EOP SCXW38165641 BCX0\u0026quot; data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:160}\u0026quot;\u0026gt;Astera Labs is establishing a strategic R\u0026amp;amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical \u0026#39;data bottlenecks\u0026#39; enabling the future of AI at scale. As we expand our presence in Israel, \u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;we\u0026#39;re seeking a highly skilled \u0026lt;strong\u0026gt;Physical Design CAD Engineer\u0026lt;/strong\u0026gt; specializing in CAD Automation and Signoff to join our local engineering powerhouse from the ground up.\u0026lt;/p\u0026gt;\n\u0026lt;p data-path-to-node=\u0026quot;4\u0026quot;\u0026gt;This is a unique opportunity to take on meaningful technical ownership in a new site, implementing the backend execution environment and methodologies for chips that power the world\u0026#39;s largest AI clusters. As a foundational member of the team, you will be responsible for the physical implementation environment. Your primary mission is to develop, optimize, and support automated flows from RTL to manufacturable GDSII tape-out, ensuring a methodical and efficient work environment for the entire PD team.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;br\u0026gt;Key Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;6,0,0\u0026quot;\u0026gt;Develop and maintain automated flows for Synthesis, Place \u0026amp;amp; Route (P\u0026amp;amp;R), and Floor-planning to ensure seamless design transitions\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;6,1,0\u0026quot;\u0026gt;Implement and manage robust environments for Static Timing Analysis (STA), Power Analysis, and Physical Verification (DRC/LVS/ERC)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;6,2,0\u0026quot;\u0026gt;Write and maintain custom plug-ins and scripts (Tcl/Python) to extend vendor tool capabilities, tailoring them to specific process node constraints\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;6,3,0\u0026quot;\u0026gt;Build automated \u0026quot;dashboards\u0026quot; and feedback loops to track and improve Power, Performance, and Area (PPA) metrics across design iterations\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;6,4,0\u0026quot;\u0026gt;Own the design database structure and version control to ensure team alignment and data integrity\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;6,5,0\u0026quot;\u0026gt;Collaborate directly with EDA vendors (Synopsys, Cadence, Siemens/Mentor) to troubleshoot flow issues and analyze tool results\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;6,6,0\u0026quot;\u0026gt;Provide technical support to the broader PD team, helping them optimize individual blocks for power, performance, and timing\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;br\u0026gt;\u0026lt;/span\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;8,0,0\u0026quot;\u0026gt;Bachelor’s degree in Electrical Engineering or a related technical field\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;8,1,0\u0026quot;\u0026gt;5+ years of hands-on professional experience with back-end industrial tool suites (e.g., Synopsys Fusion Compiler or Cadence Genus/Innovus)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;8,2,0\u0026quot;\u0026gt;Expert-level proficiency in \u0026lt;strong\u0026gt;Tcl \u0026lt;/strong\u0026gt;and\u0026lt;strong\u0026gt; Python\u0026lt;/strong\u0026gt; for high-level flow automation, data parsing, and tool customization\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;8,3,0\u0026quot;\u0026gt;Deep technical understanding of Physical Design concepts, including clock tree synthesis (CTS), routing congestion, timing closure, and signal integrity\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;8,4,0\u0026quot;\u0026gt;Proven experience executing sign-off flows for complex, high-performance designs\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;8,5,0\u0026quot;\u0026gt;Strong communication skills and a collaborative approach to solving complex engineering bottlenecks\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:160}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Preferred Experience\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;10,0,0\u0026quot;\u0026gt;Hands-on experience with 5nm, 3nm, or more advanced process nodes\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;10,1,0\u0026quot;\u0026gt;Practical knowledge of compute farm management (LSF/Slurm) and revision control (Git) for managing massive design databases\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;10,2,0\u0026quot;\u0026gt;Experience in developing proprietary automation wrappers for industry-standard EDA tools\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4008937005,"name":"Israel","location":"Israel","child_ids":[4061058005,4052111005,4056876005],"parent_id":null}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4654857005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4416638005,"location":{"name":"San Jose, CA"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Physical Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4654857005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2251","title":"Senior/Staff Physical Design Engineer ","company_name":"Astera Labs","first_published":"2026-01-28T17:51:08-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;As an Astera Labs \u0026lt;strong\u0026gt;Senior/Staff Physical Design Engineer\u0026lt;/strong\u0026gt; you will play a crucial role in overseeing the planning, coordination, and execution supporting the design of Astera Labs\u0026#39; portfolio of connectivity ASICs used in the world\u0026#39;s leading cloud service providers, server and network OEMs. To accomplish that, you will work closely with designers, verification engineering, and engineering operations. This role is fully on-site and in-person.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Basic Qualifications:\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE / Computer is required, and a Master’s degree is preferred.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;≥3 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Required Experience:\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Hands-on and thorough knowledge of synthesis, place and route, timing, extraction, EM-IR, formal verification (equivalence) and other backend tools and methodologies for technologies 7nm or less.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Block level ownership from architecture to GDSII, driving multiple complex designs to production.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with Cadence and/or Synopsys physical design tools/flows.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity and working knowledge of System Verilog/Verilog.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven expertise in developing/maintaining timing constraints, timing signoff methodology, timing closure at the block or full-chip level.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience in working with IP vendors for both RTL and hard-macro blocks.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Good scripting skills in tcl, python or Perl.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Preferred Experience:\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of design for test (DFT)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with ECO methodologies and tools.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of LVS/DRC closures.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;p\u0026gt;Your base salary will be determined based on your experience and the pay of employees in similar positions. The base salary range is $135,000 USD - $165,000 USD for Senior Level, and $160,000 USD - $195,000 USD for Staff Level.\u0026lt;/p\u0026gt;\n\u0026lt;/div\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4674516005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4425423005,"location":{"name":"Israel"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Physical Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4674516005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2377","title":"Senior/ Staff Physical Design Engineer - CAD Extraction ","company_name":"Astera Labs","first_published":"2026-03-18T12:57:45-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;EOP SCXW38165641 BCX0\u0026quot; data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:160}\u0026quot;\u0026gt;Astera Labs is establishing a strategic R\u0026amp;amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical \u0026#39;data bottlenecks\u0026#39; enabling the future of AI at scale. As we expand our presence in Israel, \u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;we\u0026#39;re seeking a highly skilled \u0026lt;strong\u0026gt;Physical Design CAD Engineer\u0026lt;/strong\u0026gt; specializing in CAD Extraction to join our local engineering powerhouse from the ground up.\u0026lt;/p\u0026gt;\n\u0026lt;p data-path-to-node=\u0026quot;4\u0026quot;\u0026gt;This is a unique opportunity to take on meaningful technical ownership in a new site, implementing the parasitic extraction (PEX) methodologies and flows for chips that power the world\u0026#39;s largest AI clusters. As a foundational member of the team, you will be responsible for the accuracy and efficiency of our extraction environment, ensuring that our high-speed designs are modeled with the highest precision from RTL to GDSII.\u0026lt;/p\u0026gt;\n\u0026lt;p data-path-to-node=\u0026quot;4\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;6,0,0\u0026quot;\u0026gt;Develop, qualify, and maintain automated RC extraction flows for high-performance AI SoCs\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;6,1,0\u0026quot;\u0026gt;Own the setup and validation of foundry technology files (e.g., StarRC/Quantus techfiles, TLU+, ITF) across various process corners\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;6,2,0\u0026quot;\u0026gt;Perform correlation studies between different extraction tools and 3D field solvers (e.g., Raphael, QuickCap) to ensure modeling accuracy\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;6,3,0\u0026quot;\u0026gt;Collaborate closely with the Signal Integrity (SI) and Power Integrity (PI) teams to provide accurate parasitic data for critical high-speed nets and power grids\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;6,4,0\u0026quot;\u0026gt;Implement automated scripts (Tcl/Python) to streamline extraction regressions, data parsing, and PEX-to-STA (Static Timing Analysis) handoffs\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;6,5,0\u0026quot;\u0026gt;Analyze the impact of layout effects (LDE) and parasitics on timing and power, providing feedback to the implementation team to optimize PPA\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;6,6,0\u0026quot;\u0026gt;Interface with EDA vendors and foundries to resolve extraction tool bugs and methodology gaps related to advanced nodes (5nm/3nm)\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;br\u0026gt;\u0026lt;/span\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;8,0,0\u0026quot;\u0026gt;Bachelor’s degree in Electrical Engineering or a related technical field\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;8,1,0\u0026quot;\u0026gt;5+ years of hands-on experience in Physical Design CAD or Physical Verification with a heavy focus on parasitic extraction\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;8,2,0\u0026quot;\u0026gt;Expert proficiency with industry-standard extraction tools such as Synopsys StarRC, Cadence Quantus (QRC), or Siemens Calibre xACT\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;8,3,0\u0026quot;\u0026gt;Strong scripting skills in Tcl and Python for flow automation and database manipulation\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;8,4,0\u0026quot;\u0026gt;Deep understanding of semiconductor physics, interconnect modeling, and the impact of parasitics on timing, EM (Electromigration), and IR drop\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;8,5,0\u0026quot;\u0026gt;Proven experience in validating tech files and running extraction for complex, multi-million gate designs\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:160}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Preferred Experience\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;10,0,0\u0026quot;\u0026gt;Hands-on experience with 5nm, 3nm, or more advanced process nodes, including FinFET-specific extraction challenges\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;10,1,0\u0026quot;\u0026gt;Familiarity with 3D field solvers and their use in benchmarking standard extraction engines\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;10,2,0\u0026quot;\u0026gt;Knowledge of Netlist formats (SPEF, DSPF) and their integration into STA and Spice simulation flows\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;10,3,0\u0026quot;\u0026gt;Experience with compute farm management (LSF/Slurm) and version control (Git)\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4008937005,"name":"Israel","location":"Israel","child_ids":[4061058005,4052111005,4056876005],"parent_id":null}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4674955005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4425621005,"location":{"name":"Tel Aviv-Yafo, Tel Aviv District, Israel"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Physical Design/DFT","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4674955005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2389","title":"Senior/ Staff Physical Design Engineer - EMIR CAD","company_name":"Astera Labs","first_published":"2026-03-19T11:38:02-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is establishing a strategic R\u0026amp;amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical \u0026#39;data bottlenecks\u0026#39; enabling the future of AI at scale. As we expand our presence in Israel, we\u0026#39;re seeking a highly skilled Physical Design Engineer specializing in EMIR CAD to join our local engineering powerhouse from the ground up.\u0026lt;/p\u0026gt;\n\u0026lt;p data-path-to-node=\u0026quot;4\u0026quot;\u0026gt;This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world\u0026#39;s largest AI clusters. As a Physical Design Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon.\u0026lt;/p\u0026gt;\n\u0026lt;p data-path-to-node=\u0026quot;5\u0026quot;\u0026gt;You will continuously develop the Electro-Migration and IR Drop (EMIR) flow, working closely at the intersection of Physical Design, Analog/Mixed-Signal design, and Package Engineering.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,0,0\u0026quot;\u0026gt;Take responsibility on IR drop analysis and signal/power electromigration (EM) flow\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,1,0\u0026quot;\u0026gt;Implement and maintain robust EMIR flows and methodologies using industry-standard tools (Ansys RedHawk-SC, Cadence Voltus, or equivalent)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,3,0\u0026quot;\u0026gt;Collaborate closely with Analog/SerDes designers to integrate current profiles and ensure robust power delivery to sensitive high-speed IP blocks\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,4,0\u0026quot;\u0026gt;Partner with Package Design engineers to perform Chip-Package-System (CPS) co-analysis flow\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,5,0\u0026quot;\u0026gt;Understand root-cause analysis for voltage drop violations and EM risks\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,7,0\u0026quot;\u0026gt;Support silicon bring-up by correlating simulation results with actual silicon measurements and yield data\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,0,0\u0026quot;\u0026gt;Bachelor\u0026#39;s or Master\u0026#39;s degree in Electrical Engineering or a related technical field\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,1,0\u0026quot;\u0026gt;5+ years of hands-on experience in EMIR/Power Integrity analysis for high-performance SoCs or high-speed connectivity products\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,2,0\u0026quot;\u0026gt;Strong proficiency in industry-standard EMIR tools flow development (Ansys RedHawk/RedHawk-SC, or Cadence Voltus)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,3,0\u0026quot;\u0026gt;Deep understanding of EM/IR challenges in advanced FinFET nodes (7nm, 5nm, 3nm)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,4,0\u0026quot;\u0026gt;Basic understanding of Place \u0026amp;amp; Route flows, power grid synthesis, extraction (RC), and standard cell architecture\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,6,0\u0026quot;\u0026gt;Proven Proficiency in Python in required, Tcl or Perl preferable for flow automation and data parsing\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,6,0\u0026quot;\u0026gt;Deep understanding of the RedHawk tool, including efficient use of MapReduce and other Ansys proprietary capabilities (including potential use of ad-hoc SDC for context and LSO – Logic State Override)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,6,0\u0026quot;\u0026gt;Strong understanding of required inputs for creating Scenarios and Analysis Views\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,6,0\u0026quot;\u0026gt;Deep understanding of standard cell and IP abstractions (APL, LIB, AVM), including IP waveform construction from PWL (sim2iprof)\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Preferred Experience\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;11,2,0\u0026quot;\u0026gt;Experience performing Chip-Package-System (CPS) thermal and power co-simulation\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;11,3,0\u0026quot;\u0026gt;Familiarity with thermal analysis tools and their interaction with electrical performance\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;11,4,0\u0026quot;\u0026gt;Experience working with sign-off criteria and margins for high-volume production chips\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;11,4,0\u0026quot;\u0026gt;Basic understanding of timing and P\u0026amp;amp;R\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;11,4,0\u0026quot;\u0026gt;Good understanding of EM, including deterministic EM (DC, peak, RMS)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;11,4,0\u0026quot;\u0026gt;Basic understanding of statistical EM and reliability concepts (SEB, Black’s Equation, FIT, MTTF)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;11,4,0\u0026quot;\u0026gt;Basic understanding of packaging, top metal layers, MIM capacitor usage, and power distribution\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4008937005,"name":"Israel","location":"Israel","child_ids":[4061058005,4052111005,4056876005],"parent_id":null}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4674520005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4425426005,"location":{"name":"Israel"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Physical Design/DFT","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4674520005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2378","title":"Senior/ Staff Physical Design STA Engineer ","company_name":"Astera Labs","first_published":"2026-03-18T12:58:06-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is establishing a strategic R\u0026amp;amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical \u0026#39;data bottlenecks\u0026#39; enabling the future of AI at scale. As we expand our presence in Israel, we\u0026#39;re seeking a highly skilled \u0026lt;strong\u0026gt;Static Timing Analysis (STA) Engineer \u0026lt;/strong\u0026gt;to join our local engineering powerhouse from the ground up.\u0026lt;/p\u0026gt;\n\u0026lt;p data-path-to-node=\u0026quot;4\u0026quot;\u0026gt;This is a unique opportunity to take on meaningful technical ownership in a new site, executing the sign-off methodology for chips that power the world\u0026#39;s most advanced AI clusters. As an STA Engineer, you will be deeply involved in the STA activities from chip partition and time budgeting through to final sign-off. You will bridge the gap between Architecture, Design, DFT, and Physical Design to ensure our high-performance silicon meets the aggressive timing targets required for next-generation connectivity.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;6,0,0\u0026quot;\u0026gt;Execute the STA flow and sign-off methodologies, ensuring our products meet rigorous timing criteria for the most demanding data center environments\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;6,1,0\u0026quot;\u0026gt;Collaborate closely with Architecture, Design, DFT, and Backend teams, participating in timing reviews and working with block owners to navigate the path to sign-off convergence\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;6,2,0\u0026quot;\u0026gt;Develop, optimize, and manage complex SDC constraints, ensuring they are accurate and robust across multi-scenario environments\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;6,3,0\u0026quot;\u0026gt;Analyze and resolve challenges related to cross-chip clock distribution networks and apply sophisticated margining techniques to ensure robust silicon across all process corners\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;6,4,0\u0026quot;\u0026gt;Participate in design methodology improvements and tool automation, utilizing both industry-standard EDA tools and custom scripts to make our sign-off process faster and more efficient\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;8,0,0\u0026quot;\u0026gt;B.Sc. in Electrical Engineering or Computer Engineering\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;8,1,0\u0026quot;\u0026gt;5+ years of hands-on experience in Static Timing Analysis (STA) at semiconductor companies, specifically working on advanced process technologies. \u0026lt;em data-path-to-node=\u0026quot;8,1,0\u0026quot; data-index-in-node=\u0026quot;147\u0026quot;\u0026gt;(Note: Adjust years of experience based on the exact level you are targeting)\u0026lt;/em\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;8,2,0\u0026quot;\u0026gt;Deep expertise in multi-scenario STA, as well as timing and SDC constraint development and verification at the block and subsystem levels\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;8,3,0\u0026quot;\u0026gt;Solid understanding of advanced margining methodologies, including OCV, AOCV, and POCV, from synthesis through to final sign-off\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;8,4,0\u0026quot;\u0026gt;Solid knowledge of physical design flows (Synthesis, P\u0026amp;amp;R, Physical Verification) and how they intersect with timing closure\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Preferred Experience\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;10,0,0\u0026quot;\u0026gt;Experience developing and validating constraints using industry-standard tools like Timing Constraints Manager (Synopsys) or TimeVision (Ausdia)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;10,1,0\u0026quot;\u0026gt;Proven track record of executing STA on complex Macro-level designs and supporting Full-Chip timing integration\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;10,2,0\u0026quot;\u0026gt;Strong background in scripting (Tcl, Python, Perl) and automation to enhance timing closure efficiency\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4008937005,"name":"Israel","location":"Israel","child_ids":[4061058005,4052111005,4056876005],"parent_id":null}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4677663005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4426976005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"System Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4677663005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2409","title":"Senior / Staff System Validation Engineer","company_name":"Astera Labs","first_published":"2026-03-30T16:15:56-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Job Description\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Develop and perform system validation tests using leading-edge Data Center equipment and scalable automation platforms. The validation team holds customers’ system requirements in the highest regard and is solely responsible for certifying a product’s conformance to this high bar.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Understand the performance and functionality requirements our AI fabric Switches must deliver to enable customers developing Data Center systems using Astera Labs’ game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Formulate a comprehensive validation plan for AI fabric switch products. automate the testing of ICs and board products in a data-centric manner, design experiments to root-cause unexpected behavior, report results and specification compliance in an automated fashion.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work with key customers directly to understand their care-abouts and highlight the unique capabilities and performance of Astera Labs’ solutions.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong academic and technical background in Electrical or Computer Engineering. At a minimum, a Bachelor’s is required, and a Master’s is preferred.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;≥3 years\u0026#39; experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Basic understanding of x86/ARM architecture, UEFI/Linux boot sequence.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Good understanding of High Speed Signaling Principles.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer/internal meetings in advance, and to work with minimal guidance and supervision.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Entrepreneurial, open-mind behavior and can-do attitude. Think and act with the customer in mind!\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Experience\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Hands-on, thorough knowledge of high-speed protocols like \u0026amp;nbsp;PCIe, CXL, NVMe, or Ethernet.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with Silicon/System bring-up, validation, and debug experience, including in customer systems.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;A strong background in developing bench automation techniques, especially using Python,\u0026amp;nbsp;with emphasis on\u0026amp;nbsp;execution efficiency, repeatability, data analysis and reporting.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with lab equipment including protocol analyzers, in-circuit debuggers, and CPU-based tool suites.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ability to work on multiple projects.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Experience\u0026lt;/strong\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Working knowledge of C or C++ for embedded FW and device drivers.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with PCIe compliance standards and ability to follow and be involved in compliance consortiums to adapt the tests to be run from X86/ARM based platforms.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of schematic capture and PCB layout tools from Cadence Allegro, Altium, etc.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Exceptional interpersonal and collaboration skills, with a proven track record of effectively leading, influencing, and navigating complex matrixed environments.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Your base salary will be determined based on your experience and the pay of employees in similar positions. The base salary range is $135,000 USD - $165,000 USD for Senior Level, and $160,000 USD - $195,000 USD for Staff Level.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025528005,"name":"Software Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4564787005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4372980005,"location":{"name":"San Jose, United States"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Hardware Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4564787005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"1772","title":"Senior/Tech Lead Silicon Validation Engineer","company_name":"Astera Labs","first_published":"2025-05-27T12:54:21-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Job Description:\u0026lt;/strong\u0026gt;\u0026lt;br\u0026gt;At Astera Labs, we are looking for motivated \u0026lt;strong\u0026gt;Senior / Tech Lead Post-Silicon Validation Engineers\u0026lt;/strong\u0026gt; to work on our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role you will formulate a comprehensive post-Silicon validation plan, automate the testing of ICs and board products, design experiments to root-cause unexpected behavior, report results and specification compliance, and work with key internal customers to quantify margins and ensure robustness. The mission of this role is to develop and execute electrical validation tests to quantify parametric device performance and margins over all system conditions. The validation team holds customers’ requirements in the highest regard and is solely responsible for certifying a product’s parametric conformance to this high bar.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong academic and technical background in Electrical or Computer Engineering. At minimum, a Bachelor’s is required, and a Master’s is preferred.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;≥3 years’ experience testing, supporting or developing complex SoC/silicon products and high-speed IO/SerDes electrical interface for Server, Storage, and/or Networking applications.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for internal meetings in advance, and to work with minimal guidance and supervision.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven track record solving problems independently, preferably as a tech lead.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Experience:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience working on debug and bring-up of complicated SoC’s with high-speed interfaces such as PCIe/802.3x Ethernet.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong problem-solving skills, ability to solve problems independently.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Basic knowledge of key, high-speed design blocks such as PLL’s, CTLE, DFE, Tx EQ, and both NRZ and PAM4 signaling.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong python scripting and coding ability: knowledge of object-oriented programming and basic dev ops using git for source control and collaboration.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency using high-speed lab equipment such as BERT, Oscilloscope, and VNA\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Experience:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience in system testing, characterization, margin analysis and optimization of high-speed, multi-gigabit data links over long and short channels\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with PCIe or Ethernet especially Electrical Compliance sections\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience with signal integrity, especially as it relates to PCIe/Ethernet testing and CEM/NVMe interfaces\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026amp;nbsp;Working knowledge of C or C++ for embedded FW\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026amp;nbsp;Familiarity with IEEE 802.3x Ethernet standards and both NRZ and PAM-4 signaling\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026amp;nbsp;Working knowledge of common serial data specifications such as I2C, SPI, etc\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026amp;nbsp;Knowledge of simulation tools such as MATLAB, Keysight ADS, or PLTS for data analysis and modeling of electrical channel and signal integrity issues\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Your base salary will be determined based on your experience and the pay of employees in similar positions. The base salary range is $148,500 USD - $165,000 USD for Senior level, and $175,000 USD - $195,000 USD for Staff level.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025526005,"name":"Hardware Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4701820005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4438688005,"location":{"name":"Tel Aviv-Yafo, Tel Aviv District, Israel"},"metadata":[{"id":12122734005,"name":"Country","value":"Israel","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Tel-Aviv","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Program Management","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4701820005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2608","title":"Silicon Technical Program Manager ","company_name":"Astera Labs","first_published":"2026-06-02T14:13:13-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is establishing a strategic R\u0026amp;amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical \u0026#39;data bottlenecks\u0026#39; enabling the future of AI at scale. As we expand our presence in Israel, we\u0026#39;re seeking a visionary \u0026lt;strong\u0026gt;Silicon Technical Program Manager\u0026amp;nbsp;\u0026amp;nbsp;\u0026lt;/strong\u0026gt;to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, leading the physical implementation strategy for chips that power the world\u0026#39;s largest AI clusters.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p data-path-to-node=\u0026quot;3\u0026quot;\u0026gt;As an\u0026amp;nbsp;Technical Program Manager, you will be the key architect of our silicon’s operational reality. You won’t just track timelines - you will help establish our local execution culture and technical standards, owning the cross-functional journey of transforming complex logic into high-performance silicon.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul type=\u0026quot;disc\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;x_MsoNormal\u0026quot;\u0026gt;Drive and manage ASIC development and subsystems from concept through to production in collaboration with internal teams and external vendors.\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_MsoNormal\u0026quot;\u0026gt;Provide hands-on program management throughout the full development cycle of silicon and firmware, including concept, design, development, fabrication, validation, and production release.\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_MsoNormal\u0026quot;\u0026gt;Work closely with the software, hardware, and architecture teams to align with product requirements and ensure all constraints are met.\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_MsoNormal\u0026quot;\u0026gt;Lead process improvements across multiple teams and functions to drive better collaboration and efficiency.\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_MsoNormal\u0026quot;\u0026gt;Independently manage complex projects with minimal supervision, ensuring timelines and milestones are met.\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_MsoNormal\u0026quot;\u0026gt;Deliver high-quality ASIC solutions products while collaborating with product management and architecture teams.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul type=\u0026quot;disc\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;x_MsoNormal\u0026quot;\u0026gt;\u0026lt;span data-olk-copy-source=\u0026quot;MessageBody\u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Computer Science, Electrical Engineering, or a related technical field\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_MsoNormal\u0026quot;\u0026gt;8+ years of experience in ASIC development and 3+ years in Program or Product Management or Technical/Engineering management\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_MsoNormal\u0026quot;\u0026gt;Proven leadership skills, with the ability to manage projects from technical details to the big picture\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_MsoNormal\u0026quot;\u0026gt;Experience in managing ASIC design flow, RTL, synthesis, functional verification, and physical layout\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_MsoNormal\u0026quot;\u0026gt;Experience in pre-silicon testing (Emulation, FPGA) and post-silicon validation is preferred\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_MsoNormal\u0026quot;\u0026gt;Excel in interpersonal communication, relationship building, and collaboration within cross-functional teams\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_MsoNormal\u0026quot;\u0026gt;Excellent organizational and leadership skills, and are capable of multitasking in a fast-paced environment\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul type=\u0026quot;disc\u0026quot;\u0026gt;\n\u0026lt;li class=\u0026quot;x_MsoNormal\u0026quot;\u0026gt;\u0026lt;span data-olk-copy-source=\u0026quot;MessageBody\u0026quot;\u0026gt;Familiarity with Networking technologies and concepts\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;x_MsoNormal\u0026quot;\u0026gt;Excellent strategic planning and communication skills, with a self-motivated focus on execution\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4043426005,"name":"Program Management","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4008937005,"name":"Israel","location":"Israel","child_ids":[4061058005,4052111005,4056876005],"parent_id":null}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4695205005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4435741005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose (HQ)","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Product Management","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4695205005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2548","title":"Sr. Director of Product Marketing","company_name":"Astera Labs","first_published":"2026-05-13T19:02:37-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is seeking a Senior Director of Product Marketing to lead go-to-market strategy for our industry-leading fabric switch and memory controller solutions. This is a high-impact leadership role at the intersection of technology and market strategy, where you\u0026#39;ll shape how the world\u0026#39;s largest hyperscalers and AI infrastructure builders understand and adopt our connectivity products.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As a senior leader on the product marketing team, you\u0026#39;ll drive positioning, messaging, and competitive strategy for products enabling the next generation of AI and cloud data centers. You\u0026#39;ll partner closely with engineering, sales, and executive leadership to translate customers’ needs into competitive roadmaps and compelling value propositions that resonate with decision-makers. This role requires someone who can move fluidly between silicon-level technical discussions and strategic market conversations.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;With AI infrastructure demand accelerating and Astera Labs at the forefront of solving critical connectivity bottlenecks, this is an opportunity to shape the narrative for technologies like PCIe, UALink, CXL and emerging high-speed protocols that are powering rack-scale AI systems worldwide.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Go-to-Market Strategy \u0026amp;amp; Execution\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Lead product strategy, positioning, and go-to-market strategy for fabric switch and controller product lines\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Define and execute product launches that drive awareness, demand, and adoption with hyperscaler and enterprise customers\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop compelling content including presentations, blogs, datasheets, and technical collateral\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Market \u0026amp;amp; Competitive Intelligence\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Own competitive analysis and market intelligence for fabric switch controller product lines\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Identify market trends, customer needs, and emerging opportunities in AI infrastructure connectivity\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Translate market insights into actionable product and positioning recommendations\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional Leadership\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Partner with engineering to deeply understand product capabilities and drive roadmap\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Enable sales teams with training, tools, and competitive positioning to win strategic accounts\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with executive leadership to align product marketing initiatives with corporate strategy\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Team \u0026amp;amp; Stakeholder Management\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Build and mentor a high-performing product marketing team\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Serve as a technical spokesperson at industry events, customer meetings, and analyst briefings\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive alignment across marketing, product, and sales organizations\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, Computer Engineering, or related technical field\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;12+ years of experience in product marketing, product management, or technical marketing roles\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Demonstrated experience with PCIe technology or high-speed switching/interconnect products\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of semiconductor products and silicon development lifecycle\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven track record of leading successful product launches in the data center or infrastructure market\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience presenting to and influencing technical audiences including engineers and architects\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;MBA or Master\u0026#39;s degree in a technical discipline\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience marketing to hyperscaler and enterprise customers (AWS, Google, Microsoft, Meta, etc.)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with high speed connectivity protocols, such as UALink, PCIe, and CXL\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Background in AI/ML infrastructure or data center architecture\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience building and leading product marketing teams at high-growth technology companies\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong executive presence and public speaking skills for industry events and analyst engagements\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Salary range is $240,000 to $300,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4000198005,"name":"Product Management","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4652764005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4415582005,"location":{"name":"San Jose, CA"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Analog/Mixed-Signal","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4652764005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2228","title":"Sr. Principal DSP Architect (Optical Transceivers \u0026 PAM4)","company_name":"Astera Labs","first_published":"2026-01-26T15:46:20-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Role Overview As a Sr. Principal DSP Architect, you will be the technical visionary leading the definition and development of next-generation Digital Signal Processing (DSP) architectures. Your focus will be on high-speed PAM4 (Pulse Amplitude Modulation 4-level) systems and coherent/direct-detect optical transceivers. You will bridge the gap between theoretical communications theory and silicon implementation, driving the roadmap for 800G, 1.6T, and beyond.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Key Responsibilities\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Architectural Leadership: Lead the definition of DSP micro-architecture for high-performance ASICs, focusing on low-power, high-throughput data paths.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Algorithm Development: Design, model, and simulate advanced DSP algorithms for:\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Adaptive Equalization (FFE, DFE, MLSE).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Forward Error Correction (FEC).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Clock and Data Recovery (CDR).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Chromatic Dispersion (CD) and Polarization Mode Dispersion (PMD) compensation.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Modeling \u0026amp;amp; Simulation: Develop bit-accurate and performance-accurate models using Python, MATLAB, or C++ to validate architectural choices against Bit Error Rate (BER) targets.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Cross-Functional Collaboration: Work closely with Analog Mixed-Signal (AMS) designers to optimize the ADC/DAC interface and with RTL teams to ensure power-efficient hardware implementation.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Performance Trade-offs: Conduct rigorous Power, Performance, and Area (PPA) analysis to balance complex DSP requirements with the thermal and size constraints of optical modules (e.g., QSFP-DD, OSFP).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Standards Contribution: Represent the company in industry standards bodies (IEEE 802.3, OIF) to influence future optical communications protocols.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Required Qualifications\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Education: PhD or MS in Electrical Engineering, Communication Theory, or a related field.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience: 12+ years of experience in DSP design, specifically for high-speed SerDes or optical communications.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Technical Deep Dive:\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Expertise in PAM4 signaling and the associated challenges (non-linearity, SNR requirements).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep understanding of Digital Filter Design (FIR, IIR) and adaptive signal processing.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with high-speed ADC/DAC architectures and their impact on DSP performance.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Tooling: Proficiency in MATLAB/Simulink, Python (NumPy/SciPy), and SystemC.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Silicon Success: A proven track record of taking complex DSP architectures from concept through tape-out to high-volume production.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Preferred Skills\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Experience with Coherent Optical technologies (QAM, polarization multiplexing).\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of Machine Learning applications in DSP for non-linearity compensation.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with hardware description languages (Verilog/SystemVerilog) and the synthesis flow\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;The base salary range is $210,000 USD – $260,000 USD. Your base salary will be determined based on location, experience, and employees\u0026#39; pay in similar positions.\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4135671005,"name":"SerDes","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4646964005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4412709005,"location":{"name":"San Jose, CA "},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Product Management","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4646964005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2190","title":"Sr. Principal Product Manager - Scorpio","company_name":"Astera Labs","first_published":"2026-01-14T12:43:18-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Are you passionate about creating differentiated products and working with hyperscale and AI platform providers to deploy the next generation of data center infrastructure?\u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; \u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;We are seeking a highly technical and experienced product manager to join our team at Astera Labs. As a key member of our product management team, you will work closely with customers, product marketing and other cross-functional teams to define and deliver competitive silicon, hardware and software solutions. With high visibility to the executive team and customers, this role requires strong leadership and communication skills, and a blend of technical expertise and market insight within your product domain.\u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; \u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;This is a unique opportunity to play a pivotal role in the success of our Scorpio Smart Fabric Switch portfolio. We are scaling our product team to support our worldwide customers, offering ample opportunities for growth and advancement within the product team.   \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Based in San Jose, CA, this position requires an in-person presence with travel to customers.\u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; \u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; \u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Own product definition:\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Define detailed product requirements and prioritize features, enhancements, and bug fixes based on business goals and customer feedback.\u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; \u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Lead customer technical engagement:\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Work closely with lighthouse customers to translate their needs to competitive product requirements and secure new\u0026amp;nbsp;design-wins\u0026amp;nbsp;throughout the product lifecycle.\u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; \u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Support go-to-market:\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Leverage technical and product expertise to support product marketing and corporate marketing teams on go-to-market planning and execution, sales enablement, competitive analysis, and product positioning.\u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; \u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Lead product planning:\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Work closely with product marketing to translate product strategy into executable product plans and collaborate with Astera Labs cross-functional teams to drive products from ideation to launch.\u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; \u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Qualifications\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; \u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Bachelor’s degree in engineering or compute science\u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; \u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;10+ years of experience in product management, technical product marketing, applications or other customer-facing product roles within the semiconductor industry \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Proven track record of defining and launching successful semiconductor products\u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; \u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;(switch products are a plus) \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Deep understanding of high-speed protocols (PCIe/CXL and/or\u0026amp;nbsp;UALink\u0026amp;nbsp;are required; Ethernet and other protocols are a plus) and system architectures used in cloud and AI infrastructure\u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; \u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Strong strategic thinking and analytical skills, with the ability to translate customer pain points into competitive products\u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; \u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Excellent communication and presentation skills, with the ability to articulate complex technical concepts in a clear and compelling manner\u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; \u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Proven ability to collaborate effectively with cross-functional teams and drive consensus in a fast-paced, dynamic environment\u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; \u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Results-oriented mindset with a focus on driving measurable impact and achieving business objectives\u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; \u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Experience working with customers and partners to understand their needs and drive product definition\u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; \u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Willingness to travel as needed for customer meetings, industry events, and trade shows\u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; \u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;If you are passionate about driving innovation and shaping the future of data center connectivity through world-class products, we encourage you to apply. Join Astera Labs in unleashing the potential of cloud and AI infrastructure!\u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; \u0026lt;/span\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt; \u0026lt;/span\u0026gt;\u0026amp;nbsp;\u0026lt;br\u0026gt;\u0026amp;nbsp;\u0026lt;br\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Compensation will be based on leveling and experience.\u0026lt;/span\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Base Salary Range $210,000 - $255,000\u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4000198005,"name":"Product Management","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4646965005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4412710005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Product Management","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4646965005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2191","title":"Sr. Principal Product Marketer - Leo","company_name":"Astera Labs","first_published":"2026-01-14T12:42:48-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is seeking a Senior Principal, Product Marketing to serve as the strategic marketing leader for our Leo Smart Memory Extender product line — the industry\u0026#39;s most advanced CXL-based solution enabling memory expansion and disaggregation for AI and cloud infrastructure at rack scale. This is a senior individual contributor role with outsized influence, where you\u0026#39;ll define how the market understands, evaluates, and adopts CXL memory technology.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As AI models scale to hundreds of billions of parameters and memory capacity becomes the defining bottleneck in modern data centers, Leo is uniquely positioned to unlock new levels of performance and efficiency. In this role, you\u0026#39;ll operate as the authoritative voice of the Leo product line — shaping narratives that influence hyperscaler architecture decisions, driving industry thought leadership, and partnering with Astera Labs\u0026#39; most senior technical and business leaders to accelerate market creation.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This is a rare opportunity to own the marketing strategy for a category-defining product at a hyper-growth public semiconductor company that is building the connectivity backbone of AI infrastructure. You\u0026#39;ll combine deep technical mastery of CXL and memory architectures with world-class marketing craft to drive outsized business impact.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;Based in San Jose, CA or Vancouver, BC, this position requires an in-person presence with travel to customers. \u0026lt;/span\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Market Strategy \u0026amp;amp; Positioning\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Own end-to-end go-to-market strategy for the Leo Smart Memory Extender portfolio, from early market development through production ramp and lifecycle management\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Define differentiated positioning and messaging frameworks that articulate Leo\u0026#39;s value to platform architects, memory subsystem engineers, and CTO-level decision-makers at hyperscalers and OEMs\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Lead competitive analysis and market segmentation to identify whitespace opportunities and inform product roadmap investment priorities\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Thought Leadership \u0026amp;amp; Industry Influence\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Serve as Astera Labs\u0026#39; external subject matter expert on CXL memory expansion, representing the company at keynotes, panels, analyst briefings, and consortium forums\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Develop high-impact technical content including white papers, architecture guides, solution briefs, and reference designs that shape industry conversation\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Build and maintain relationships with key industry analysts, media, and ecosystem partners to amplify Leo\u0026#39;s market presence\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Cross-Functional Leadership \u0026amp;amp; Enablement\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Partner with product management and silicon engineering to translate roadmap innovations into compelling customer-facing narratives and launch strategies\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Develop advanced sales enablement assets — competitive battlecards, technical presentations, ROI models, and objection-handling frameworks — that accelerate deal velocity\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Engage directly with strategic customers in executive briefings and design-win pursuits, serving as a trusted technical marketing advisor\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Market Intelligence \u0026amp;amp; Business Impact\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Synthesize insights from customer engagements, competitive dynamics, and technology trends to influence Leo product strategy and investment decisions\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Track the evolving CXL ecosystem, memory disaggregation architectures, and AI infrastructure spending patterns to keep Astera Labs ahead of market inflection points\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Define and measure marketing effectiveness through pipeline contribution, content engagement, and market awareness metrics\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, Computer Science, or a related technical field\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;12+ years of experience in product marketing, technical marketing, or strategic marketing roles in the semiconductor or data center infrastructure industry\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Deep technical understanding of CXL protocol, memory subsystem architectures, and data center platform design\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Proven track record of positioning and launching complex silicon products to hyperscale and enterprise customers\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Exceptional ability to craft compelling technical narratives for audiences ranging from system architects to C-suite executives\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience operating as a senior individual contributor with cross-functional influence across engineering, product, sales, and executive leadership\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Master\u0026#39;s degree in Electrical Engineering, Computer Science, or MBA\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Direct experience marketing CXL, DDR/HBM memory technologies, or coherent interconnect solutions\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Established relationships with hyperscaler architecture teams and/or Tier-1 OEM partners\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Track record of keynote speaking, published white papers, or recognized thought leadership in the memory/interconnect space\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;auto\u0026quot;\u0026gt;The salary range for this position is $180,000 to $250,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;br\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4000198005,"name":"Product Management","child_ids":[],"parent_id":null}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4703779005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4439618005,"location":{"name":"Tel Aviv-Yafo, Tel Aviv District, Israel"},"metadata":[{"id":12122734005,"name":"Country","value":"Israel","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Tel-Aviv","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Physical Design/DFT","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4703779005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2625","title":"Staff Physical Design Engineer - SoC EMIR Engineer","company_name":"Astera Labs","first_published":"2026-06-07T07:55:28-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is establishing a strategic R\u0026amp;amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical \u0026#39;data bottlenecks\u0026#39; enabling the future of AI at scale. As we expand our presence in Israel, we\u0026#39;re seeking a highly skilled Physical Design Engineer specializing in SoC EMIR to join our local engineering powerhouse from the ground up.\u0026lt;/p\u0026gt;\n\u0026lt;p data-path-to-node=\u0026quot;4\u0026quot;\u0026gt;This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world\u0026#39;s largest AI clusters. As an EMIR Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon.\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;margin: 0in; font-family: Calibri; font-size: 11.0pt;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;You will be responsible for SoC EMIR Analysis to ensure our products meet aggressive voltage drop and reliability targets in advanced FinFET process nodes, directly impacting the performance and yield of chips operating in the world\u0026lt;/span\u0026gt;\u0026lt;span lang=\u0026quot;en-IL\u0026quot;\u0026gt;’\u0026lt;/span\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;s most demanding AI and cloud environments.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,0,0\u0026quot;\u0026gt;Take responsibility on IR drop analysis and signal/power electromigration (EM) of very complex chip\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,3,0\u0026quot;\u0026gt;Collaborate closely with Physical Design team to insure a full power integrity\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,4,0\u0026quot;\u0026gt;Partner with Package Design engineers to perform Chip-Package co-analysis (CPM)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,5,0\u0026quot;\u0026gt;Understand root-cause analysis for voltage drop violations and EM risks\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,0,0\u0026quot;\u0026gt;Bachelor\u0026#39;s or Master\u0026#39;s degree in Electrical Engineering or a related technical field\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,1,0\u0026quot;\u0026gt;7+ years of hands-on experience in EMIR/Power Integrity analysis for high-performance SoCs or high-speed connectivity products\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,2,0\u0026quot;\u0026gt;Strong proficiency in industry-standard EMIR tools (Ansys RedHawk/RedHawk-SC, or Cadence Voltus)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,3,0\u0026quot;\u0026gt;Deep understanding of EM/IR challenges in advanced FinFET nodes (7nm, 5nm, 3nm)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,4,0\u0026quot;\u0026gt;Deep understanding of Place \u0026amp;amp; Route flows, power grid synthesis, extraction (RC), and standard cell architecture\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,4,0\u0026quot;\u0026gt;Deep understanding of EM and trade-offs between signal EM and power grid (PG) EM\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Preferred Experience\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;11,3,0\u0026quot;\u0026gt;Familiarity with thermal analysis tools and their interaction with electrical performance\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;11,4,0\u0026quot;\u0026gt;Experience working with sign-off criteria and margins for high-volume production chips\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;11,4,0\u0026quot;\u0026gt;Good understanding of timing and P\u0026amp;amp;R\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;11,4,0\u0026quot;\u0026gt;Basic understanding of packaging, top metal layers, MIM capacitor usage, and power distribution\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;11,4,0\u0026quot;\u0026gt;Ability to write TCL scripts for STA and Fusion Compiler (FC)\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4008937005,"name":"Israel","location":"Israel","child_ids":[4061058005,4052111005,4056876005],"parent_id":null}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4701334005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4438398005,"location":{"name":"Tel Aviv-Yafo, Tel Aviv District, Israel"},"metadata":[{"id":12122734005,"name":"Country","value":"Israel","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Tel-Aviv","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Design Verification","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4701334005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2602","title":"Staff/ Principal Design Verification Engineer ","company_name":"Astera Labs","first_published":"2026-06-01T05:43:59-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is establishing a strategic R\u0026amp;amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical \u0026#39;data bottlenecks\u0026#39; enabling the future of AI at scale. As we expand our presence in Israel, we\u0026#39;re seeking a talented \u0026lt;strong\u0026gt;Staff/ Principal Design Verification Engineer\u0026lt;/strong\u0026gt;\u0026amp;nbsp;to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, developing the verification environments that ensure our next-generation AI silicon performs flawlessly.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As a \u0026lt;strong\u0026gt;Staff/ Principal Design Verification Engineer\u0026lt;/strong\u0026gt;, you will be a vital contributor to the quality and reliability of our Israel R\u0026amp;amp;D center. You will work on the front lines of functional verification, developing testbenches and environments that validate high-performance digital blocks, subsystems, and full-chip designs. You will tackle complex verification challenges that ensure our connectivity solutions meet the rigorous demands of the world\u0026#39;s largest AI clusters. If you thrive on solving technical puzzles and want to play a key role in delivering cutting-edge AI infrastructure connectivity, this is your opportunity.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Verification Environment Development\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Contribute to the design and development of ASIC verification environments, focusing on unit-level and subsystem functional blocks\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Develop and maintain SystemVerilog/UVM-based components including traffic generators, monitors, and checkers to ensure robust testing\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Execute detailed verification plans for challenging digital designs, ensuring all functional requirements are met and verified\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Coverage \u0026amp;amp; Quality Assurance\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Implement functional coverage models and analyze results to identify gaps in the verification process\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Drive designs toward 100% verification closure through comprehensive test development\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Contribute to verification methodology improvements and best practices\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Debug \u0026amp;amp; Cross-Functional Collaboration\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Work closely with design engineers to identify, root-cause, and resolve complex hardware bugs early in the development cycle\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Apply analytical skills and debugging techniques to solve intricate verification challenges\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Collaborate effectively in a fast-paced, team-oriented R\u0026amp;amp;D environment\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering or related technical field\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;5+ years of proven experience in ASIC verification within the semiconductor industry\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Hands-on experience developing components within complex verification environments using SystemVerilog\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Strong working knowledge of standard verification methodologies, specifically UVM\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Sharp analytical mind with passion for debugging and technical problem-solving\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Excellent communication skills with ability to thrive in collaborative R\u0026amp;amp;D environments\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Master\u0026#39;s degree in Electrical Engineering or related field\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Familiarity with Formal Verification or Emulation flows\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Basic proficiency in scripting languages such as Python or Tcl to automate verification tasks\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Exposure to industry-standard protocols such as AMBA, PCIe, Ethernet, or CXL\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience with assertion-based verification and constrained-random testing\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Background in connectivity or networking silicon verification\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4052111005,"name":"Haifa","location":"Haifa, Israel","child_ids":[],"parent_id":4008937005},{"id":4056876005,"name":"Tel Aviv","location":"Tel Aviv, Israel","child_ids":[],"parent_id":4008937005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4674496005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4425410005,"location":{"name":"Israel"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Design Verification","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4674496005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2374","title":"Staff/ Principal Formal Verification Engineer","company_name":"Astera Labs","first_published":"2026-03-18T12:55:17-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is establishing a strategic R\u0026amp;amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical \u0026#39;data bottlenecks\u0026#39; enabling the future of AI at scale. As we expand our presence in Israel, we\u0026#39;re seeking a visionary \u0026lt;strong\u0026gt;Formal Verification Engineer\u0026lt;/strong\u0026gt; to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the formal verification strategy for chips that power the world\u0026#39;s largest AI clusters.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span class=\u0026quot;TextRun SCXW214065216 BCX0\u0026quot; lang=\u0026quot;EN-US\u0026quot; data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;NormalTextRun SCXW214065216 BCX0\u0026quot;\u0026gt;As the Formal Verification Engineer, you will be a foundational member of our Israel R\u0026amp;amp;D center. You won’t just execute tasks; you will define the\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span class=\u0026quot;TextRun SCXW214065216 BCX0\u0026quot; lang=\u0026quot;EN-US\u0026quot; data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;NormalTextRun SCXW214065216 BCX0\u0026quot;\u0026gt;Formal verification strategy\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;span class=\u0026quot;TextRun SCXW214065216 BCX0\u0026quot; lang=\u0026quot;EN-US\u0026quot; data-contrast=\u0026quot;auto\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;NormalTextRun SCXW214065216 BCX0\u0026quot;\u0026gt; for chips that drive the world’s largest AI clusters. You will dive deep into the technical details, proving the correctness of complex designs and ensuring they flawlessly meet specifications.\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li style=\u0026quot;text-align: left;\u0026quot; data-path-to-node=\u0026quot;6,0,0\u0026quot;\u0026gt;Own and develop formal verification environments from scratch through to sign-off\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;6,1,0\u0026quot;\u0026gt;Apply formal verification methodologies and strategies to prove the correctness of intricate designs\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;6,2,0\u0026quot;\u0026gt;Work closely with the Architecture, Design, and DV teams to identify verification needs and pinpoint design requirements\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;6,3,0\u0026quot;\u0026gt;Create robust formal environments, analyze complex RTL designs, and apply advanced formal techniques to find corner-case bugs\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;6,4,0\u0026quot;\u0026gt;Analyze verification results, identify failures, and collaborate directly with designers to resolve issues efficiently\u0026lt;/li\u0026gt;\n\u0026lt;li style=\u0026quot;text-align: left;\u0026quot; data-path-to-node=\u0026quot;6,5,0\u0026quot;\u0026gt;Architect and develop generic, common formal functions and properties to be reused across multiple projects\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;8,0,0\u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering or a related technical field\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;8,1,0\u0026quot;\u0026gt;5+ years of hands-on experience in Formal Verification within semiconductor companies\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;8,2,0\u0026quot;\u0026gt;Deep expertise in formal verification methodologies, tools, and flows\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;8,3,0\u0026quot;\u0026gt;Strong understanding of RTL design and verification principles\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;8,4,0\u0026quot;\u0026gt;Experience with industry-standard formal verification tools (Jasper, VC Formal, or similar)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;8,5,0\u0026quot;\u0026gt;Excellent communication skills, strong analytical thinking, and a proactive, \u0026quot;can-do\u0026quot; approach to problem-solving\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;10,0,0\u0026quot;\u0026gt;Track record of successfully taking complex blocks or subsystems through the entire formal verification lifecycle\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;10,1,0\u0026quot;\u0026gt;Experience with SystemVerilog UVM-based design verification\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;10,2,0\u0026quot;\u0026gt;Knowledge of networking standards (Ethernet, NVLink, UALink, PCIe)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;10,3,0\u0026quot;\u0026gt;Background in high-speed serial interface verification\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4008937005,"name":"Israel","location":"Israel","child_ids":[4061058005,4052111005,4056876005],"parent_id":null}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4701340005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4438401005,"location":{"name":"Tel Aviv-Yafo, Tel Aviv District, Israel"},"metadata":[{"id":12122734005,"name":"Country","value":"Israel","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Tel-Aviv","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Physical Design","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4701340005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2603","title":"Staff/ Principal Physical Design CAD Engineer","company_name":"Astera Labs","first_published":"2026-06-01T06:04:29-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;span class=\u0026quot;EOP SCXW38165641 BCX0\u0026quot; data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:160}\u0026quot;\u0026gt;Astera Labs is establishing a strategic R\u0026amp;amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical \u0026#39;data bottlenecks\u0026#39; enabling the future of AI at scale. As we expand our presence in Israel, We are looking for a\u0026amp;nbsp;\u0026lt;strong\u0026gt;Physical Design CAD Engineer\u0026lt;/strong\u0026gt;\u0026amp;nbsp;with at least\u0026amp;nbsp;\u0026lt;strong\u0026gt;3 years of hands-on experience\u0026lt;/strong\u0026gt;\u0026amp;nbsp;in digital implementation flows. The ideal candidate is highly technical, curious, and eager to drive innovation by combining strong physical design knowledge with modern automation and\u0026amp;nbsp;\u0026lt;strong\u0026gt;GenAI-based methodologies.\u0026lt;/strong\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p data-path-to-node=\u0026quot;4\u0026quot;\u0026gt;This is a unique opportunity to take on meaningful technical ownership in a new site, implementing the parasitic extraction (PEX) methodologies and flows for chips that power the world\u0026#39;s largest AI clusters. As a foundational member of the team, you will be responsible for the accuracy and efficiency of our extraction environment, ensuring that our high-speed designs are modeled with the highest precision from RTL to GDSII.\u0026lt;/p\u0026gt;\n\u0026lt;p data-path-to-node=\u0026quot;4\u0026quot;\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;p data-olk-copy-source=\u0026quot;MessageBody\u0026quot;\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;p data-olk-copy-source=\u0026quot;MessageBody\u0026quot;\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;p data-olk-copy-source=\u0026quot;MessageBody\u0026quot;\u0026gt;The Engineer will develop, maintain, and improve CAD flows and methodologies for physical design teams, supporting advanced implementation stages from synthesis through place and route, timing closure, power optimization, and signoff readiness.\u0026lt;/p\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;p\u0026gt;Key responsibilities include:\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Develop and support physical design CAD flows using industry-standard EDA tools\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Build automation infrastructure for implementation, analysis, reporting, and debug\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support design teams in areas such as synthesis, floorplanning, placement, CTS, routing, timing, power, and physical verification\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Create scripts and utilities to improve productivity, quality of results, and flow robustness\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Support and enhance flows based on\u0026amp;nbsp;\u0026lt;strong\u0026gt;Synopsys Fusion Compiler\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Explore and integrate\u0026amp;nbsp;\u0026lt;strong\u0026gt;GenAI solutions\u0026lt;/strong\u0026gt; to accelerate debug, automate repetitive tasks, improve reporting, and enhance engineering productivity\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Analyze tool results, logs, QoR metrics, timing reports, congestion, utilization, power, and design-rule issues\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;/div\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;\u0026lt;br\u0026gt;\u0026lt;/span\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-olk-copy-source=\u0026quot;MessageBody\u0026quot;\u0026gt;At least\u0026amp;nbsp;\u0026lt;strong\u0026gt;3 years of experience\u0026lt;/strong\u0026gt; in Physical Design, CAD, or implementation methodology\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of digital physical design concepts, including synthesis, placement, CTS, routing, timing closure, and physical verification\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience with\u0026amp;nbsp;\u0026lt;strong\u0026gt;Synopsys Fusion Compiler\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with scripting languages such as\u0026amp;nbsp;\u0026lt;strong\u0026gt;Tcl, Python\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ability to develop automation around EDA tools and large-scale design flows\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Good understanding of timing, power, congestion, floorplanning, and QoR analysis\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong debugging and problem-solving skills\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ability to work closely with multiple engineering teams and support complex design environments\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;High motivation to learn and apply\u0026amp;nbsp;\u0026lt;strong\u0026gt;GenAI technologies\u0026lt;/strong\u0026gt;\u0026amp;nbsp;in semiconductor design flows.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-ccp-props=\u0026quot;{\u0026amp;quot;134233117\u0026amp;quot;:false,\u0026amp;quot;134233118\u0026amp;quot;:false,\u0026amp;quot;335559738\u0026amp;quot;:0,\u0026amp;quot;335559739\u0026amp;quot;:160}\u0026quot;\u0026gt;\u0026amp;nbsp;\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Preferred Experience\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-olk-copy-source=\u0026quot;MessageBody\u0026quot;\u0026gt;Experience with additional tools such as PrimeTime, StarRC, ICC2, Innovus, Voltus, RedHawk, Calibre, or similar\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of STA, low-power design, UPF, EM/IR, extraction, or signoff flows\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience building dashboards, regression systems, flow checkers, or automated report analyzers\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with LLMs, prompt engineering, AI agents, or GenAI-based coding/debug tools\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with Git, CI/CD, databases, or cloud-based compute environments\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4008937005,"name":"Israel","location":"Israel","child_ids":[4061058005,4052111005,4056876005],"parent_id":null}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4703778005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4439617005,"location":{"name":"Tel Aviv-Yafo, Tel Aviv District, Israel"},"metadata":[{"id":12122734005,"name":"Country","value":"Israel","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Tel-Aviv","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Physical Design/DFT","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4703778005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2624","title":"Staff/ Principal Physical Design Engineer - SoC EMIR Expert","company_name":"Astera Labs","first_published":"2026-06-07T07:55:07-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is establishing a strategic R\u0026amp;amp;D center in Israel to drive the development of complex semiconductor chips that solve the critical \u0026#39;data bottlenecks\u0026#39; enabling the future of AI at scale. As we expand our presence in Israel, we\u0026#39;re seeking a highly skilled Physical Design Engineer specializing in SoC EMIR to join our local engineering powerhouse from the ground up.\u0026lt;/p\u0026gt;\n\u0026lt;p data-path-to-node=\u0026quot;4\u0026quot;\u0026gt;This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world\u0026#39;s largest AI clusters. As an EMIR Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon.\u0026lt;/p\u0026gt;\n\u0026lt;p data-path-to-node=\u0026quot;5\u0026quot;\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;margin: 0in; font-family: Calibri; font-size: 11.0pt;\u0026quot;\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;You will be responsible for SoC EMIR Analysis to ensure our products meet aggressive voltage drop and reliability targets in advanced FinFET process nodes, directly impacting the performance and yield of chips operating in the world\u0026lt;/span\u0026gt;\u0026lt;span lang=\u0026quot;en-IL\u0026quot;\u0026gt;’\u0026lt;/span\u0026gt;\u0026lt;span lang=\u0026quot;en-US\u0026quot;\u0026gt;s most demanding AI and cloud environments.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Key Responsibilities\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,0,0\u0026quot;\u0026gt;Take responsibility on IR drop analysis and signal/power electromigration (EM) of very complex chip\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,3,0\u0026quot;\u0026gt;Collaborate closely with Physical Design team to insure a full power integrity\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,4,0\u0026quot;\u0026gt;Be responsible\u0026amp;nbsp;on IR architecture for timing convergence\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,4,0\u0026quot;\u0026gt;Partner with Package Design engineers to perform Chip-Package co-analysis (CPM)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,5,0\u0026quot;\u0026gt;Understand root-cause analysis for voltage drop violations and EM risks\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;7,5,0\u0026quot;\u0026gt;Be responsible and go-to person for any IR related issues\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,0,0\u0026quot;\u0026gt;Bachelor\u0026#39;s or Master\u0026#39;s degree in Electrical Engineering or a related technical field\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,1,0\u0026quot;\u0026gt;10+ years of hands-on experience in EMIR/Power Integrity analysis for high-performance SoCs or high-speed connectivity products\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,2,0\u0026quot;\u0026gt;Strong proficiency in industry-standard EMIR tools (Ansys RedHawk/RedHawk-SC, or Cadence Voltus)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,3,0\u0026quot;\u0026gt;Deep understanding of EM/IR challenges in advanced FinFET nodes (7nm, 5nm, 3nm)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,4,0\u0026quot;\u0026gt;Deep understanding of Place \u0026amp;amp; Route flows, power grid synthesis, extraction (RC), and standard cell architecture\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,4,0\u0026quot;\u0026gt;Ability to define and own EMIR methodologies\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,4,0\u0026quot;\u0026gt;Capability to identify issues early in the project lifecycle (preferably with experience in sub-N5 TSMC technologies)\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,4,0\u0026quot;\u0026gt;Deep understanding of EM and trade-offs between signal EM and power grid (PG) EM\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;9,4,0\u0026quot;\u0026gt;Thermal analysis, self-heat and Statistical EM proficiency\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;\u0026lt;span data-contrast=\u0026quot;none\u0026quot;\u0026gt;Preferred Experience\u0026lt;/span\u0026gt;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;11,3,0\u0026quot;\u0026gt;Familiarity with thermal analysis tools and their interaction with electrical performance\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;11,4,0\u0026quot;\u0026gt;Experience working with sign-off criteria and margins for high-volume production chips\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;11,4,0\u0026quot;\u0026gt;Good understanding of timing and P\u0026amp;amp;R\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;11,4,0\u0026quot;\u0026gt;Good understanding of packaging, top metal layers, MIM capacitor usage, and power distribution\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;11,4,0\u0026quot;\u0026gt;Understanding of ESD (including full CDM closure) and latch-up\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;11,4,0\u0026quot;\u0026gt;Strong Reliability knowledge\u0026lt;/li\u0026gt;\n\u0026lt;li data-path-to-node=\u0026quot;11,4,0\u0026quot;\u0026gt;Ability to write TCL scripts for STA and Fusion Compiler (FC)\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4008937005,"name":"Israel","location":"Israel","child_ids":[4061058005,4052111005,4056876005],"parent_id":null}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4671898005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4424158005,"location":{"name":"Vancouver, British Columbia, Canada"},"metadata":[{"id":12122734005,"name":"Country","value":"Canada","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Vancouver","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"System Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4671898005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2355","title":"System Validation Engineering Director","company_name":"Astera Labs","first_published":"2026-03-11T14:53:45-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;Astera Labs is seeking an exceptional \u0026lt;strong\u0026gt;Director of System Validation\u0026amp;nbsp;\u0026lt;/strong\u0026gt;to lead our AI Fabric Validation organization. Connectivity is a critical component of every AI accelerator deployment and hyperscale data center architecture. As part of the AI Fabric Engineering group, you will play a key role in ensuring that Astera Labs’ fabric solutions perform at scale and deliver system-level performance across the most demanding AI and ML workloads. This role offers a unique opportunity to shape validation strategy for cutting-edge connectivity silicon and gain deep insight into next-generation AI infrastructure platforms. Your primary responsibility will be to build and lead a world-class validation organization tasked with validating all silicon, firmware, and system-level solutions at scale, ensuring performance, reliability, and production readiness across customer deployments.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Job Description\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Seeking a strong technical leader who has delivered multiple SoC products.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead and scale the system validation organization for Astera Labs\u0026#39; AI fabric portfolio, building a high-performing team across multiple concurrent product programs.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Understand the performance and functionality requirements of our AI fabric switches to enable customers to develop Data Center systems using Astera Labs\u0026#39; connectivity products for AI and ML applications.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Own comprehensive validation strategies for AI fabric switch products. Drive execution through scalable automation platforms and data-centric testing with automated reporting and specification compliance verification.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate cross-functionally with Architecture, Hardware, Firmware, and Software teams to influence product requirements and ensure validation excellence.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ensure timely bringup of new silicon and platforms, driving rootcause analysis and crossfunctional debug of hardware, firmware, and system issues.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deliver high confidence validation results that support product qualification, customer sampling, and mass production readiness.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Engage directly with key customers to understand their requirements and highlight the unique capabilities of Astera Labs\u0026#39; solutions.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;The ideal candidate brings deep expertise in silicon/system validation, a strong architectural mindset, and a proven ability to scale organizations in fastmoving, highperformance computing environments.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work closely with silicon design, architecture, Firmware, software engineering teams to ensure cohesive validation strategies.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive a culture of technical excellence, accountability, and continuous improvement.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Manage resource planning, and vendor/partner relationships.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Strong academic background in Electrical or Computer Engineering. Bachelor\u0026#39;s required, Master\u0026#39;s preferred.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;≥15 years\u0026#39; experience supporting or developing complex SoC/silicon products for Server, Storage, Networking applications and high-performance hardware companies.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;≥5 years hands-on experience with Silicon/System bring-up, validation, and debug, including in customer systems.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;≥2 years building high performance Engineering teams and validation methodologies.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep understanding of CPU, GPU, SoC, or AI/ML accelerator architectures, including memory subsystems, I/O, power management, and firmware interactions.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Expertise in validation methodologies: presilicon simulation/emulation, postsilicon bring-up, system validation, stress testing, and performance characterization.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong background in debug methodologies, lab infrastructure, and automation frameworks.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent communication skills and ability to influence executives and cross functional partners.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Experience:\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;≥5 years leading validation teams planning, execution and maintaining project visibility.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;≥10 years hands-on experience with Silicon/System bring-up, validation, and debug, including in customer systems.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Thorough knowledge of high-speed protocols like PCIe, CXL, NVMe, or Ethernet.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep understanding of High-Speed Signaling Principles and x86/ARM architecture, UEFI/Linux boot sequence.\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;The base salary range is $200,000 CAD - $250,000 CAD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. \u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025528005,"name":"Software Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4003931005,"name":"Vancouver","location":"Vancouver, Canada","child_ids":[],"parent_id":4004709005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4610812005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4395733005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"System Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Early Career","value_type":"single_select"}],"id":4610812005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2021","title":"System Validation Engineer (NCG 2026)","company_name":"Astera Labs","first_published":"2025-10-02T21:04:54-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;h2\u0026gt;About Astera Labs\u0026lt;/h2\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is a rapidly growing semiconductor company redefining connectivity for AI and cloud infrastructure. Our intelligent connectivity solutions—built on PCIe®, CXL™, Ethernet, and custom fabrics—enable seamless data movement across compute, memory, and storage. As part of our team, you\u0026#39;ll help validate the silicon that powers the world\u0026#39;s most advanced AI platforms.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;h2\u0026gt;Role Overview\u0026lt;/h2\u0026gt;\n\u0026lt;p\u0026gt;As an Entry-Level System Validation Engineer on the \u0026lt;strong\u0026gt;Taurus\u0026lt;/strong\u0026gt; team, you will validate Astera Labs\u0026#39; \u0026lt;strong\u0026gt;Taurus Ethernet Smart Cable Modules \u0026lt;/strong\u0026gt;and\u0026lt;strong\u0026gt; Taurus ASICs\u0026lt;/strong\u0026gt;. You\u0026#39;ll work on chip bring-up, system-level debug, and interoperability testing across real-world AI server and networking platforms, collaborating closely with electrical validation, firmware, and product applications teams.\u0026lt;/p\u0026gt;\n\u0026lt;h2\u0026gt;Key Responsibilities\u0026lt;/h2\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Execute system validation test plans for \u0026lt;strong\u0026gt;Taurus Ethernet Smart Cable Modules.\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Perform chip bring-up and debug for Taurus ASICs in lab environments using oscilloscopes, protocol analyzers, BERTs, and network switches\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Validate high-speed interconnects and AI fabrics in custom silicon, including signal integrity, link training, FEC stats, and protocol compliance\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with electrical validation, firmware, and product applications teams to root-cause issues and drive resolution\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Document validation results, debug findings, and contribute to bring-up notes and test reports\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Required Qualifications\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong academic foundation in circuit analysis, signals and systems, electromagnetics, or high‑speed digital design through coursework and labs\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with PCIe®, CXL™, or Ethernet standards\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with fundamental signal‑integrity concepts such as eye diagrams, jitter, noise, impedance, and transmission lines\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Exposure to electrical lab equipment (e.g., oscilloscopes, logic analyzers, network analyzers)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience using scripting or programming languages such as Python, MATLAB, TCL, or C/C++\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Comfortable working with lab tools and debugging hardware\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong analytical and communication skills\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Preferred Skills\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Exposure to post-silicon validation or bring-up of connectivity IP blocks\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Knowledge of signal integrity analysis and eye diagram interpretation\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with Linux systems, shell scripting, and version control (Git)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Understanding of AI workloads and how interconnect bandwidth impacts performance\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4671900005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4424159005,"location":{"name":"Vancouver, BC, Canada"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"System Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4671900005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2356","title":"System Validation Engineer (Various Levels)","company_name":"Astera Labs","first_published":"2026-03-11T15:06:29-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is seeking \u0026lt;strong\u0026gt;System Validation Engineers across multiple levels\u0026lt;/strong\u0026gt; to lead post‑silicon bring‑up and system validation for high‑performance PCIe and CXL memory expansion products used in AI and cloud data centers. You will design and execute validation plans, automate data‑centric test flows, drive root‑cause investigations across silicon, firmware, hardware, and systems, and work directly with customers to validate real world performance and interoperability.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;This role is based in our Vancouver office\u0026lt;/strong\u0026gt;, which is a strategic growth hub for Astera Labs\u0026#39; validation team. You\u0026#39;ll have the opportunity to be a foundational member of this expanding site while collaborating closely with our core team in San Jose. This is a unique chance to help shape the team\u0026#39;s culture, processes, and technical direction as we scale our validation capabilities to meet surging demand for AI infrastructure connectivity.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;What Success Looks Like:\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;New silicon and platforms brought up on schedule with reproducible validation results\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Automated test suites that reduce manual effort and provide clear pass/fail and performance metrics\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Rapid, data-backed root-cause resolution of system issues and strong customer satisfaction during integration\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Validation Planning \u0026amp;amp; Strategy\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Create comprehensive validation plans for AI fabric switch products covering functionality, performance, reliability, and interoperability\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Contribute to compliance testing strategies and adapt consortium test cases for execution from x86 and ARM platforms\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Produce clear, data-driven validation reports and status updates for internal stakeholders and customers\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Silicon \u0026amp;amp; System Bring-Up\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead silicon and platform bring-up activities, verify boot and runtime behavior on x86 and ARM systems\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ensure timely readiness for customer engagements and product launches\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Debug complex issues across PCIe, CXL, NVMe, Ethernet, firmware, and hardware layers using protocol analyzers, logic analyzers, and CPU-based tool suites\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Test Automation \u0026amp;amp; Infrastructure\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Develop robust, repeatable automation for IC and board testing with emphasis on execution efficiency, data collection, analysis, and automated reporting\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Design experiments to root-cause unexpected behavior and report results and specification compliance in an automated fashion\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Customer \u0026amp;amp; Cross-Functional Collaboration\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Collaborate directly with customers to capture system requirements, reproduce customer scenarios, and demonstrate product capabilities\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive cross-functional root-cause analysis with silicon, firmware, hardware, and system teams and document findings and corrective actions\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, Computer Engineering, or related field\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;2-12+ years of experience supporting or developing complex SoC or silicon products for server, storage, or networking domains (level dependent)\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Working understanding of x86 and ARM architectures and UEFI/Linux boot sequences\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Solid grasp of high-speed signaling principles\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience with high-speed protocols such as PCIe, CXL, NVMe, or Ethernet\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven experience in silicon and system bring-up, validation, and debug in lab and customer environments\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong Python automation skills for bench control, test orchestration, data analysis, and reporting\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with lab equipment including protocol analyzers, logic analyzers, in-circuit debuggers, and CPU-based tool suites\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong prioritization, planning, and independent execution skills with a customer-focused mindset\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026amp;nbsp;\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Master\u0026#39;s degree in Electrical Engineering, Computer Engineering, or related field\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Working knowledge of C or C++ for embedded firmware and device drivers\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with PCIe compliance standards and experience adapting consortium tests for platform execution\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Advanced understanding of memory architectures, high-speed signaling, and system boot flows\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Track record of influencing cross-functional teams and navigating complex matrixed organizations\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Entrepreneurial, can-do attitude with ability to think and act with the customer in mind\u0026amp;nbsp;\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;The base salary range for this role is $125,000 - $290,000 CAD depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025528005,"name":"Software Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4003931005,"name":"Vancouver","location":"Vancouver, Canada","child_ids":[],"parent_id":4004709005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4695548005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4435899005,"location":{"name":"Seattle, Washington, United States, Remote"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"Seattle","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Field Applications Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4695548005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2553","title":"Tech Lead Field Application Engineer","company_name":"Astera Labs","first_published":"2026-05-14T14:37:07-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Astera Labs is seeking a Tech Lead Field Application Engineer to serve as the technical bridge between our customers and engineering teams, supporting our industry-leading connectivity solutions across the Aries PCIe retimer, Scorpio Ethernet fabric switch, and Leo CXL memory connectivity platforms. This is a high-impact, customer-facing role where you\u0026#39;ll be embedded with hyperscaler and OEM partners, helping them design, validate, and deploy Astera Labs silicon into the AI infrastructure systems that are reshaping the data center landscape.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;As AI clusters scale to tens of thousands of GPUs and accelerators, the connectivity fabric binding compute, memory, and networking together has never been more critical. You\u0026#39;ll operate at the intersection of cutting-edge silicon and real-world system deployment—solving complex signal integrity, interoperability, and performance challenges that directly influence product roadmaps and customer success. This role demands a self-starter who thrives in ambiguity, can independently drive technical engagements, and is energized by frequent travel to customer sites.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Customer Technical Engagement\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Serve as the primary technical point of contact for strategic customers, providing deep application support for Aries, Scorpio, and Leo product families\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Drive board design reviews, schematic reviews, and system-level debug sessions with customer hardware and system development teams\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Deliver technical presentations, training sessions, and product demonstrations tailored to customer architectures and use cases\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;System Debug \u0026amp;amp; Enablement\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Lead hands-on debug of PCIe, Ethernet, and CXL/DDR memory connectivity issues in customer server and rack-scale platforms\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Collaborate with internal silicon, firmware, and applications engineering teams to resolve field issues and drive root cause analysis\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Develop and maintain application notes, reference designs, and technical collateral based on field learnings\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Strategic Feedback \u0026amp;amp; Product Influence\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Capture and communicate customer requirements, competitive insights, and system architecture trends to product management and engineering\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Represent the voice of the customer in internal roadmap discussions, helping shape next-generation connectivity solutions\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Identify new use cases and expansion opportunities within existing accounts\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering, Computer Engineering, or a related field\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;5+ years of experience in server hardware design, cloud system development (SysDev), or field application engineering\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Hands-on experience with PCIe protocol/physical layer including signal integrity fundamentals, link training, and debug\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Working knowledge of DDR memory subsystems and memory interface design or validation\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Self-starter mentality with the ability to work independently and drive customer engagements with minimal supervision\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Willingness to travel up to 40-50% to customer sites\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience with CXL protocol or CXL-enabled memory architectures\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Familiarity with Ethernet switch or NIC silicon in data center environments\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Experience working directly with hyperscaler or Tier-1 OEM customers\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Proficiency with lab equipment (oscilloscopes, protocol analyzers, BERT) and signal integrity tools\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Strong presentation and communication skills with the ability to convey complex technical concepts to diverse audiences\u0026lt;/li\u0026gt;\n\u0026lt;li class=\u0026quot;text-start \u0026quot;\u0026gt;Prior experience at a semiconductor company in an FAE or applications engineering capacity\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4134751005,"name":"Field Applications","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4017614005,"name":"Seattle","location":"Seattle","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4632063005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4405844005,"location":{"name":"San Jose, CA"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Program Management","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4632063005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2139","title":"Technical Chief of Staff for ASIC Engineering","company_name":"Astera Labs","first_published":"2025-11-19T19:24:24-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Summary\u0026lt;/strong\u0026gt;\u0026lt;br\u0026gt;We are seeking a technically strong Chief of Staff to the Head of Engineering who will also lead Engineering Program Management across Silicon Engineering. This role is a force-multiplier for Engineering leadership — driving org scale, decision velocity, and execution rigor. The ideal candidate brings deep technical fluency, structured problem-solving, and the ability to drive outcomes through influence rather than hierarchy. The role is fully in person in San Jose.\u0026lt;br\u0026gt;\u0026lt;br\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Responsibilities — What You Will Own\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;1) Chief of Staff to Head of Engineering\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;padding-left: 40px;\u0026quot;\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Drive operational cadence: engineering all hands, staff meetings, agenda/material prep, tech talks, university engagements, action follow-through, and leadership syncs.\u0026amp;nbsp;\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Frame and resolve high-leverage decisions — proactively surface blockers (technical, operational, organizational) before they escalate.\u0026amp;nbsp;\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Manage escalations and organizational friction — diagnose root causes, coordinate resolution paths, and ensure durable fixes.\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Partner cross-functionally with Hardware, Product, and Quality teams to ensure clarity of communication, alignment on priorities, and disciplined follow-through on decisions.\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Support org design, headcount planning, and hiring prioritization for engineering teams.\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Maintain alignment across functions through clear messaging and communication, validate exitance and validation of processes\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Navigate org dynamics, build trust, and constructively challenge assumptions; maintain psychological safety.\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Support the head of engineering with administrative and org related activities\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;2) Lead ASIC Tape out Management \u0026amp;nbsp;(Silicon Programs)\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;padding-left: 40px;\u0026quot;\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Status management — collect and track status across functions contributing to ASIC tapeouts.\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Milestone tracking — maintain methodology checklists and boundary agreements to ensure schedule adherence.\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;IP and vendor tracking — own visibility into IP deliveries, version inventory, vendor issues, and escalation loops.\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Quality \u0026amp;amp; documentation — monitor quality KPIs, ensure engineering documentation completeness.\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Requirements tracking — ensure PRDs/features are captured, tracked, baselined.\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Resource monitoring — track compute, hardware, storage consumption and thresholds.\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Internal reporting — generate status reporting for Silicon Engineering leadership.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;br\u0026gt;\u0026lt;strong\u0026gt;3) Influence Without Authority\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;padding-left: 40px;\u0026quot;\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Drive cross-engineering outcomes through credibility, clarity, and follow-through — not hierarchy.\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Create order in ambiguous spaces; shape scope where it is undefined.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;padding-left: 40px;\u0026quot;\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;10+ years in semiconductor/SoC/ASIC or adjacent high-complexity engineering environment (e.g., CPU/IP/System companies).\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Proven success in Chief of Staff, Staff Program Manager, TPM Director, or similar technical leadership-enablement role. \u0026amp;nbsp;\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Strong technical acumen — able to understand engineering trade-offs and make decisions with limited information, challenge assumptions, and earn credibility with senior ICs.\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Demonstrated experience running program cadence for complex silicon programs (tapeout, IP integration, etc.).\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Proven ability to organize complex workflows and drive consistent follow-through.\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;High EQ and organizational awareness; can navigate tension and align diverse viewpoints.\u0026amp;nbsp;\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Exceptional written/verbal communication, structured thinking, and execution discipline.\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Prior experience in leading RTL2GDSII chip design is a huge plus.\u0026lt;br\u0026gt;\u0026lt;br\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;What Success Looks Like\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p style=\u0026quot;padding-left: 40px;\u0026quot;\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Engineering leadership spends more time on strategic and technical decisions, less on coordination.\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Milestones hit with fewer escalations and clearer accountability.\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Status, risks, and decisions are crisp — never ad hoc or late.\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Teams feel supported, not policed — trust increases, friction decreases without compromising on accountability \u0026amp;nbsp;.\u0026lt;br\u0026gt;• \u0026amp;nbsp; \u0026amp;nbsp;Ambiguity decreases over time as clarity and execution rhythm scale with the org.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Salary range is $216,000 to $300,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4697334005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4436749005,"location":{"name":"San Jose, CA"},"metadata":[{"id":12122734005,"name":"Country","value":"United States","value_type":"single_select"},{"id":12122790005,"name":"City","value":"San Jose (HQ)","value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Design Verification","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4697334005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2563","title":"Technical Lead Design Verification Engineer ","company_name":"Astera Labs","first_published":"2026-05-28T14:54:54-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p data-renderer-start-pos=\u0026quot;1\u0026quot;\u0026gt;We are looking for\u0026amp;nbsp;\u0026lt;strong data-renderer-mark=\u0026quot;true\u0026quot;\u0026gt;a Technical Lead Design Verification Engineers\u0026lt;/strong\u0026gt; with a flair for being a code breaker, ability to come up hybrid mechanisms for verification of complex ASICs. Experience with System Verilog, C, C++, Python or other scripting languages would be a plus. Using your coding and problem-solving skills, you will contribute to the functional verification of the designs. You\u0026#39;ll be responsible for the full life cycle of verification, from planning to writing tests to debugging, collect and closing coverage. You’ll also work with the software and system validation teams to come up with test plans and executing them in emulation platforms.\u0026lt;/p\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;646\u0026quot;\u0026gt;\u0026lt;strong data-renderer-mark=\u0026quot;true\u0026quot;\u0026gt;Basic qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;670\u0026quot;\u0026gt;Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, and a Masters is preferred.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;813\u0026quot;\u0026gt;≥5 years’ experience verifying and validating complex SoC for Server, Storage, and Networking applications.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;924\u0026quot;\u0026gt;Knowledge of industry-standard simulators, revision control systems, and regression systems.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;1020\u0026quot;\u0026gt;Professional attitude with the ability to prioritize a dynamic list of multiple tasks, and work with minimal guidance and supervision.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;1158\u0026quot;\u0026gt;Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;1266\u0026quot;\u0026gt;Authorized to work in the US and start immediately.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;1321\u0026quot;\u0026gt;\u0026lt;strong data-renderer-mark=\u0026quot;true\u0026quot;\u0026gt;Required Experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;1344\u0026quot;\u0026gt;Experience with full verification lifecycle based on System Verilog/UVM/C/C++.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;1426\u0026quot;\u0026gt;Proven ability to mix and deploy hybrid techniques as in both directed and constrained random.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;1524\u0026quot;\u0026gt;Experience with different ways to bug and coverage hunting. Experience in formal methods is a plus.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;1627\u0026quot;\u0026gt;Must be able to work independently to develop test-plans, and related test-sequences to generate stimuli and work collaboratively with RTL designers to debug failures.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;1798\u0026quot;\u0026gt;Identify and write all types of coverage measures for stimulus and corner-cases. Close coverage to identify verification holes for high quality tape-out.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;1955\u0026quot;\u0026gt;\u0026lt;strong data-renderer-mark=\u0026quot;true\u0026quot;\u0026gt;Preferred Experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;1979\u0026quot;\u0026gt;Working experience with scripting tools (Perl/Python) to automate verification infrastructure.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;2077\u0026quot;\u0026gt;Prior experience using Verification IPs from 3rd party vendors with one or more communication protocols such as PCI-Express (Gen-3 and above), Ethernet, InfiniBand, DDR4/5, NVMe, USB, etc.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;2269\u0026quot;\u0026gt;Working experience with scripting tools (Perl/Python) to automate verification infrastructure.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;2367\u0026quot;\u0026gt;Experience with directed test based methodologies, cache verification and formal methods.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;2460\u0026quot;\u0026gt;The base salary range is USD 147,000.00 – USD 195,000.00. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. \u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4680229005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4428316005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Design Verification","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4680229005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2438","title":"Technical Lead Design Verification Engineer ","company_name":"Astera Labs","first_published":"2026-04-01T13:13:38-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p data-renderer-start-pos=\u0026quot;1\u0026quot;\u0026gt;We are looking for\u0026amp;nbsp;\u0026lt;strong data-renderer-mark=\u0026quot;true\u0026quot;\u0026gt;a Technical Lead Design Verification Engineers\u0026lt;/strong\u0026gt; with a flair for being a code breaker, ability to come up hybrid mechanisms for verification of complex ASICs. Experience with System Verilog, C, C++, Python or other scripting languages would be a plus. Using your coding and problem-solving skills, you will contribute to the functional verification of the designs. You\u0026#39;ll be responsible for the full life cycle of verification, from planning to writing tests to debugging, collect and closing coverage. You’ll also work with the software and system validation teams to come up with test plans and executing them in emulation platforms.\u0026lt;/p\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;646\u0026quot;\u0026gt;\u0026lt;strong data-renderer-mark=\u0026quot;true\u0026quot;\u0026gt;Basic qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;670\u0026quot;\u0026gt;Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, and a Masters is preferred.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;813\u0026quot;\u0026gt;≥5 years’ experience verifying and validating complex SoC for Server, Storage, and Networking applications.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;924\u0026quot;\u0026gt;Knowledge of industry-standard simulators, revision control systems, and regression systems.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;1020\u0026quot;\u0026gt;Professional attitude with the ability to prioritize a dynamic list of multiple tasks, and work with minimal guidance and supervision.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;1158\u0026quot;\u0026gt;Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;1266\u0026quot;\u0026gt;Authorized to work in the US and start immediately.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;1321\u0026quot;\u0026gt;\u0026lt;strong data-renderer-mark=\u0026quot;true\u0026quot;\u0026gt;Required Experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;1344\u0026quot;\u0026gt;Experience with full verification lifecycle based on System Verilog/UVM/C/C++.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;1426\u0026quot;\u0026gt;Proven ability to mix and deploy hybrid techniques as in both directed and constrained random.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;1524\u0026quot;\u0026gt;Experience with different ways to bug and coverage hunting. Experience in formal methods is a plus.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;1627\u0026quot;\u0026gt;Must be able to work independently to develop test-plans, and related test-sequences to generate stimuli and work collaboratively with RTL designers to debug failures.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;1798\u0026quot;\u0026gt;Identify and write all types of coverage measures for stimulus and corner-cases. Close coverage to identify verification holes for high quality tape-out.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;1955\u0026quot;\u0026gt;\u0026lt;strong data-renderer-mark=\u0026quot;true\u0026quot;\u0026gt;Preferred Experience\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;1979\u0026quot;\u0026gt;Working experience with scripting tools (Perl/Python) to automate verification infrastructure.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;2077\u0026quot;\u0026gt;Prior experience using Verification IPs from 3rd party vendors with one or more communication protocols such as PCI-Express (Gen-3 and above), Ethernet, InfiniBand, DDR4/5, NVMe, USB, etc.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;2269\u0026quot;\u0026gt;Working experience with scripting tools (Perl/Python) to automate verification infrastructure.\u0026lt;/li\u0026gt;\n\u0026lt;li data-renderer-start-pos=\u0026quot;2367\u0026quot;\u0026gt;Experience with directed test based methodologies, cache verification and formal methods.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p data-renderer-start-pos=\u0026quot;2460\u0026quot;\u0026gt;The base salary range is USD 160,000.00 – USD 195,000.00. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. \u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4672633005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4424486005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Design Verification","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4672633005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2365","title":"Technical Lead Digital Design Engineer","company_name":"Astera Labs","first_published":"2026-03-12T15:13:34-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Role Overview\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Join Astera Labs as a\u0026amp;nbsp;\u0026lt;strong\u0026gt;Technical Lead Digital Design Engineer\u0026lt;/strong\u0026gt;\u0026amp;nbsp;to architect and implement next-generation digital designs for high-performance AI connectivity solutions. You\u0026#39;ll own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, physical design, and DFT teams to deliver production-quality silicon supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;This role offers the opportunity to work on cutting-edge technology at the forefront of AI infrastructure, taking ownership of critical design challenges in a fast-paced, collaborative environment where your contributions directly impact products deployed by the world\u0026#39;s leading hyperscalers.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Design Ownership \u0026amp;amp; Execution\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Develop and implement complex digital blocks and subsystems by defining micro-architecture and driving RTL implementation with an exceptional power, performance and area trade-off using silicon technologies better than 7nm.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Lead efforts to achieve timing closure and implement Design-for-Test (DFT) features for optimal design performance\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive designs to production, ensuring accountability for quality, schedule, and overall design success\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Verification \u0026amp;amp; Integration\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Collaborate with verification teams to develop test plans, achieve coverage closure, and debug complex issues\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Own third-party IP integration and block-level verification through sign-off\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work closely with post-silicon teams to facilitate silicon bring-up and debug\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Technical Leadership\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Mentor junior engineers to develop their technical skills and expertise\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Actively contribute to the development and improvement of silicon development processes\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Drive design methodology improvements and CAD automation initiatives\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Bachelor\u0026#39;s degree in Electrical Engineering or equivalent\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;5+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Expertise in architecture definition, micro-architecture development, RTL coding, functional simulation, and synthesis\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of timing closure, gate-level simulation (GLS), and DFT implementation\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Deep expertise in at least one high-speed protocol: PCIe, CXL, Ethernet, DDR, or similar\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Production experience with advanced CMOS nodes (≤7nm)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency with Cadence and/or Synopsys digital design flows\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Master\u0026#39;s degree in Electrical Engineering or related field\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Track record of delivering multiple high-performance designs to production in data-center environments\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on collaboration with embedded firmware teams; understanding of firmware development challenges\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with standard embedded processor subsystems (RISC-V, Arm, etc.)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proven contributions to design methodology, CAD automation, or design infrastructure\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;Salary range is $160,000 to $195,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4641495005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4410296005,"location":{"name":"San Jose, CA "},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Hardware Engineering","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4641495005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2167","title":"Technical Lead Power Engineer ","company_name":"Astera Labs","first_published":"2025-12-29T16:50:19-05:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Overview:\u0026lt;/strong\u0026gt;\u0026lt;br\u0026gt;We are seeking a highly skilled and experienced Technical Lead Power Engineer to join our team. In this role, you will be responsible for designing and optimizing power delivery systems for our ASIC products, ensuring robust power integrity, and developing board-level designs. Your expertise will be crucial in selecting power components, collaborating with vendors, and utilizing industry-leading tools to deliver high-performance solutions.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Key Responsibilities:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Develop and optimize power conversion circuits, including DC-DC converters, voltage regulators, and power modules.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Design high-efficiency, high-reliability power circuits including:\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Buck / boost / buck-boost converters\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Multiphase regulators\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hot-swap, protection, and sequencing circuits\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Design and optimize power delivery for ASICs, ensuring stable voltage and current distribution across the board. Address power integrity challenges such as voltage ripple, noise, and impedance of mismatches.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Perform power integrity, transient response, stability, and thermal analysis.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Evaluate and select appropriate power components, such as voltage regulators, capacitors, and inductors, ensuring they meet performance, thermal, and reliability specifications. Also, will be asked to do the same evaluation on overall system level design components.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work closely with component vendors to identify and source the best power solutions, ensuring compatibility with our ASIC designs and meeting quality standards.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Work closely with cross-functional teams, including firmware, mechanical, and validation engineers, to integrate designs into complete systems.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Generate and maintain comprehensive design documentation, including, Specifications, schematics and BOMs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Conduct thorough debugging and analysis of power-related or system level issue utilizing lab equipment such as oscilloscopes and power analyzers to identify and resolve problems.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Education:\u0026lt;/strong\u0026gt; Bachelor’s or Master’s degree in electrical engineering or related field.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Experience:\u0026lt;/strong\u0026gt; 5-8 years of experience in power and board design engineering, with a focus on ASIC or high-speed digital designs.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Technical Skills:\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Proficiency in Cadence OrCAD and Allegro for schematic capture and PCB layout.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong understanding of power integrity principles and techniques.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience with power component selection and vendor collaboration.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on experience with debugging power-related issues using lab equipment.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Proficiency with lab equipment (oscilloscopes, electronic loads, spectrum analyzers).\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;li\u0026gt;\u0026lt;strong\u0026gt;Soft Skills:\u0026lt;/strong\u0026gt;\u0026lt;/li\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Excellent problem-solving and analytical skills.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong communication and teamwork abilities.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Ability to work in a fast-paced, collaborative environment.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Qualifications:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with high-speed interfaces such as PCIe, DDR, and USB.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with electromagnetic interference (EMI) and electromagnetic compatibility (EMC) considerations.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Familiarity with Design for Manufacturability (DFM) considerations.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience in thermal management and reliability analysis.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Why Join Us:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Work on cutting-edge ASIC designs in a collaborative and innovative environment.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Opportunity to influence power design strategies and contribute to product success.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Access to state-of-the-art tools and resources to enhance your skills and career growth.\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;If you are passionate about power and board design engineering and meet the qualifications outlined above, we encourage you to apply and become a key contributor to our team.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;Base pay range for this role is $170,000 - $195,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. \u0026amp;nbsp;\u0026lt;/p\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025526005,"name":"Hardware Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]},{"absolute_url":"https://job-boards.greenhouse.io/asteralabs/jobs/4680695005","data_compliance":[{"type":"gdpr","requires_consent":false,"requires_processing_consent":false,"requires_retention_consent":false,"retention_period":null,"demographic_data_consent_applies":false}],"education":"education_required","internal_job_id":4428444005,"location":{"name":"San Jose, California, United States"},"metadata":[{"id":12122734005,"name":"Country","value":null,"value_type":"single_select"},{"id":12122790005,"name":"City","value":null,"value_type":"single_select"},{"id":12303721005,"name":"HRIS Department","value":null,"value_type":"single_select"},{"id":7826080005,"name":"Job Family/Domain","value":"Engineering Operations","value_type":"single_select"},{"id":7826085005,"name":"Role Type","value":"Experienced","value_type":"single_select"}],"id":4680695005,"updated_at":"2026-06-07T13:39:36-04:00","requisition_id":"2444","title":"Technical Lead Product Engineer ","company_name":"Astera Labs","first_published":"2026-04-01T19:40:31-04:00","language":"en","application_deadline":null,"content":"\u0026lt;div class=\u0026quot;content-intro\u0026quot;\u0026gt;\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at \u0026lt;a id=\u0026quot;menurhut\u0026quot; class=\u0026quot;fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn\u0026quot; href=\u0026quot;http://www.asteralabs.com/\u0026quot; target=\u0026quot;_blank\u0026quot;\u0026gt;www.asteralabs.com\u0026lt;/a\u0026gt;.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Job Description:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;We are seeking an experienced and hands-on \u0026lt;strong\u0026gt;Technical Lead Product Engineer \u0026lt;/strong\u0026gt;to lead and develop next generation high-speed, high performance and low power semiconductor products in advanced process node. The ideal candidate possesses breadth of industry experience in high-speed product development in the field of product and/or test engineering, can apply fundamentals in circuit, ATE, and test program to aid problem solving, and is a self-driven, result focused go-getter in the pursuit of goals and objectives.\u0026lt;/p\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Basic Qualifications:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Minimum of 5 years of experience in the field of post silicon product development dealing with high-speed XCVR (product, test or validation)\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Experience in working with PCIe Gen3 and above\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Have gone through at least one cycle of full product development life cycle\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong academic/technical background in electrical or computer engineering; Bachelor’s is required; MS preferred\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong problem-solving skills that involve system level analysis with test hardware, test program and DUT.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Digital and analog circuit level understanding for DUT.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Excellent team player with great communication skills\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Professional attitude with the ability to prioritize a dynamic list of multiple tasks\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Required Experience\u0026lt;/strong\u0026gt;:\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Hands on experience with using the Advantest 93k ATE platform with specific skills updating ATE test programs for wafer sort and final test solutions\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands-on knowledge of NRZ/PAM4 SerDes protocols like PCIe (Gen3 and above), Ethernet (25G and above), etc. and/or memory interfaces such as (LP)DDR5/4.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Detailed mindset monitoring device ATE test yields, ATE test time, device quality and rolling out new ATE test programs using consistent BKMs\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Strong data analysis skills using tools such as JMP or Spotfire calculating limits and drawing conclusions\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Energetic work mindset meeting the demands of shipping quality parts to Astera Labs’ customers through the manufacturing stage of development\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;strong\u0026gt;Preferred Experience:\u0026lt;/strong\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;ul\u0026gt;\n\u0026lt;li\u0026gt;Working with silicon validation teams to ensure device performance meets production requirements.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Firmware development in C/C++, scripting in Python, or other equivalent programming experience.\u0026lt;/li\u0026gt;\n\u0026lt;li\u0026gt;Hands on experience in product/package qualification\u0026lt;/li\u0026gt;\n\u0026lt;/ul\u0026gt;\n\u0026lt;div\u0026gt;\n\u0026lt;p\u0026gt;\u0026lt;span data-teams=\u0026quot;true\u0026quot;\u0026gt;The base salary range is USD 160,00 - USD 195,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.\u0026lt;/span\u0026gt;\u0026lt;/p\u0026gt;\n\u0026lt;/div\u0026gt;\u0026lt;div class=\u0026quot;content-conclusion\u0026quot;\u0026gt;\u0026lt;p\u0026gt;We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\u0026lt;/p\u0026gt;\u0026lt;/div\u0026gt;","departments":[{"id":4025527005,"name":"ASIC Engineering","child_ids":[],"parent_id":4000196005}],"offices":[{"id":4000118005,"name":"San Jose","location":"San Jose, United States","child_ids":[],"parent_id":4019546005}]}],"meta":{"total":161}}